Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V4 19/34] UefiCpuPkg/CpuDxe: Add RISCV_EFI_BOOT_PROTOCOL support

["Chang, Abner" <abner.chang@amd.com>]

[AMD Official Use Only - General]

The implementation of RISCV_EFI_BOOT_PROTOCOL looks good and the copyright is clear. Thanks
Acked-by: Abner Chang <abner.chang@amd.com>

Abner

> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Sunil V L
> via groups.io
> Sent: Saturday, October 15, 2022 12:48 AM
> To: devel@edk2.groups.io
> Cc: Eric Dong <eric.dong@intel.com>; Ray Ni <ray.ni@intel.com>; Rahul
> Kumar <rahul1.kumar@intel.com>; Daniel Schaefer
> <git@danielschaefer.me>
> Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V4 19/34]
> UefiCpuPkg/CpuDxe: Add RISCV_EFI_BOOT_PROTOCOL support
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> REF:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076&amp;data=05%7C01%7Ca
> bner.chang%40amd.com%7C1585e32f06574b8131ef08daae046155%7C3dd89
> 61fe4884e608e11a82d994e183d%7C0%7C0%7C638013631208922591%7CUnkn
> own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=Zm3JNrM1BG0z
> o33Qpj1oCzgn6JcEgIB5gb40q2dUyZk%3D&amp;reserved=0
> 
> RISC-V UEFI platforms need to support RISCV_EFI_BOOT_PROTOCOL.
> Add the support for this protocol which is defined in the spec:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> ub.com%2Friscv-non-isa%2Friscv-
> uefi%2Freleases%2Fdownload%2F1.0.0%2FRISCV_UEFI_PROTOCOL-
> spec.pdf&amp;data=05%7C01%7Cabner.chang%40amd.com%7C1585e32f065
> 74b8131ef08daae046155%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C
> 0%7C638013631208922591%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLj
> AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%
> 7C%7C&amp;sdata=5CB%2F89Lz5OTmFZQaoCk17VbEiXu5ggPSgL0PVeuFPTM
> %3D&amp;reserved=0
> 
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Daniel Schaefer <git@danielschaefer.me>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  UefiCpuPkg/UefiCpuPkg.dsc          | 12 ++--
>  UefiCpuPkg/CpuDxe/CpuDxe.inf       |  3 +
>  UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 60 +++++++++++++++++++-
>  3 files changed, 68 insertions(+), 7 deletions(-)
> 
> diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index
> f694b3a77c2e..6ea90507e36f 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dsc
> +++ b/UefiCpuPkg/UefiCpuPkg.dsc
> @@ -122,9 +122,13 @@ [Components]
>    UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
>    UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
>    UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf
> -
> -[Components.IA32, Components.X64]
>    UefiCpuPkg/CpuDxe/CpuDxe.inf
> +
> +UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i
> nf
> +!if $(TOOL_CHAIN_TAG) != "XCODE5"
> +
> +UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi
> b.
> +inf
> +!endif
> +
> +[Components.IA32, Components.X64]
>    UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf {
>      <LibraryClasses>
> 
> NULL|UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLi
> b.inf
> @@ -141,10 +145,6 @@ [Components.IA32, Components.X64]
>    UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
>    UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
>    UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
> -
> UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.in
> f
> -!if $(TOOL_CHAIN_TAG) != "XCODE5"
> -
> UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib
> .inf
> -!endif
> 
> UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i
> nf
> 
> UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
> 
> UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHa
> ndlerLib.inf
> diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 235100d86274..b16b640946c6
> 100644
> --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> @@ -74,6 +74,9 @@ [Protocols]
>    gEfiMpServiceProtocolGuid                     ## PRODUCES
>    gEfiSmmBase2ProtocolGuid                      ## SOMETIMES_CONSUMES
> 
> +[Protocols.RISCV64]
> +  gRiscVEfiBootProtocolGuid                     ## PRODUCES
> +
>  [Guids]
>    gIdleLoopEventGuid                            ## CONSUMES           ## Event
>    gEfiVectorHandoffTableGuid                    ## SOMETIMES_CONSUMES ##
> SystemTable
> diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> index 9f557b776a09..7551e0653603 100644
> --- a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> @@ -2,6 +2,7 @@
>    RISC-V CPU DXE driver.
> 
>    Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All
> rights reserved.<BR>
> +  Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> + reserved.<BR>
> 
>    SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> @@ -14,6 +15,39 @@
>  //
>  STATIC BOOLEAN           mInterruptState = FALSE;
>  STATIC EFI_HANDLE        mCpuHandle      = NULL;
> +STATIC UINTN             mBootHartId;
> +RISCV_EFI_BOOT_PROTOCOL  gRiscvBootProtocol;
> +
> +/**
> +  Get the boot hartid
> +
> +  @param  This                   Protocol instance structure
> +  @param  BootHartId             Pointer to the Boot Hart ID variable
> +
> +  @retval EFI_SUCCESS            If BootHartId is returned
> +  @retval EFI_INVALID_PARAMETER  Either "BootHartId" is NULL or "This" is
> not
> +                                 a valid RISCV_EFI_BOOT_PROTOCOL instance.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +RiscvGetBootHartId (
> +  IN RISCV_EFI_BOOT_PROTOCOL  *This,
> +  OUT UINTN                   *BootHartId
> +  )
> +{
> +  if ((This != &gRiscvBootProtocol) || (BootHartId == NULL)) {
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  *BootHartId = mBootHartId;
> +  return EFI_SUCCESS;
> +}
> +
> +RISCV_EFI_BOOT_PROTOCOL  gRiscvBootProtocol = {
> +  RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION,
> +  RiscvGetBootHartId
> +};
> 
>  EFI_CPU_ARCH_PROTOCOL  gCpu = {
>    CpuFlushCpuDataCache,
> @@ -285,14 +319,38 @@ InitializeCpu (
>    )
>  {
>    EFI_STATUS                  Status;
> +  EFI_RISCV_FIRMWARE_CONTEXT  *FirmwareContext;
> 
> -  InitializeCpuExceptionHandlers(NULL);
> +  GetFirmwareContextPointer (&FirmwareContext);  ASSERT
> + (FirmwareContext != NULL);  if (FirmwareContext == NULL) {
> +    DEBUG ((DEBUG_ERROR, "Failed to get the pointer of
> EFI_RISCV_FIRMWARE_CONTEXT\n"));
> +    return EFI_NOT_FOUND;
> +  }
> +
> +  DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n",
> + __FUNCTION__, FirmwareContext));
> +
> +  mBootHartId = FirmwareContext->BootHartId;  DEBUG ((DEBUG_INFO, "
> %a:
> + mBootHartId = 0x%x.\n", __FUNCTION__, mBootHartId));
> +
> +  InitializeCpuExceptionHandlers (NULL);
> 
>    //
>    // Make sure interrupts are disabled
>    //
>    DisableInterrupts ();
> 
> +  //
> +  // Install Boot protocol
> +  //
> +  Status = gBS->InstallProtocolInterface (
> +                  &ImageHandle,
> +                  &gRiscVEfiBootProtocolGuid,
> +                  EFI_NATIVE_INTERFACE,
> +                  &gRiscvBootProtocol
> +                  );
> +  ASSERT_EFI_ERROR (Status);
> +
>    //
>    // Install CPU Architectural Protocol
>    //
> --
> 2.38.0
> 
> 
> 
> 
>