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charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only - General] Hi Sunil and UefiCpuPkg maintainers, For CpuDxe case, I think we should abstract CpuDxe to accommodate all proce= ssor architectures instead of having copy for each archs. CpuDxeCommon.c ca= n have the generic protocol structure and the installation functions, and C= puDxeCommon.h has the general definitions. So does CpuMp related files. Mov= e processor architecture dependent files to under arch folders. AMD may hav= e some differences with Intel so we will have CpuDxeAmd.inf under CpuDxe\. = AMD is revising SmmFeatureCpuLib base on the similar concept. I think this= makes the module looks simple and architectural. Furthermore, the similar = concept should apply to all modules (if necessary) under UefiCpuPkg. I think we should revise CpuDxe before adding new arch such as RISC-V and L= oongson64 to this module. Here is a BZ for UefiCpuPkg rearchitecture, https://bugzilla.tianocore.org/= show_bug.cgi?id=3D3860 Abner Something looks like below, CpuDxe\X86\Ia32\ \IA32\CpuAsm.asm \IA32\PageAttribute.c \X86\X64\ \X64\CpuAsm.asm \X64\PageAttribute.c \X86\CpuGdt.c \CpuGdt.h \CpuPageTable.C \CpuPageTableh.h \CpuDxe.c \RISCV\RISCV64\ \RISCV64\CpuDxe.h \CpuDxe.c \ARM\ARM\ \AARCH64\ \CpuDxe.c \CpuDxeCommon.c \CpuMpCommon.c \CpuDxeCommon.h \CpuMpCommon.h \CpuDxe.inf =20 > -----Original Message----- > From: Sunil V L > Sent: Wednesday, September 7, 2022 1:09 AM > To: devel@edk2.groups.io > Cc: Jian J Wang ; Liming Gao > ; Eric Dong ; Ray Ni > ; Rahul Kumar ; Debkumar De > ; Catharine West ; > Daniel Schaefer ; Chang, Abner > ; Leif Lindholm ; Ard > Biesheuvel ; Heinrich Schuchardt > ; Anup Patel > ; Sunil V L > Subject: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in > CpuDxe module >=20 > [CAUTION: External Email] >=20 > This DXE module initializes the RISC-V CPU by installing the CPU specific= ARCH > protocol handlers. This also initializes the RISCV_EFI_BOOT_PROTOCOL whic= h > is required on RISC-V platforms. >=20 > Signed-off-by: Sunil V L > --- > UefiCpuPkg/CpuDxe/CpuDxe.inf | 16 +- > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 337 > +++++++++++++++++++++++++++++ > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 200 +++++++++++++++++ > 3 files changed, 552 insertions(+), 1 deletion(-) create mode 100644 > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c > create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h >=20 > diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf > b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 4f2ea42f16..17cf2b1ecd 100644 > --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf > +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf > @@ -1,8 +1,12 @@ > ## @file >=20 > -# CPU driver installs CPU Architecture Protocol and CPU MP protocol. >=20 > +# On X86, CPU driver installs CPU Architecture Protocol and CPU MP > protocol. >=20 > +# >=20 > +# On RISC-V, CPU driver installs CPU Architecture Protocol and RISC-V > +boot >=20 > +# protocol >=20 > # >=20 > # Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved. >=20 > # Copyright (c) 2017, AMD Incorporated. All rights reserved.
>=20 > +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights > +reserved.
>=20 > # >=20 > # SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > # >=20 > @@ -44,6 +48,9 @@ > MtrrLib >=20 > UefiCpuLib >=20 >=20 >=20 > +[LibraryClasses.RISCV64] >=20 > + RiscVSbiLib >=20 > + >=20 > [Sources.IA32, Sources.X64] >=20 > CpuDxe.c >=20 > CpuDxe.h >=20 > @@ -62,11 +69,18 @@ > X64/CpuAsm.nasm >=20 > X64/PagingAttribute.c >=20 >=20 >=20 > +[Sources.RISCV64] >=20 > + RiscV64/CpuDxe.c >=20 > + RiscV64/CpuDxe.h >=20 > + >=20 > [Protocols] >=20 > gEfiCpuArchProtocolGuid ## PRODUCES >=20 > gEfiMpServiceProtocolGuid ## PRODUCES >=20 > gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES >=20 >=20 >=20 > +[Protocols.RISCV64] >=20 > + gRiscVEfiBootProtocolGuid ## PRODUCES >=20 > + >=20 > [Guids] >=20 > gIdleLoopEventGuid ## CONSUMES ##= Event >=20 > gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES ## > SystemTable >=20 > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c > new file mode 100644 > index 0000000000..4112b6b8c6 > --- /dev/null > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c > @@ -0,0 +1,337 @@ > +/** @file >=20 > + RISC-V CPU DXE driver. >=20 > + >=20 > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. > + All rights reserved.
>=20 > + Copyright (c) 2022, Ventana Micro Systems Inc. All rights > + reserved.
>=20 > + >=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include "CpuDxe.h" >=20 > + >=20 > +// >=20 > +// Global Variables >=20 > +// >=20 > +STATIC BOOLEAN mInterruptState =3D FALSE; >=20 > +STATIC EFI_HANDLE mCpuHandle =3D NULL; >=20 > +STATIC UINTN mBootHartId; >=20 > +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol; >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +RiscvGetBootHartId ( >=20 > + IN RISCV_EFI_BOOT_PROTOCOL *This, >=20 > + OUT UINTN *BootHartId >=20 > + ) >=20 > +{ >=20 > + if((This !=3D &gRiscvBootProtocol) || (BootHartId =3D=3D NULL)) { >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + *BootHartId =3D mBootHartId; >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol =3D { >=20 > + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION, >=20 > + RiscvGetBootHartId >=20 > +}; >=20 > + >=20 > +EFI_CPU_ARCH_PROTOCOL gCpu =3D { >=20 > + CpuFlushCpuDataCache, >=20 > + CpuEnableInterrupt, >=20 > + CpuDisableInterrupt, >=20 > + CpuGetInterruptState, >=20 > + CpuInit, >=20 > + CpuRegisterInterruptHandler, >=20 > + CpuGetTimerValue, >=20 > + CpuSetMemoryAttributes, >=20 > + 1, // NumberOfTimers >=20 > + 4 // DmaBufferAlignment >=20 > +}; >=20 > + >=20 > +// >=20 > +// CPU Arch Protocol Functions >=20 > +// >=20 > + >=20 > +/** >=20 > + Flush CPU data cache. If the instruction cache is fully coherent >=20 > + with all DMA operations then function can just return EFI_SUCCESS. >=20 > + >=20 > + @param This Protocol instance structure >=20 > + @param Start Physical address to start flushing from. >=20 > + @param Length Number of bytes to flush. Round up to chipse= t >=20 > + granularity. >=20 > + @param FlushType Specifies the type of flush operation to per= form. >=20 > + >=20 > + @retval EFI_SUCCESS If cache was flushed >=20 > + @retval EFI_UNSUPPORTED If flush type is not supported. >=20 > + @retval EFI_DEVICE_ERROR If requested range could not be flushed. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuFlushCpuDataCache ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This, >=20 > + IN EFI_PHYSICAL_ADDRESS Start, >=20 > + IN UINT64 Length, >=20 > + IN EFI_CPU_FLUSH_TYPE FlushType >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Enables CPU interrupts. >=20 > + >=20 > + @param This Protocol instance structure >=20 > + >=20 > + @retval EFI_SUCCESS If interrupts were enabled in the CPU >=20 > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CP= U. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuEnableInterrupt ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This >=20 > + ) >=20 > +{ >=20 > + EnableInterrupts (); >=20 > + mInterruptState =3D TRUE; >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Disables CPU interrupts. >=20 > + >=20 > + @param This Protocol instance structure >=20 > + >=20 > + @retval EFI_SUCCESS If interrupts were disabled in the CPU. >=20 > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the C= PU. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuDisableInterrupt ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This >=20 > + ) >=20 > +{ >=20 > + DisableInterrupts (); >=20 > + mInterruptState =3D FALSE; >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Return the state of interrupts. >=20 > + >=20 > + @param This Protocol instance structure >=20 > + @param State Pointer to the CPU's current interrupt = state >=20 > + >=20 > + @retval EFI_SUCCESS If interrupts were disabled in the CPU. >=20 > + @retval EFI_INVALID_PARAMETER State is NULL. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuGetInterruptState ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This, >=20 > + OUT BOOLEAN *State >=20 > + ) >=20 > +{ >=20 > + if (State =3D=3D NULL) { >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + *State =3D mInterruptState; >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Generates an INIT to the CPU. >=20 > + >=20 > + @param This Protocol instance structure >=20 > + @param InitType Type of CPU INIT to perform >=20 > + >=20 > + @retval EFI_SUCCESS If CPU INIT occurred. This value should neve= r be >=20 > + seen. >=20 > + @retval EFI_DEVICE_ERROR If CPU INIT failed. >=20 > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuInit ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This, >=20 > + IN EFI_CPU_INIT_TYPE InitType >=20 > + ) >=20 > +{ >=20 > + return EFI_UNSUPPORTED; >=20 > +} >=20 > + >=20 > +/** >=20 > + Registers a function to be called from the CPU interrupt handler. >=20 > + >=20 > + @param This Protocol instance structure >=20 > + @param InterruptType Defines which interrupt to hook. IA-32 >=20 > + valid range is 0x00 through 0xFF >=20 > + @param InterruptHandler A pointer to a function of type >=20 > + EFI_CPU_INTERRUPT_HANDLER that is > + called >=20 > + when a processor interrupt occurs. A > + null >=20 > + pointer is an error condition. >=20 > + >=20 > + @retval EFI_SUCCESS If handler installed or uninstalled. >=20 > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a > handler >=20 > + for InterruptType was previously instal= led. >=20 > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a > + handler for >=20 > + InterruptType was not previously instal= led. >=20 > + @retval EFI_UNSUPPORTED The interrupt specified by InterruptTyp= e >=20 > + is not supported. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuRegisterInterruptHandler ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This, >=20 > + IN EFI_EXCEPTION_TYPE InterruptType, >=20 > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler >=20 > + ) >=20 > +{ >=20 > + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler); >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns a timer value from one of the CPU's internal timers. There is > + no >=20 > + inherent time interval between ticks but is a function of the CPU > frequency. >=20 > + >=20 > + @param This - Protocol instance structure. >=20 > + @param TimerIndex - Specifies which CPU timer is requested. >=20 > + @param TimerValue - Pointer to the returned timer value. >=20 > + @param TimerPeriod - A pointer to the amount of time that pas= ses >=20 > + in femtoseconds (10-15) for each > + increment >=20 > + of TimerValue. If TimerValue does not >=20 > + increment at a predictable rate, then 0 > + is >=20 > + returned. The amount of time that has >=20 > + passed between two calls to > + GetTimerValue() >=20 > + can be calculated with the formula >=20 > + (TimerValue2 - TimerValue1) * TimerPerio= d. >=20 > + This parameter is optional and may be NU= LL. >=20 > + >=20 > + @retval EFI_SUCCESS - If the CPU timer count was returned. >=20 > + @retval EFI_UNSUPPORTED - If the CPU does not have any readable > timers. >=20 > + @retval EFI_DEVICE_ERROR - If an error occurred while reading the > timer. >=20 > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue > is NULL. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuGetTimerValue ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This, >=20 > + IN UINT32 TimerIndex, >=20 > + OUT UINT64 *TimerValue, >=20 > + OUT UINT64 *TimerPeriod OPTIONAL >=20 > + ) >=20 > +{ >=20 > + return EFI_UNSUPPORTED; >=20 > +} >=20 > + >=20 > +/** >=20 > + Implementation of SetMemoryAttributes() service of CPU Architecture > Protocol. >=20 > + >=20 > + This function modifies the attributes for the memory region specified > + by BaseAddress and >=20 > + Length from their current attributes to the attributes specified by > Attributes. >=20 > + >=20 > + @param This The EFI_CPU_ARCH_PROTOCOL instance. >=20 > + @param BaseAddress The physical address that is the start addres= s of a > memory region. >=20 > + @param Length The size in bytes of the memory region. >=20 > + @param Attributes The bit mask of attributes to set for the mem= ory > region. >=20 > + >=20 > + @retval EFI_SUCCESS The attributes were set for the memory r= egion. >=20 > + @retval EFI_ACCESS_DENIED The attributes for the memory resource > range specified by >=20 > + BaseAddress and Length cannot be modifie= d. >=20 > + @retval EFI_INVALID_PARAMETER Length is zero. >=20 > + Attributes specified an illegal > + combination of attributes that >=20 > + cannot be set together. >=20 > + @retval EFI_OUT_OF_RESOURCES There are not enough system > resources > + to modify the attributes of >=20 > + the memory resource range. >=20 > + @retval EFI_UNSUPPORTED The processor does not support one or > more bytes of the memory >=20 > + resource range specified by BaseAddress = and Length. >=20 > + The bit mask of attributes is not > + support for the memory resource >=20 > + range specified by BaseAddress and Lengt= h. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuSetMemoryAttributes ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This, >=20 > + IN EFI_PHYSICAL_ADDRESS BaseAddress, >=20 > + IN UINT64 Length, >=20 > + IN UINT64 Attributes >=20 > + ) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", > + __FUNCTION__)); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Initialize the state information for the CPU Architectural Protocol. >=20 > + >=20 > + @param ImageHandle Image handle this driver. >=20 > + @param SystemTable Pointer to the System Table. >=20 > + >=20 > + @retval EFI_SUCCESS Thread can be successfully created >=20 > + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure >=20 > + @retval EFI_DEVICE_ERROR Cannot create the thread >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +InitializeCpu ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN EFI_SYSTEM_TABLE *SystemTable >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; >=20 > + >=20 > + GetFirmwareContextPointer (&FirmwareContext); >=20 > + ASSERT (FirmwareContext !=3D NULL); >=20 > + if (FirmwareContext =3D=3D NULL) { >=20 > + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of > + EFI_RISCV_FIRMWARE_CONTEXT\n")); >=20 > + return EFI_NOT_FOUND; >=20 > + } >=20 > + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", > + __FUNCTION__, FirmwareContext)); >=20 > + >=20 > + mBootHartId =3D FirmwareContext->BootHartId; >=20 > + DEBUG ((DEBUG_INFO, " %a: mBootHartId =3D 0x%x.\n", __FUNCTION__, > + mBootHartId)); >=20 > + >=20 > + >=20 > + InitializeCpuExceptionHandlers(NULL); >=20 > + >=20 > + // >=20 > + // Make sure interrupts are disabled >=20 > + // >=20 > + DisableInterrupts (); >=20 > + >=20 > + Status =3D gBS->InstallProtocolInterface (&ImageHandle, >=20 > + &gRiscVEfiBootProtocolGuid, >=20 > + EFI_NATIVE_INTERFACE, >=20 > + &gRiscvBootProtocol >=20 > + ); >=20 > + >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + // >=20 > + // Install CPU Architectural Protocol >=20 > + // >=20 > + Status =3D gBS->InstallMultipleProtocolInterfaces ( >=20 > + &mCpuHandle, >=20 > + &gEfiCpuArchProtocolGuid, >=20 > + &gCpu, >=20 > + NULL >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + return Status; >=20 > +} >=20 > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h > new file mode 100644 > index 0000000000..f039759dbd > --- /dev/null > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h > @@ -0,0 +1,200 @@ > +/** @file >=20 > + RISC-V CPU DXE module header file. >=20 > + >=20 > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. > + All rights reserved.
>=20 > + Copyright (c) 2022, Ventana Micro Systems Inc. All rights > + reserved.
>=20 > + >=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#ifndef CPU_DXE_H_ >=20 > +#define CPU_DXE_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Flush CPU data cache. If the instruction cache is fully coherent >=20 > + with all DMA operations then function can just return EFI_SUCCESS. >=20 > + >=20 > + @param This Protocol instance structure >=20 > + @param Start Physical address to start flushing from. >=20 > + @param Length Number of bytes to flush. Round up to chipse= t >=20 > + granularity. >=20 > + @param FlushType Specifies the type of flush operation to per= form. >=20 > + >=20 > + @retval EFI_SUCCESS If cache was flushed >=20 > + @retval EFI_UNSUPPORTED If flush type is not supported. >=20 > + @retval EFI_DEVICE_ERROR If requested range could not be flushed. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuFlushCpuDataCache ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This, >=20 > + IN EFI_PHYSICAL_ADDRESS Start, >=20 > + IN UINT64 Length, >=20 > + IN EFI_CPU_FLUSH_TYPE FlushType >=20 > + ); >=20 > + >=20 > +/** >=20 > + Enables CPU interrupts. >=20 > + >=20 > + @param This Protocol instance structure >=20 > + >=20 > + @retval EFI_SUCCESS If interrupts were enabled in the CPU >=20 > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CP= U. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuEnableInterrupt ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This >=20 > + ); >=20 > + >=20 > +/** >=20 > + Disables CPU interrupts. >=20 > + >=20 > + @param This Protocol instance structure >=20 > + >=20 > + @retval EFI_SUCCESS If interrupts were disabled in the CPU. >=20 > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the C= PU. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuDisableInterrupt ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This >=20 > + ); >=20 > + >=20 > +/** >=20 > + Return the state of interrupts. >=20 > + >=20 > + @param This Protocol instance structure >=20 > + @param State Pointer to the CPU's current interrupt = state >=20 > + >=20 > + @retval EFI_SUCCESS If interrupts were disabled in the CPU. >=20 > + @retval EFI_INVALID_PARAMETER State is NULL. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuGetInterruptState ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This, >=20 > + OUT BOOLEAN *State >=20 > + ); >=20 > + >=20 > +/** >=20 > + Generates an INIT to the CPU. >=20 > + >=20 > + @param This Protocol instance structure >=20 > + @param InitType Type of CPU INIT to perform >=20 > + >=20 > + @retval EFI_SUCCESS If CPU INIT occurred. This value should neve= r be >=20 > + seen. >=20 > + @retval EFI_DEVICE_ERROR If CPU INIT failed. >=20 > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuInit ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This, >=20 > + IN EFI_CPU_INIT_TYPE InitType >=20 > + ); >=20 > + >=20 > +/** >=20 > + Registers a function to be called from the CPU interrupt handler. >=20 > + >=20 > + @param This Protocol instance structure >=20 > + @param InterruptType Defines which interrupt to hook. IA-32 >=20 > + valid range is 0x00 through 0xFF >=20 > + @param InterruptHandler A pointer to a function of type >=20 > + EFI_CPU_INTERRUPT_HANDLER that is > + called >=20 > + when a processor interrupt occurs. A > + null >=20 > + pointer is an error condition. >=20 > + >=20 > + @retval EFI_SUCCESS If handler installed or uninstalled. >=20 > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a > handler >=20 > + for InterruptType was previously instal= led. >=20 > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a > + handler for >=20 > + InterruptType was not previously instal= led. >=20 > + @retval EFI_UNSUPPORTED The interrupt specified by InterruptTyp= e >=20 > + is not supported. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuRegisterInterruptHandler ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This, >=20 > + IN EFI_EXCEPTION_TYPE InterruptType, >=20 > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler >=20 > + ); >=20 > + >=20 > +/** >=20 > + Returns a timer value from one of the CPU's internal timers. There is > + no >=20 > + inherent time interval between ticks but is a function of the CPU > frequency. >=20 > + >=20 > + @param This - Protocol instance structure. >=20 > + @param TimerIndex - Specifies which CPU timer is requested. >=20 > + @param TimerValue - Pointer to the returned timer value. >=20 > + @param TimerPeriod - A pointer to the amount of time that pas= ses >=20 > + in femtoseconds (10-15) for each > + increment >=20 > + of TimerValue. If TimerValue does not >=20 > + increment at a predictable rate, then 0 > + is >=20 > + returned. The amount of time that has >=20 > + passed between two calls to > + GetTimerValue() >=20 > + can be calculated with the formula >=20 > + (TimerValue2 - TimerValue1) * TimerPerio= d. >=20 > + This parameter is optional and may be NU= LL. >=20 > + >=20 > + @retval EFI_SUCCESS - If the CPU timer count was returned. >=20 > + @retval EFI_UNSUPPORTED - If the CPU does not have any readable > timers. >=20 > + @retval EFI_DEVICE_ERROR - If an error occurred while reading the > timer. >=20 > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue > is NULL. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuGetTimerValue ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This, >=20 > + IN UINT32 TimerIndex, >=20 > + OUT UINT64 *TimerValue, >=20 > + OUT UINT64 *TimerPeriod OPTIONAL >=20 > + ); >=20 > + >=20 > +/** >=20 > + Set memory cacheability attributes for given range of memeory. >=20 > + >=20 > + @param This Protocol instance structure >=20 > + @param BaseAddress Specifies the start address of the >=20 > + memory range >=20 > + @param Length Specifies the length of the memory rang= e >=20 > + @param Attributes The memory cacheability for the memory = range >=20 > + >=20 > + @retval EFI_SUCCESS If the cacheability of that memory rang= e is >=20 > + set successfully >=20 > + @retval EFI_UNSUPPORTED If the desired operation cannot be done >=20 > + @retval EFI_INVALID_PARAMETER The input parameter is not correct, >=20 > + such as Length =3D 0 >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CpuSetMemoryAttributes ( >=20 > + IN EFI_CPU_ARCH_PROTOCOL *This, >=20 > + IN EFI_PHYSICAL_ADDRESS BaseAddress, >=20 > + IN UINT64 Length, >=20 > + IN UINT64 Attributes >=20 > + ); >=20 > + >=20 > +#endif >=20 > -- > 2.25.1