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charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only - General] Same comment as 4/6. Please have AmdSmmCpuFeatureLib.c under SmmCpuFeatureLib. Thanks Abner > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Abdul > Lateef Attar via groups.io > Sent: Wednesday, January 11, 2023 2:16 PM > To: devel@edk2.groups.io > Cc: Attar, AbdulLateef (Abdul Lateef) ; > Grimes, Paul ; Kirkendall, Garrett > ; Chang, Abner ; > Eric Dong ; Ray Ni ; Rahul Kumar > > Subject: [edk2-devel] [PATCH v2 5/6] UefiCpuPkg: Initial implementation o= f > AMD's SmmCpuFeaturesLib >=20 > Caution: This message originated from an External Source. Use proper > caution when opening attachments, clicking links, or responding. >=20 >=20 > From: Abdul Lateef Attar >=20 > BZ: > https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fbugz > illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4182&data=3D05%7C01%7Cabner. > chang%40amd.com%7Caee2000763a74d2ed6a308daf39b9189%7C3dd8961fe4 > 884e608e11a82d994e183d%7C0%7C0%7C638090146744031405%7CUnknown > %7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha > WwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=3DWnv%2B%2BMaUiyF0gq > USzQCrcHcdkUVwZ5L%2BaDzjEvcjQS0%3D&reserved=3D0 >=20 > Adds initial defination for AMD's SmmCpuFeaturesLib library implementatio= n. > All function's body either empty or just returns value. Its initial skele= ton of > library implementation. >=20 > Cc: Paul Grimes > Cc: Garrett Kirkendall > Cc: Abner Chang > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Signed-off-by: Abdul Lateef Attar > --- > UefiCpuPkg/UefiCpuPkg.dsc | 8 + > .../AmdSmmCpuFeaturesLib.inf | 33 ++ > .../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 345 > ++++++++++++++++++ > 3 files changed, 386 insertions(+) > create mode 100644 > UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > create mode 100644 > UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c >=20 > diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index > 99f7532ce00b..1833d35fb354 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dsc > +++ b/UefiCpuPkg/UefiCpuPkg.dsc > @@ -178,6 +178,13 @@ [Components.IA32, Components.X64] > >=20 >=20 > SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFea > turesLibStm.inf >=20 > } >=20 > + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { >=20 > + >=20 > + FILE_GUID =3D B7242C74-BD21-49EE-84B4-07162E8C080D >=20 > + >=20 > + > + > SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCp > uFeatur > + esLib.inf >=20 > + > + > SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull > /Smm > + CpuPlatformHookLibNull.inf >=20 > + } >=20 > UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf >=20 > UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf >=20 > UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf >=20 > @@ -194,6 +201,7 @@ [Components.IA32, Components.X64] >=20 > UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultRep > ortLib/UnitTestResultReportLibConOut.inf >=20 > } >=20 >=20 > UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib. > inf >=20 > + UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf >=20 >=20 >=20 > [Components.X64] >=20 >=20 > UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHan > dlerLibUnitTest.inf >=20 > diff --git > a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > new file mode 100644 > index 000000000000..547b9cf15b84 > --- /dev/null > +++ > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > @@ -0,0 +1,33 @@ > +## @file >=20 > +# The CPU specific programming for PiSmmCpuDxeSmm module. >=20 > +# >=20 > +# Copyright (c) 2009 - 2016, Intel Corporation. All rights > +reserved.
>=20 > +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights > +reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D SmmCpuFeaturesLib >=20 > + MODULE_UNI_FILE =3D SmmCpuFeaturesLib.uni >=20 > + FILE_GUID =3D 5849E964-78EC-428E-8CBD-848A7E35913= 4 >=20 > + MODULE_TYPE =3D DXE_SMM_DRIVER >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D SmmCpuFeaturesLib >=20 > + CONSTRUCTOR =3D SmmCpuFeaturesLibConstructor >=20 > + >=20 > +[Sources] >=20 > + SmmCpuFeaturesLib.c >=20 > + SmmCpuFeaturesLibCommon.c >=20 > + Amd/SmmCpuFeaturesLib.c >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + UefiCpuPkg/UefiCpuPkg.dec >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + PcdLib >=20 > + MemoryAllocationLib >=20 > + DebugLib >=20 > diff --git > a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c > new file mode 100644 > index 000000000000..c74e1a0c0c5b > --- /dev/null > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c > @@ -0,0 +1,345 @@ > +/** @file >=20 > +Implementation specific to the SmmCpuFeatureLib library instance >=20 > +for AMD based platforms. >=20 > + >=20 > +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
>=20 > +Copyright (c) Microsoft Corporation.
>=20 > +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights > +reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Read an SMM Save State register on the target processor. If this > + function >=20 > + returns EFI_UNSUPPORTED, then the caller is responsible for reading > + the >=20 > + SMM Save Sate register. >=20 > + >=20 > + @param[in] CpuIndex The index of the CPU to read the SMM Save > + State. The >=20 > + value must be between 0 and the NumberOfCpus > + field in >=20 > + the System Management System Table (SMST). >=20 > + @param[in] Register The SMM Save State register to read. >=20 > + @param[in] Width The number of bytes to read from the CPU save > state. >=20 > + @param[out] Buffer Upon return, this holds the CPU register value r= ead >=20 > + from the save state. >=20 > + >=20 > + @retval EFI_SUCCESS The register was read from Save State. >=20 > + @retval EFI_INVALID_PARAMTER Buffer is NULL. >=20 > + @retval EFI_UNSUPPORTED This function does not support reading > Register. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SmmCpuFeaturesReadSaveStateRegister ( >=20 > + IN UINTN CpuIndex, >=20 > + IN EFI_SMM_SAVE_STATE_REGISTER Register, >=20 > + IN UINTN Width, >=20 > + OUT VOID *Buffer >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Writes an SMM Save State register on the target processor. If this > + function >=20 > + returns EFI_UNSUPPORTED, then the caller is responsible for writing > + the >=20 > + SMM Save Sate register. >=20 > + >=20 > + @param[in] CpuIndex The index of the CPU to write the SMM Save > + State. The >=20 > + value must be between 0 and the NumberOfCpus > + field in >=20 > + the System Management System Table (SMST). >=20 > + @param[in] Register The SMM Save State register to write. >=20 > + @param[in] Width The number of bytes to write to the CPU save stat= e. >=20 > + @param[in] Buffer Upon entry, this holds the new CPU register value= . >=20 > + >=20 > + @retval EFI_SUCCESS The register was written to Save State. >=20 > + @retval EFI_INVALID_PARAMTER Buffer is NULL. >=20 > + @retval EFI_UNSUPPORTED This function does not support writing > Register. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SmmCpuFeaturesWriteSaveStateRegister ( >=20 > + IN UINTN CpuIndex, >=20 > + IN EFI_SMM_SAVE_STATE_REGISTER Register, >=20 > + IN UINTN Width, >=20 > + IN CONST VOID *Buffer >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs library initialization. >=20 > + >=20 > + This initialization function contains common functionality shared > + betwen all >=20 > + library instance constructors. >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +CpuFeaturesLibInitialization ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > +} >=20 > + >=20 > +/** >=20 > + Called during the very first SMI into System Management Mode to > + initialize >=20 > + CPU features, including SMBASE, for the currently executing CPU. > + Since this >=20 > + is the first SMI, the SMRAM Save State Map is at the default address > + of >=20 > + AMD_SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. > The currently > + executing >=20 > + CPU is specified by CpuIndex and CpuIndex can be used to access > + information >=20 > + about the currently executing CPU in the ProcessorInfo array and the >=20 > + HotPlugCpuData data structure. >=20 > + >=20 > + @param[in] CpuIndex The index of the CPU to initialize. The va= lue >=20 > + must be between 0 and the NumberOfCpus > + field in >=20 > + the System Management System Table (SMST). >=20 > + @param[in] IsMonarch TRUE if the CpuIndex is the index of the CP= U > that >=20 > + was elected as monarch during System > + Management >=20 > + Mode initialization. >=20 > + FALSE if the CpuIndex is not the index of > + the CPU >=20 > + that was elected as monarch during System >=20 > + Management Mode initialization. >=20 > + @param[in] ProcessorInfo Pointer to an array of > EFI_PROCESSOR_INFORMATION >=20 > + structures. ProcessorInfo[CpuIndex] > + contains the >=20 > + information for the currently executing CPU= . >=20 > + @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA > structure > + that >=20 > + contains the ApidId and SmBase arrays. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +SmmCpuFeaturesInitializeProcessor ( >=20 > + IN UINTN CpuIndex, >=20 > + IN BOOLEAN IsMonarch, >=20 > + IN EFI_PROCESSOR_INFORMATION *ProcessorInfo, >=20 > + IN CPU_HOT_PLUG_DATA *CpuHotPlugData >=20 > + ) >=20 > +{ >=20 > +} >=20 > + >=20 > +/** >=20 > + This function updates the SMRAM save state on the currently executing > + CPU >=20 > + to resume execution at a specific address after an RSM instruction. > + This >=20 > + function must evaluate the SMRAM save state to determine the > + execution mode >=20 > + the RSM instruction resumes and update the resume execution address > + with >=20 > + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT > + restart >=20 > + flag in the SMRAM save state must always be cleared. This function > + returns >=20 > + the value of the instruction pointer from the SMRAM save state that > + was >=20 > + replaced. If this function returns 0, then the SMRAM save state was > + not >=20 > + modified. >=20 > + >=20 > + This function is called during the very first SMI on each CPU after >=20 > + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution > + mode >=20 > + to signal that the SMBASE of each CPU has been updated before the > + default >=20 > + SMBASE address is used for the first SMI to the next CPU. >=20 > + >=20 > + @param[in] CpuIndex The index of the CPU to hook. The= value >=20 > + must be between 0 and the > + NumberOfCpus >=20 > + field in the System Management > + System Table >=20 > + (SMST). >=20 > + @param[in] CpuState Pointer to SMRAM Save State Map fo= r the >=20 > + currently executing CPU. >=20 > + @param[in] NewInstructionPointer32 Instruction pointer to use if > + resuming to >=20 > + 32-bit execution mode from 64-bit = SMM. >=20 > + @param[in] NewInstructionPointer Instruction pointer to use if resu= ming > to >=20 > + same execution mode as SMM. >=20 > + >=20 > + @retval 0 This function did modify the SMRAM save state. >=20 > + @retval > 0 The original instruction pointer value from the SMRAM > + save state >=20 > + before it was replaced. >=20 > +**/ >=20 > +UINT64 >=20 > +EFIAPI >=20 > +SmmCpuFeaturesHookReturnFromSmm ( >=20 > + IN UINTN CpuIndex, >=20 > + IN SMRAM_SAVE_STATE_MAP *CpuState, >=20 > + IN UINT64 NewInstructionPointer32, >=20 > + IN UINT64 NewInstructionPointer >=20 > + ) >=20 > +{ >=20 > + return 0; >=20 > +} >=20 > + >=20 > +/** >=20 > + Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is >=20 > + returned, then a custom SMI handler is not provided by this library, >=20 > + and the default SMI handler must be used. >=20 > + >=20 > + @retval 0 Use the default SMI handler. >=20 > + @retval > 0 Use the SMI handler installed by > + SmmCpuFeaturesInstallSmiHandler() >=20 > + The caller is required to allocate enough SMRAM for each > + CPU to >=20 > + support the size of the custom SMI handler. >=20 > +**/ >=20 > +UINTN >=20 > +EFIAPI >=20 > +SmmCpuFeaturesGetSmiHandlerSize ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return 0; >=20 > +} >=20 > + >=20 > +/** >=20 > + Install a custom SMI handler for the CPU specified by CpuIndex. This > + function >=20 > + is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is > + greater >=20 > + than zero and is called by the CPU that was elected as monarch during > + System >=20 > + Management Mode initialization. >=20 > + >=20 > + @param[in] CpuIndex The index of the CPU to install the custom SMI > handler. >=20 > + The value must be between 0 and the > + NumberOfCpus field >=20 > + in the System Management System Table (SMST). >=20 > + @param[in] SmBase The SMBASE address for the CPU specified by > CpuIndex. >=20 > + @param[in] SmiStack The stack to use when an SMI is processed by the >=20 > + the CPU specified by CpuIndex. >=20 > + @param[in] StackSize The size, in bytes, if the stack used when an > + SMI is >=20 > + processed by the CPU specified by CpuIndex. >=20 > + @param[in] GdtBase The base address of the GDT to use when an SMI i= s >=20 > + processed by the CPU specified by CpuIndex. >=20 > + @param[in] GdtSize The size, in bytes, of the GDT used when an SMI = is >=20 > + processed by the CPU specified by CpuIndex. >=20 > + @param[in] IdtBase The base address of the IDT to use when an SMI i= s >=20 > + processed by the CPU specified by CpuIndex. >=20 > + @param[in] IdtSize The size, in bytes, of the IDT used when an SMI = is >=20 > + processed by the CPU specified by CpuIndex. >=20 > + @param[in] Cr3 The base address of the page tables to use when = an > SMI >=20 > + is processed by the CPU specified by CpuIndex. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +SmmCpuFeaturesInstallSmiHandler ( >=20 > + IN UINTN CpuIndex, >=20 > + IN UINT32 SmBase, >=20 > + IN VOID *SmiStack, >=20 > + IN UINTN StackSize, >=20 > + IN UINTN GdtBase, >=20 > + IN UINTN GdtSize, >=20 > + IN UINTN IdtBase, >=20 > + IN UINTN IdtSize, >=20 > + IN UINT32 Cr3 >=20 > + ) >=20 > +{ >=20 > +} >=20 > + >=20 > +/** >=20 > + Determines if MTRR registers must be configured to set SMRAM > + cache-ability >=20 > + when executing in System Management Mode. >=20 > + >=20 > + @retval TRUE MTRR registers must be configured to set SMRAM cache- > ability. >=20 > + @retval FALSE MTRR registers do not need to be configured to set > + SMRAM >=20 > + cache-ability. >=20 > +**/ >=20 > +BOOLEAN >=20 > +EFIAPI >=20 > +SmmCpuFeaturesNeedConfigureMtrrs ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return FALSE; >=20 > +} >=20 > + >=20 > +/** >=20 > + Disable SMRR register if SMRR is supported and > + SmmCpuFeaturesNeedConfigureMtrrs() >=20 > + returns TRUE. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +SmmCpuFeaturesDisableSmrr ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > +} >=20 > + >=20 > +/** >=20 > + Enable SMRR register if SMRR is supported and > + SmmCpuFeaturesNeedConfigureMtrrs() >=20 > + returns TRUE. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +SmmCpuFeaturesReenableSmrr ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > +} >=20 > + >=20 > +/** >=20 > + Processor specific hook point each time a CPU enters System Management > Mode. >=20 > + >=20 > + @param[in] CpuIndex The index of the CPU that has entered SMM. The > + value >=20 > + must be between 0 and the NumberOfCpus field in > + the >=20 > + System Management System Table (SMST). >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +SmmCpuFeaturesRendezvousEntry ( >=20 > + IN UINTN CpuIndex >=20 > + ) >=20 > +{ >=20 > +} >=20 > + >=20 > +/** >=20 > + Returns the current value of the SMM register for the specified CPU. >=20 > + If the SMM register is not supported, then 0 is returned. >=20 > + >=20 > + @param[in] CpuIndex The index of the CPU to read the SMM register. > + The >=20 > + value must be between 0 and the NumberOfCpus > + field in >=20 > + the System Management System Table (SMST). >=20 > + @param[in] RegName Identifies the SMM register to read. >=20 > + >=20 > + @return The value of the SMM register specified by RegName from the > + CPU >=20 > + specified by CpuIndex. >=20 > +**/ >=20 > +UINT64 >=20 > +EFIAPI >=20 > +SmmCpuFeaturesGetSmmRegister ( >=20 > + IN UINTN CpuIndex, >=20 > + IN SMM_REG_NAME RegName >=20 > + ) >=20 > +{ >=20 > + return 0; >=20 > +} >=20 > + >=20 > +/** >=20 > + Sets the value of an SMM register on a specified CPU. >=20 > + If the SMM register is not supported, then no action is performed. >=20 > + >=20 > + @param[in] CpuIndex The index of the CPU to write the SMM register. > + The >=20 > + value must be between 0 and the NumberOfCpus > + field in >=20 > + the System Management System Table (SMST). >=20 > + @param[in] RegName Identifies the SMM register to write. >=20 > + registers are read-only. >=20 > + @param[in] Value The value to write to the SMM register. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +SmmCpuFeaturesSetSmmRegister ( >=20 > + IN UINTN CpuIndex, >=20 > + IN SMM_REG_NAME RegName, >=20 > + IN UINT64 Value >=20 > + ) >=20 > +{ >=20 > +} >=20 > + >=20 > +/** >=20 > + Check to see if an SMM register is supported by a specified CPU. >=20 > + >=20 > + @param[in] CpuIndex The index of the CPU to check for SMM register > support. >=20 > + The value must be between 0 and the NumberOfCpus > + field >=20 > + in the System Management System Table (SMST). >=20 > + @param[in] RegName Identifies the SMM register to check for support. >=20 > + >=20 > + @retval TRUE The SMM register specified by RegName is supported by > the CPU >=20 > + specified by CpuIndex. >=20 > + @retval FALSE The SMM register specified by RegName is not supported > + by the >=20 > + CPU specified by CpuIndex. >=20 > +**/ >=20 > +BOOLEAN >=20 > +EFIAPI >=20 > +SmmCpuFeaturesIsSmmRegisterSupported ( >=20 > + IN UINTN CpuIndex, >=20 > + IN SMM_REG_NAME RegName >=20 > + ) >=20 > +{ >=20 > + return FALSE; >=20 > +} >=20 > -- > 2.25.1 >=20 >=20 >=20 >=20 >=20