* [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo
@ 2022-09-06 17:08 Sunil V L
2022-09-06 17:08 ` [RFC PATCH 01/17] MdePkg/Register: Add register definition header files for RISC-V Sunil V L
` (17 more replies)
0 siblings, 18 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
RISC-V ProcessorPkg and PlatformPkg were added in edk2-platforms
repo. But the recommendation was they should be added in edk2 repo
itself leveraging common packages as much as possible. This series
tries to create RISC-V specific modules and libraries under standard
packages.
The approach taken here is to do this in multiple phases.
In the first phase, the proposal adds support in edk2 repo without
disturbing the edk2-platforms repo. So, existing platforms will
continue to build in same way. Only qemu virt machine which is
being supported as part of this series will make use of the refactored
modules from edk2 repo.
In the second phase, plan is to use newly added edk2 packages as much as
possible in edk2-platforms and remove the redundant code from
edk2-platforms repo.
Generic platforms will NOT have integrated OpenSBI library in
EDK2. EDK2 should be booted only in S-mode by a separate M-mode
firmware on generic platforms. This doesn't exclude the vendors
to have the option of having M-mode functionality in EDK2 itself,
but they need to be special platforms and should be using edk2-platforms.
The reasons to take this design choice are,
1) The expectation that EDK2 always starts in M-mode would not
work in case of virtualization like KVM guests.
2) opensbi as M-mode firmware is one of the implementation of SBI
specification. It may be the only one open source implementation
as of today. But EDk2 should be able to boot with any M-mode firmware.
3) Integrating opensbi in edk2 is not trivial. opensbi repo is
frequently changing and it is not possible to upgrade this in
edk2 so frequently. Failing to upgrade, edk2 will be left behind
other firmware solutions in terms of functionality. Also, there
will be duplicate of efforts both in opensbi and edk2.
4) By making EDK2 as a payload of a previous stage M-mode firmware,
the design gets simplified in a great way. There is no need to handle
multiple CPUs entering EDK2, no wrapper libraries required etc.
5) This allows to follow the RISC-V S-mode calling convention which
passes BootHartId and the DTB to S-Mode. EDk2 can parse the DTB
instead of hardcoding many platform specific details in PCD variables.
In few places, a separate INF file is created
(ex: UefiCpuPkg/SecCore/SecCoreRiscV.inf) since there is not much to leverage
the code and may not suit to other architectures. But happy to do which is the
correct thing to do.
At high level the changes are spread in 3 main modules.
1) UefiCpuPkg
- Added new SEC(SecCore) for RISC-V
- Refactored and added RISC-V support in DxeCpuExceptionHandlerLib
- Refactored and added RISC-V support in CpuDxe
- Added PCD variable for RISC-V similar to existing
PcdCpuCoreCrystalClockFrequency
2) MdePkg
- Added RISC-V register definition headers
- Added definition of RISCV_EFI_BOOT_PROTOCOL GUID and header file
- BaseLib - enhanced to add interfaces to access the SSCRATCH register
- Added ArchTimerLib which can be leveraged by other architectures if needed.
- Added RiscVSbiLib specific to RISC-V to make SBI calls to M-mode firmware.
- Added ResetSystemLib which can be leveraged by other architectures.
- Added PlatformPeiLib which can be leveraged by other architectures.
3)MdeModulePkg
- Added PCD variables for RISC-V
- Added PlatformPei PEIM which can be leveraged by other architectures.
- Added TimerDxe module which can be leveraged by other architectures.
RISC-V virt needs following packages from ARM. Need feedback whether they can
be moved to a common location. Current RISC-V virt model DSC file include them
directly.
- ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
- ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
- ArmVirtPkg/Library/NorFlashQemuLib/NorFlashQemuLib.inf
I have not run CI/CD. Only CheckPatch is run and RISC-V build is tested. Once
we get consensus on the proposal, we can run additional tests required.
These changes are available at
https://github.com/vlsunil/edk2/tree/virt_refactor_smode_v1
The RISC-V virt machine support is added in edk2-platforms and changes
are available in below branch.
https://github.com/vlsunil/edk2-platforms/tree/virt_refactor_smode_v1
The chnges are tested on qemu but it needs an additional patch series.
https://lists.gnu.org/archive/html/qemu-devel/2022-09/msg00838.html
2) Build EDK2 for RISC-V
export WORKSPACE=`pwd`
export GCC5_RISCV64_PREFIX=riscv64-linux-gnu-
export PACKAGES_PATH=$WORKSPACE/edk2:$WORKSPACE/edk2-platforms
export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools
source edk2/edksetup.sh
make -C edk2/BaseTools clean
make -C edk2/BaseTools
make -C edk2/BaseTools/Source/C
source edk2/edksetup.sh BaseTools
build -a RISCV64 -p Platform/Qemu/RiscVVirt/RiscVVirt.dsc -t GCC5
3)Make the EDK2 image size to match with what qemu flash expects
truncate -s 32M Build/RiscVVirt/DEBUG_GCC5/FV/RISCV_VIRT.fd
4) Run
a) Boot to EFI shell (no -kernel / -initrd option)
qemu-system-riscv64 -nographic -drive
file=Build/RiscVVirt/DEBUG_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1
-machine virt -M 2G
b) With -kernel, -initrd and -pflash
qemu-system-riscv64 -nographic -drive
file=Build/RiscVVirt/DEBUG_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1
-machine virt -M 2G -kernel arch/riscv/boot/Image.gz -initrd rootfs.cpio
Sunil V L (17):
MdePkg/Register: Add register definition header files for RISC-V
MdePkg/MdePkg.dec: Add RISCV_EFI_BOOT_PROTOCOL GUID
MdePkg/Protocol: Add RiscVBootProtocol.h
MdeModulePkg/MdeModulePkg.dec: Add PCD variables for RISC-V
UefiCpuPkg.dec: Add PCD variable for RISC-V
MdePkg/BaseLib: RISC-V: Add generic CPU related functions
MdePkg: Add ArchTimerLib library
MdePkg: Add RiscVSbiLib Library for RISC-V
UefiCpuPkg/DxeCpuExceptionHandlerLib: Refactor to add other
architectures
UefiCpuPkg: Add RISC-V support in DxeCpuExceptionHandlerLib
MdePkg/Library: Add ResetSystemLib library
UefiCpuPkg/SecCore: Add SEC startup code for RISC-V
MdePkg: Add PlatformPeiLib library
MdeModulePkg/Universal: Add PlatformPei module for RISC-V
UefiCpuPkg/CpuDxe: Refactor to allow other CPU architectures
UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module
MdeModulePkg/Universal: Add TimerDxe module
MdeModulePkg/MdeModulePkg.dec | 13 +
.../Universal/PlatformPei/PlatformPei.inf | 65 ++
.../Universal/PlatformPei/RiscV64/Fv.c | 83 ++
.../Universal/PlatformPei/RiscV64/MemDetect.c | 179 ++++
.../Universal/PlatformPei/RiscV64/Platform.c | 372 ++++++++
.../Universal/PlatformPei/RiscV64/Platform.h | 97 +++
.../Universal/TimerDxe/RiscV64/Timer.c | 293 +++++++
.../Universal/TimerDxe/RiscV64/Timer.h | 174 ++++
MdeModulePkg/Universal/TimerDxe/Timer.uni | 15 +
MdeModulePkg/Universal/TimerDxe/TimerDxe.inf | 52 ++
.../Universal/TimerDxe/TimerExtra.uni | 13 +
MdePkg/Include/Library/BaseLib.h | 10 +
MdePkg/Include/Library/PlatformPeiLib.h | 15 +
MdePkg/Include/Library/RiscVSbiLib.h | 129 +++
MdePkg/Include/Protocol/RiscVBootProtocol.h | 35 +
MdePkg/Include/Register/RiscV64/RiscVAsm.h | 104 +++
MdePkg/Include/Register/RiscV64/RiscVConst.h | 46 +
.../Include/Register/RiscV64/RiscVEncoding.h | 129 +++
MdePkg/Include/Register/RiscV64/RiscVImpl.h | 24 +
MdePkg/Library/ArchTimerLib/ArchTimerLib.inf | 40 +
MdePkg/Library/ArchTimerLib/ArchTimerLib.uni | 14 +
.../ArchTimerLib/RiscV64/CpuTimerLib.c | 299 +++++++
MdePkg/Library/BaseLib/BaseLib.inf | 1 +
MdePkg/Library/BaseLib/RiscV64/CpuGen.S | 33 +
.../Library/PlatformPeiLib/PlatformPeiLib.inf | 40 +
.../PlatformPeiLib/RiscV64/PlatformPeiLib.c | 68 ++
.../Library/ResetSystemLib/ResetSystemLib.inf | 35 +
.../ResetSystemLib/RiscV64/ResetSystemLib.c | 128 +++
MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c | 228 +++++
MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf | 28 +
MdePkg/MdePkg.dec | 6 +
UefiCpuPkg/CpuDxe/CpuDxe.inf | 28 +-
UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 337 ++++++++
UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 200 +++++
.../DxeCpuExceptionHandlerLib.inf | 13 +-
.../RiscV64/CpuExceptionHandlerLib.c | 136 +++
.../RiscV64/CpuExceptionHandlerLib.h | 112 +++
.../RiscV64/SupervisorTrapHandler.S | 105 +++
UefiCpuPkg/SecCore/RiscV64/SecEntry.S | 23 +
UefiCpuPkg/SecCore/RiscV64/SecMain.c | 796 ++++++++++++++++++
UefiCpuPkg/SecCore/RiscV64/SecMain.h | 63 ++
UefiCpuPkg/SecCore/SecCoreRiscV.inf | 59 ++
UefiCpuPkg/UefiCpuPkg.dec | 3 +
43 files changed, 4634 insertions(+), 9 deletions(-)
create mode 100644 MdeModulePkg/Universal/PlatformPei/PlatformPei.inf
create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c
create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c
create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c
create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h
create mode 100644 MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.c
create mode 100644 MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.h
create mode 100644 MdeModulePkg/Universal/TimerDxe/Timer.uni
create mode 100644 MdeModulePkg/Universal/TimerDxe/TimerDxe.inf
create mode 100644 MdeModulePkg/Universal/TimerDxe/TimerExtra.uni
create mode 100644 MdePkg/Include/Library/PlatformPeiLib.h
create mode 100644 MdePkg/Include/Library/RiscVSbiLib.h
create mode 100644 MdePkg/Include/Protocol/RiscVBootProtocol.h
create mode 100644 MdePkg/Include/Register/RiscV64/RiscVAsm.h
create mode 100644 MdePkg/Include/Register/RiscV64/RiscVConst.h
create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h
create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h
create mode 100644 MdePkg/Library/ArchTimerLib/ArchTimerLib.inf
create mode 100644 MdePkg/Library/ArchTimerLib/ArchTimerLib.uni
create mode 100644 MdePkg/Library/ArchTimerLib/RiscV64/CpuTimerLib.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuGen.S
create mode 100644 MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf
create mode 100644 MdePkg/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c
create mode 100644 MdePkg/Library/ResetSystemLib/ResetSystemLib.inf
create mode 100644 MdePkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c
create mode 100644 MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c
create mode 100644 MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf
create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S
create mode 100644 UefiCpuPkg/SecCore/RiscV64/SecEntry.S
create mode 100644 UefiCpuPkg/SecCore/RiscV64/SecMain.c
create mode 100644 UefiCpuPkg/SecCore/RiscV64/SecMain.h
create mode 100644 UefiCpuPkg/SecCore/SecCoreRiscV.inf
--
2.25.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* [RFC PATCH 01/17] MdePkg/Register: Add register definition header files for RISC-V
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 02/17] MdePkg/MdePkg.dec: Add RISCV_EFI_BOOT_PROTOCOL GUID Sunil V L
` (16 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
Add register definitions and access routines for RISC-V. These
headers are leveraged from opensbi repo.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
MdePkg/Include/Register/RiscV64/RiscVAsm.h | 104 ++++++++++++++
MdePkg/Include/Register/RiscV64/RiscVConst.h | 46 +++++++
.../Include/Register/RiscV64/RiscVEncoding.h | 129 ++++++++++++++++++
MdePkg/Include/Register/RiscV64/RiscVImpl.h | 24 ++++
4 files changed, 303 insertions(+)
create mode 100644 MdePkg/Include/Register/RiscV64/RiscVAsm.h
create mode 100644 MdePkg/Include/Register/RiscV64/RiscVConst.h
create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h
create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h
diff --git a/MdePkg/Include/Register/RiscV64/RiscVAsm.h b/MdePkg/Include/Register/RiscV64/RiscVAsm.h
new file mode 100644
index 0000000000..e566061b73
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVAsm.h
@@ -0,0 +1,104 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __RISCV_ASM_H__
+#define __RISCV_ASM_H__
+
+#include <Register/RiscV64/RiscVEncoding.h>
+
+#ifdef __ASSEMBLER__
+#define __ASM_STR(x) x
+#else
+#define __ASM_STR(x) #x
+#endif
+
+#ifndef __ASSEMBLER__
+
+#define csr_swap(csr, val) \
+ ({ \
+ unsigned long __v = (unsigned long)(val); \
+ __asm__ __volatile__("csrrw %0, " __ASM_STR(csr) ", %1" \
+ : "=r"(__v) \
+ : "rK"(__v) \
+ : "memory"); \
+ __v; \
+ })
+
+#define csr_read(csr) \
+ ({ \
+ register unsigned long __v; \
+ __asm__ __volatile__("csrr %0, " __ASM_STR(csr) \
+ : "=r"(__v) \
+ : \
+ : "memory"); \
+ __v; \
+ })
+
+#define csr_write(csr, val) \
+ ({ \
+ unsigned long __v = (unsigned long)(val); \
+ __asm__ __volatile__("csrw " __ASM_STR(csr) ", %0" \
+ : \
+ : "rK"(__v) \
+ : "memory"); \
+ })
+
+#define csr_read_set(csr, val) \
+ ({ \
+ unsigned long __v = (unsigned long)(val); \
+ __asm__ __volatile__("csrrs %0, " __ASM_STR(csr) ", %1" \
+ : "=r"(__v) \
+ : "rK"(__v) \
+ : "memory"); \
+ __v; \
+ })
+
+#define csr_set(csr, val) \
+ ({ \
+ unsigned long __v = (unsigned long)(val); \
+ __asm__ __volatile__("csrs " __ASM_STR(csr) ", %0" \
+ : \
+ : "rK"(__v) \
+ : "memory"); \
+ })
+
+#define csr_read_clear(csr, val) \
+ ({ \
+ unsigned long __v = (unsigned long)(val); \
+ __asm__ __volatile__("csrrc %0, " __ASM_STR(csr) ", %1" \
+ : "=r"(__v) \
+ : "rK"(__v) \
+ : "memory"); \
+ __v; \
+ })
+
+#define csr_clear(csr, val) \
+ ({ \
+ unsigned long __v = (unsigned long)(val); \
+ __asm__ __volatile__("csrc " __ASM_STR(csr) ", %0" \
+ : \
+ : "rK"(__v) \
+ : "memory"); \
+ })
+
+#define wfi() \
+ do { \
+ __asm__ __volatile__("wfi" ::: "memory"); \
+ } while (0)
+
+#define ebreak() \
+ do { \
+ __asm__ __volatile__("ebreak" ::: "memory"); \
+ } while (0)
+
+
+#endif /* !__ASSEMBLER__ */
+
+#endif
diff --git a/MdePkg/Include/Register/RiscV64/RiscVConst.h b/MdePkg/Include/Register/RiscV64/RiscVConst.h
new file mode 100644
index 0000000000..ea7e151191
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVConst.h
@@ -0,0 +1,46 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2022 Ventana Micro Systems Inc. All rights reserved.<BR>
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ * This is leveraged from sbi_const.h in opensbi.
+ */
+
+#ifndef __RISCV_CONST_H__
+#define __RISCV_CONST_H__
+
+/*
+ * Some constant macros are used in both assembler and
+ * C code. Therefore we cannot annotate them always with
+ * 'UL' and other type specifiers unilaterally. We
+ * use the following macros to deal with this.
+ *
+ * Similarly, _AT() will cast an expression with a type in C, but
+ * leave it unchanged in asm.
+ */
+
+#ifdef __ASSEMBLER__
+#define _AC(X,Y) X
+#define _AT(T,X) X
+#else
+#define __AC(X,Y) (X##Y)
+#define _AC(X,Y) __AC(X,Y)
+#define _AT(T,X) ((T)(X))
+#endif
+
+#define _UL(x) (_AC(x, UL))
+#define _ULL(x) (_AC(x, ULL))
+
+#define _BITUL(x) (_UL(1) << (x))
+#define _BITULL(x) (_ULL(1) << (x))
+
+#define UL(x) (_UL(x))
+#define ULL(x) (_ULL(x))
+
+#define __STR(s) #s
+#define STRINGIFY(s) __STR(s)
+
+#endif
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
new file mode 100644
index 0000000000..5ad66ee7e7
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
@@ -0,0 +1,129 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __RISCV_ENCODING_H__
+#define __RISCV_ENCODING_H__
+
+#include <Register/RiscV64/RiscVConst.h>
+
+/* clang-format off */
+#define MSTATUS_SIE _UL(0x00000002)
+#define MSTATUS_MIE _UL(0x00000008)
+#define MSTATUS_SPIE_SHIFT 5
+#define MSTATUS_SPIE (_UL(1) << MSTATUS_SPIE_SHIFT)
+#define MSTATUS_UBE _UL(0x00000040)
+#define MSTATUS_MPIE _UL(0x00000080)
+#define MSTATUS_SPP_SHIFT 8
+#define MSTATUS_SPP (_UL(1) << MSTATUS_SPP_SHIFT)
+#define MSTATUS_MPP_SHIFT 11
+#define MSTATUS_MPP (_UL(3) << MSTATUS_MPP_SHIFT)
+
+#define SSTATUS_SIE MSTATUS_SIE
+#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT
+#define SSTATUS_SPIE MSTATUS_SPIE
+#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT
+#define SSTATUS_SPP MSTATUS_SPP
+
+#define IRQ_S_SOFT 1
+#define IRQ_VS_SOFT 2
+#define IRQ_M_SOFT 3
+#define IRQ_S_TIMER 5
+#define IRQ_VS_TIMER 6
+#define IRQ_M_TIMER 7
+#define IRQ_S_EXT 9
+#define IRQ_VS_EXT 10
+#define IRQ_M_EXT 11
+#define IRQ_S_GEXT 12
+#define IRQ_PMU_OVF 13
+
+#define MIP_SSIP (_UL(1) << IRQ_S_SOFT)
+#define MIP_VSSIP (_UL(1) << IRQ_VS_SOFT)
+#define MIP_MSIP (_UL(1) << IRQ_M_SOFT)
+#define MIP_STIP (_UL(1) << IRQ_S_TIMER)
+#define MIP_VSTIP (_UL(1) << IRQ_VS_TIMER)
+#define MIP_MTIP (_UL(1) << IRQ_M_TIMER)
+#define MIP_SEIP (_UL(1) << IRQ_S_EXT)
+#define MIP_VSEIP (_UL(1) << IRQ_VS_EXT)
+#define MIP_MEIP (_UL(1) << IRQ_M_EXT)
+#define MIP_SGEIP (_UL(1) << IRQ_S_GEXT)
+#define MIP_LCOFIP (_UL(1) << IRQ_PMU_OVF)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U _UL(0)
+#define PRV_S _UL(1)
+#define PRV_M _UL(3)
+
+#define SATP64_MODE _ULL(0xF000000000000000)
+#define SATP64_ASID _ULL(0x0FFFF00000000000)
+#define SATP64_PPN _ULL(0x00000FFFFFFFFFFF)
+
+#define SATP_MODE_OFF _UL(0)
+#define SATP_MODE_SV32 _UL(1)
+#define SATP_MODE_SV39 _UL(8)
+#define SATP_MODE_SV48 _UL(9)
+#define SATP_MODE_SV57 _UL(10)
+#define SATP_MODE_SV64 _UL(11)
+
+
+#define SATP_MODE SATP64_MODE
+
+/* ===== User-level CSRs ===== */
+
+/* User Counters/Timers */
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+
+/* ===== Supervisor-level CSRs ===== */
+
+/* Supervisor Trap Setup */
+#define CSR_SSTATUS 0x100
+#define CSR_SEDELEG 0x102
+#define CSR_SIDELEG 0x103
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+
+/* Supervisor Configuration */
+#define CSR_SENVCFG 0x10a
+
+/* Supervisor Trap Handling */
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_STVAL 0x143
+#define CSR_SIP 0x144
+
+/* Supervisor Protection and Translation */
+#define CSR_SATP 0x180
+
+/* ===== Trap/Exception Causes ===== */
+
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FETCH_ACCESS 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_STORE_ACCESS 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#define CAUSE_FETCH_PAGE_FAULT 0xc
+#define CAUSE_LOAD_PAGE_FAULT 0xd
+#define CAUSE_STORE_PAGE_FAULT 0xf
+#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14
+#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15
+#define CAUSE_VIRTUAL_INST_FAULT 0x16
+#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17
+
+#endif
diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
new file mode 100644
index 0000000000..e9ccd34039
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
@@ -0,0 +1,24 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __RISCV_IMPL_H_
+#define __RISCV_IMPL_H_
+
+#define _ASM_FUNC(Name, Section) \
+ .global Name ; \
+ .section #Section, "ax" ; \
+ .type Name, %function ; \
+ .p2align 2 ; \
+ Name:
+
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+#define RISCV_TIMER_COMPARE_BITS 32
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 02/17] MdePkg/MdePkg.dec: Add RISCV_EFI_BOOT_PROTOCOL GUID
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
2022-09-06 17:08 ` [RFC PATCH 01/17] MdePkg/Register: Add register definition header files for RISC-V Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 03/17] MdePkg/Protocol: Add RiscVBootProtocol.h Sunil V L
` (15 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL.
Add this protocol GUID definition.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
MdePkg/MdePkg.dec | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index f1ebf9e251..3010557bd8 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -1915,6 +1915,12 @@
## Include/Protocol/ShellDynamicCommand.h
gEfiShellDynamicCommandProtocolGuid = { 0x3c7200e9, 0x005f, 0x4ea4, {0x87, 0xde, 0xa3, 0xdf, 0xac, 0x8a, 0x27, 0xc3 }}
+ #
+ # Protocols defined for RISC-V systems
+ #
+ ## Include/Protocol/RiscVBootProtocol.h
+ gRiscVEfiBootProtocolGuid = { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf}}
+
#
# [Error.gEfiMdePkgTokenSpaceGuid]
# 0x80000001 | Invalid value provided.
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 03/17] MdePkg/Protocol: Add RiscVBootProtocol.h
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
2022-09-06 17:08 ` [RFC PATCH 01/17] MdePkg/Register: Add register definition header files for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 02/17] MdePkg/MdePkg.dec: Add RISCV_EFI_BOOT_PROTOCOL GUID Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 04/17] MdeModulePkg/MdeModulePkg.dec: Add PCD variables for RISC-V Sunil V L
` (14 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
RISC-V UEFI platforms need to implement RISCV_EFI_BOOT_PROTOCOL.
Add header file with the definitions of this protocol.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
MdePkg/Include/Protocol/RiscVBootProtocol.h | 35 +++++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 MdePkg/Include/Protocol/RiscVBootProtocol.h
diff --git a/MdePkg/Include/Protocol/RiscVBootProtocol.h b/MdePkg/Include/Protocol/RiscVBootProtocol.h
new file mode 100644
index 0000000000..7ceb7d8309
--- /dev/null
+++ b/MdePkg/Include/Protocol/RiscVBootProtocol.h
@@ -0,0 +1,35 @@
+
+/** @file
+ RISC-V Boot Protocol mandatory for RISC-V UEFI platforms.
+
+ Specification available at
+ https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RISCV_UEFI_PROTOCOL-spec.pdf
+
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _RISCV_BOOT_PROTOCOL_H_
+#define _RISCV_BOOT_PROTOCOL_H_
+
+//extern EFI_GUID gRiscVEfiBootProtocolGuid;
+
+typedef struct _RISCV_EFI_BOOT_PROTOCOL RISCV_EFI_BOOT_PROTOCOL;
+
+#define RISCV_EFI_BOOT_PROTOCOL_REVISION 0x00010000
+#define RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION \
+ RISCV_EFI_BOOT_PROTOCOL_REVISION
+
+typedef EFI_STATUS
+(EFIAPI *EFI_GET_BOOT_HARTID) (
+ IN RISCV_EFI_BOOT_PROTOCOL *This,
+ OUT UINTN *BootHartId
+ );
+
+typedef struct _RISCV_EFI_BOOT_PROTOCOL {
+ UINT64 Revision;
+ EFI_GET_BOOT_HARTID GetBootHartId;
+} RISCV_EFI_BOOT_PROTOCOL;
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 04/17] MdeModulePkg/MdeModulePkg.dec: Add PCD variables for RISC-V
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (2 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 03/17] MdePkg/Protocol: Add RiscVBootProtocol.h Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 05/17] UefiCpuPkg.dec: Add PCD variable " Sunil V L
` (13 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
Add few PCD variables for RISC-V platforms to indicate the
memory locations of the firmware volumes, temporary RAM etc.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
MdeModulePkg/MdeModulePkg.dec | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index 7d98910832..557fc2f3d4 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -2176,5 +2176,18 @@
# @Prompt 64bit VPD base address.
gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress64|0x0|UINT64|0x00030006
+[PcdsFixedAtBuild.RISCV64]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSecMemFvBase|0|UINT32|0x50000000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSecMemFvSize|0|UINT32|0x50000001
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvBase|0|UINT32|0x50000003
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvSize|0|UINT32|0x50000004
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvBase|0|UINT32|0x50000005
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvSize|0|UINT32|0x50000006
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x50000007
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x50000008
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x50000009
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSecPeiTempRamBase|0|UINT32|0x5000000a
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSecPeiTempRamSize|0|UINT32|0x5000000b
+
[UserExtensions.TianoCore."ExtraFiles"]
MdeModulePkgExtra.uni
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 05/17] UefiCpuPkg.dec: Add PCD variable for RISC-V
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (3 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 04/17] MdeModulePkg/MdeModulePkg.dec: Add PCD variables for RISC-V Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 06/17] MdePkg/BaseLib: RISC-V: Add generic CPU related functions Sunil V L
` (12 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
RISC-V platforms need PCD variable to indicate the mtimer
frequency which will be consumed by CpuDxe and TimerLib.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
UefiCpuPkg/UefiCpuPkg.dec | 3 +++
1 file changed, 3 insertions(+)
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 718323d904..5e94bde5fe 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -350,6 +350,9 @@
# @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
+[PcdsFixedAtBuild.RISCV64]
+ gUefiCpuPkgTokenSpaceGuid.PcdRiscVTimerFrequencyInHz|0|UINT32|0x50000000
+
[PcdsDynamic, PcdsDynamicEx]
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
# @Prompt The pointer to a CPU S3 data buffer.
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 06/17] MdePkg/BaseLib: RISC-V: Add generic CPU related functions
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (4 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 05/17] UefiCpuPkg.dec: Add PCD variable " Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 07/17] MdePkg: Add ArchTimerLib library Sunil V L
` (11 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
EDK2 in S-mode needs to use SSCRATCH register. Implement functions
to set/get the SSCRATCH register.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
MdePkg/Include/Library/BaseLib.h | 10 ++++++++
MdePkg/Library/BaseLib/BaseLib.inf | 1 +
MdePkg/Library/BaseLib/RiscV64/CpuGen.S | 33 +++++++++++++++++++++++++
3 files changed, 44 insertions(+)
create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuGen.S
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index a6f9a194ef..a742de61a4 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -150,6 +150,16 @@ typedef struct {
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+VOID
+RiscVSetSupervisorScratch (
+ UINT64
+ );
+
+UINT64
+RiscVGetSupervisorScratch (
+ VOID
+ );
+
#endif // defined (MDE_CPU_RISCV64)
//
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 6be5be9428..5429329e39 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -401,6 +401,7 @@
RiscV64/RiscVCpuPause.S | GCC
RiscV64/RiscVInterrupt.S | GCC
RiscV64/FlushCache.S | GCC
+ RiscV64/CpuGen.S | GCC
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuGen.S b/MdePkg/Library/BaseLib/RiscV64/CpuGen.S
new file mode 100644
index 0000000000..d11929cf32
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/CpuGen.S
@@ -0,0 +1,33 @@
+//------------------------------------------------------------------------------
+//
+// Generic CPU related functions for RISC-V
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+#include <Register/RiscV64/RiscVAsm.h>
+#include <Register/RiscV64/RiscVImpl.h>
+
+.data
+.align 3
+.section .text
+
+//
+// Set Supervisor mode scratch.
+// @param a0 : Value set to Supervisor mode scratch
+//
+ASM_FUNC (RiscVSetSupervisorScratch)
+ csrrw a1, CSR_SSCRATCH, a0
+ ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode scratch
+//
+ASM_FUNC (RiscVGetSupervisorScratch)
+ csrr a0, CSR_SSCRATCH
+ ret
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 07/17] MdePkg: Add ArchTimerLib library
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (5 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 06/17] MdePkg/BaseLib: RISC-V: Add generic CPU related functions Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 08/17] MdePkg: Add RiscVSbiLib Library for RISC-V Sunil V L
` (10 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
This library implements the TimerLib.h functionality. This library
is similar to CpuTimerLib but needs the library constructor.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
MdePkg/Library/ArchTimerLib/ArchTimerLib.inf | 40 +++
MdePkg/Library/ArchTimerLib/ArchTimerLib.uni | 14 +
.../ArchTimerLib/RiscV64/CpuTimerLib.c | 299 ++++++++++++++++++
3 files changed, 353 insertions(+)
create mode 100644 MdePkg/Library/ArchTimerLib/ArchTimerLib.inf
create mode 100644 MdePkg/Library/ArchTimerLib/ArchTimerLib.uni
create mode 100644 MdePkg/Library/ArchTimerLib/RiscV64/CpuTimerLib.c
diff --git a/MdePkg/Library/ArchTimerLib/ArchTimerLib.inf b/MdePkg/Library/ArchTimerLib/ArchTimerLib.inf
new file mode 100644
index 0000000000..b61ae58d01
--- /dev/null
+++ b/MdePkg/Library/ArchTimerLib/ArchTimerLib.inf
@@ -0,0 +1,40 @@
+## @file
+# Timer Library Instance which needs a constructor for the architecture.
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Ventana Micro System Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = ArchTimerLib
+ FILE_GUID = D3CF51A9-1CEA-4776-A8AB-CCFD14D7DAAF
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = TimerLib
+ MODULE_UNI_FILE = ArchTimerLib.uni
+ CONSTRUCTOR = ArchTimerLibConstructor
+
+[Sources.RISCV64]
+ RiscV64/CpuTimerLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ FdtLib
+ HobLib
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdRiscVTimerFrequencyInHz ## CONSUMES
+
+[Guids]
+ gFdtHobGuid
diff --git a/MdePkg/Library/ArchTimerLib/ArchTimerLib.uni b/MdePkg/Library/ArchTimerLib/ArchTimerLib.uni
new file mode 100644
index 0000000000..1c900bea42
--- /dev/null
+++ b/MdePkg/Library/ArchTimerLib/ArchTimerLib.uni
@@ -0,0 +1,14 @@
+// /** @file
+// Base CPU Timer Library
+//
+// Provides basic timer support using architecture specific methods.
+//
+// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_MODULE_ABSTRACT #language en-US "CPU Timer Library"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Provides basic timer support using architecture specific methods"
diff --git a/MdePkg/Library/ArchTimerLib/RiscV64/CpuTimerLib.c b/MdePkg/Library/ArchTimerLib/RiscV64/CpuTimerLib.c
new file mode 100644
index 0000000000..a81ac8c37c
--- /dev/null
+++ b/MdePkg/Library/ArchTimerLib/RiscV64/CpuTimerLib.c
@@ -0,0 +1,299 @@
+/** @file
+ RISC-V instance of Timer Library.
+
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/HobLib.h>
+#include <Guid/FdtHob.h>
+#include <Register/RiscV64/RiscVAsm.h>
+#include <Register/RiscV64/RiscVImpl.h>
+#include <libfdt.h>
+
+
+STATIC UINT32 mTimeBaseFrequency;
+STATIC BOOLEAN mTimeBaseFreqInitialized;
+
+UINT32
+InternalGetTimerFrequency(
+ VOID
+ )
+{
+ return mTimeBaseFrequency;
+}
+
+
+/**
+ Stalls the CPU for at least the given number of ticks.
+
+ Stalls the CPU for at least the given number of ticks. It's invoked by
+ MicroSecondDelay() and NanoSecondDelay().
+
+ @param Delay A period of time to delay in ticks.
+
+**/
+VOID
+InternalRiscVTimerDelay (
+ IN UINT32 Delay
+ )
+{
+ UINT32 Ticks;
+ UINT32 Times;
+
+ Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
+ Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
+ do {
+ //
+ // The target timer count is calculated here
+ //
+ Ticks = csr_read(CSR_TIME) + Delay;
+ Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
+ while (((Ticks - csr_read(CSR_TIME)) & (1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
+ CpuPause ();
+ }
+ } while (Times-- > 0);
+}
+
+/**
+ Stalls the CPU for at least the given number of microseconds.
+
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+ @param MicroSeconds The minimum number of microseconds to delay.
+
+ @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+ IN UINTN MicroSeconds
+ )
+{
+ InternalRiscVTimerDelay (
+ (UINT32)DivU64x32 (
+ MultU64x32 (
+ MicroSeconds,
+ InternalGetTimerFrequency()
+ ),
+ 1000000u
+ )
+ );
+ return MicroSeconds;
+}
+
+/**
+ Stalls the CPU for at least the given number of nanoseconds.
+
+ Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+ @param NanoSeconds The minimum number of nanoseconds to delay.
+
+ @return NanoSeconds
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+ IN UINTN NanoSeconds
+ )
+{
+ InternalRiscVTimerDelay (
+ (UINT32)DivU64x32 (
+ MultU64x32 (
+ NanoSeconds,
+ InternalGetTimerFrequency()
+ ),
+ 1000000000u
+ )
+ );
+ return NanoSeconds;
+}
+
+/**
+ Retrieves the current value of a 64-bit free running performance counter.
+
+ Retrieves the current value of a 64-bit free running performance counter. The
+ counter can either count up by 1 or count down by 1. If the physical
+ performance counter counts by a larger increment, then the counter values
+ must be translated. The properties of the counter can be retrieved from
+ GetPerformanceCounterProperties().
+
+ @return The current value of the free running performance counter.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounter (
+ VOID
+ )
+{
+ return (UINT64)csr_read (CSR_TIME);
+}
+
+/**return
+ Retrieves the 64-bit frequency in Hz and the range of performance counter
+ values.
+
+ If StartValue is not NULL, then the value that the performance counter starts
+ with immediately after is it rolls over is returned in StartValue. If
+ EndValue is not NULL, then the value that the performance counter end with
+ immediately before it rolls over is returned in EndValue. The 64-bit
+ frequency of the performance counter in Hz is always returned. If StartValue
+ is less than EndValue, then the performance counter counts up. If StartValue
+ is greater than EndValue, then the performance counter counts down. For
+ example, a 64-bit free running counter that counts up would have a StartValue
+ of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
+ that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
+
+ @param StartValue The value the performance counter starts with when it
+ rolls over.
+ @param EndValue The value that the performance counter ends with before
+ it rolls over.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounterProperties (
+ OUT UINT64 *StartValue, OPTIONAL
+ OUT UINT64 *EndValue OPTIONAL
+ )
+{
+ if (StartValue != NULL) {
+ *StartValue = 0;
+ }
+
+ if (EndValue != NULL) {
+ *EndValue = 32 - 1;
+ }
+
+ return InternalGetTimerFrequency();
+}
+
+/**
+ Converts elapsed ticks of performance counter to time in nanoseconds.
+
+ This function converts the elapsed ticks of running performance counter to
+ time value in unit of nanoseconds.
+
+ @param Ticks The number of elapsed ticks of running performance counter.
+
+ @return The elapsed time in nanoseconds.
+
+**/
+UINT64
+EFIAPI
+GetTimeInNanoSecond (
+ IN UINT64 Ticks
+ )
+{
+ UINT64 NanoSeconds;
+ UINT32 Remainder;
+
+ //
+ // Ticks
+ // Time = --------- x 1,000,000,000
+ // Frequency
+ //
+ NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, InternalGetTimerFrequency(), &Remainder), 1000000000u);
+
+ //
+ // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000)
+ // will not overflow 64-bit.
+ //
+ NanoSeconds += DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u), InternalGetTimerFrequency());
+
+ return NanoSeconds;
+}
+
+STATIC
+RETURN_STATUS
+EFIAPI
+FdtInitializeTimerFrequency (
+ VOID
+ )
+{
+ VOID *Hob;
+ VOID *Fdt;
+ INT32 CpusNode, Len;
+ const fdt32_t *Prop;
+
+ Hob = GetFirstGuidHob (&gFdtHobGuid);
+ if ((Hob == NULL) || (GET_GUID_HOB_DATA_SIZE (Hob) != sizeof (UINT64))) {
+ DEBUG ((DEBUG_ERROR, "%a: No FDT Hob found\n", __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ Fdt = (VOID *)(UINTN)*(UINT64 *)GET_GUID_HOB_DATA (Hob);
+
+ if (fdt_check_header (Fdt) != 0) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: No DTB found @ 0x%p\n",
+ __FUNCTION__,
+ Fdt
+ ));
+ return EFI_NOT_FOUND;
+ }
+
+ // The "cpus" node resides at the the root of the DT. Fetch it.
+ CpusNode = fdt_path_offset (Fdt, "/cpus");
+ if (CpusNode < 0) {
+ DEBUG ((DEBUG_ERROR, "%a: Invalid /cpus node\n", __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ Prop = fdt_getprop((void *)Fdt, CpusNode, "timebase-frequency", &Len);
+ if (!Prop) {
+ DEBUG ((DEBUG_ERROR, "%a: timebase-frequency propertynot found\n", __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ mTimeBaseFrequency = fdt32_to_cpu(*Prop);
+ DEBUG((DEBUG_INFO, "%a: Timer Frequency (DT) is set to 0x%x\n", __FUNCTION__, mTimeBaseFrequency));
+
+ return EFI_SUCCESS;
+}
+/**
+ Initializes the Timer Frequency by reading it from the DTB
+
+**/
+RETURN_STATUS
+EFIAPI
+ArchTimerLibConstructor (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ /*
+ * Initialize only once
+ */
+ if (mTimeBaseFreqInitialized) {
+ return EFI_SUCCESS;
+ }
+
+ mTimeBaseFreqInitialized = 1;
+
+ Status = FdtInitializeTimerFrequency();
+
+ if (EFI_ERROR(Status)) {
+ mTimeBaseFrequency = PcdGet32 (PcdRiscVTimerFrequencyInHz);
+ DEBUG((DEBUG_INFO, "%a: Timer Frequency (PCD) is set to 0x%x\n", __FUNCTION__, mTimeBaseFrequency));
+ }
+
+ return EFI_SUCCESS;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 08/17] MdePkg: Add RiscVSbiLib Library for RISC-V
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (6 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 07/17] MdePkg: Add ArchTimerLib library Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 09/17] UefiCpuPkg/DxeCpuExceptionHandlerLib: Refactor to add other architectures Sunil V L
` (9 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
This library is required to make SBI ecalls from the S-mode EDK2.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
MdePkg/Include/Library/RiscVSbiLib.h | 129 ++++++++++++
MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c | 228 +++++++++++++++++++++
MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf | 28 +++
3 files changed, 385 insertions(+)
create mode 100644 MdePkg/Include/Library/RiscVSbiLib.h
create mode 100644 MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c
create mode 100644 MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf
diff --git a/MdePkg/Include/Library/RiscVSbiLib.h b/MdePkg/Include/Library/RiscVSbiLib.h
new file mode 100644
index 0000000000..e94adb08fd
--- /dev/null
+++ b/MdePkg/Include/Library/RiscVSbiLib.h
@@ -0,0 +1,129 @@
+/** @file
+ Library to call the RISC-V SBI ecalls
+
+ Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Hart - Hardware Thread, similar to a CPU core
+
+ Currently, EDK2 needs to call SBI only to set the time and to do system reset.
+
+**/
+
+#ifndef RISCV_SBI_LIB_H_
+#define RISCV_SBI_LIB_H_
+
+#include <Uefi.h>
+
+/* SBI Extension IDs */
+#define SBI_EXT_TIME 0x54494D45
+#define SBI_EXT_SRST 0x53525354
+
+/* SBI function IDs for TIME extension*/
+#define SBI_EXT_TIME_SET_TIMER 0x0
+
+/* SBI function IDs for SRST extension */
+#define SBI_EXT_SRST_RESET 0x0
+
+#define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
+#define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1
+#define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2
+#define SBI_SRST_RESET_TYPE_LAST SBI_SRST_RESET_TYPE_WARM_REBOOT
+
+#define SBI_SRST_RESET_REASON_NONE 0x0
+#define SBI_SRST_RESET_REASON_SYSFAIL 0x1
+
+/* SBI return error codes */
+#define SBI_SUCCESS 0
+#define SBI_ERR_FAILED -1
+#define SBI_ERR_NOT_SUPPORTED -2
+#define SBI_ERR_INVALID_PARAM -3
+#define SBI_ERR_DENIED -4
+#define SBI_ERR_INVALID_ADDRESS -5
+#define SBI_ERR_ALREADY_AVAILABLE -6
+#define SBI_ERR_ALREADY_STARTED -7
+#define SBI_ERR_ALREADY_STOPPED -8
+
+#define SBI_LAST_ERR SBI_ERR_ALREADY_STOPPED
+
+typedef struct {
+ UINT64 BootHartId;
+ VOID *PeiServiceTable; // PEI Service table
+ UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
+} EFI_RISCV_FIRMWARE_CONTEXT;
+
+
+//
+// EDK2 OpenSBI firmware extension return status.
+//
+typedef struct {
+ UINTN Error; ///< SBI status code
+ UINTN Value; ///< Value returned
+} SBI_RET;
+
+VOID
+EFIAPI
+SbiSetTimer (
+ IN UINT64 Time
+ );
+
+EFI_STATUS
+EFIAPI
+SbiSystemReset (
+ IN UINTN ResetType,
+ IN UINTN ResetReason
+ );
+
+/**
+ Get firmware context of the calling hart.
+
+ @param[out] FirmwareContext The firmware context pointer.
+**/
+VOID
+EFIAPI
+GetFirmwareContext (
+ OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContext
+ );
+
+/**
+ Set firmware context of the calling hart.
+
+ @param[in] FirmwareContext The firmware context pointer.
+**/
+VOID
+EFIAPI
+SetFirmwareContext (
+ IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext
+ );
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr
+ );
+
+/**
+ Set pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr
+ );
+
+#endif
diff --git a/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c b/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c
new file mode 100644
index 0000000000..39cc6628be
--- /dev/null
+++ b/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c
@@ -0,0 +1,228 @@
+/** @file
+ Instance of the SBI ecall library.
+
+ It allows calling an SBI function via an ecall from S-Mode.
+
+ Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVSbiLib.h>
+#include <Register/RiscV64/RiscVAsm.h>
+
+//
+// Maximum arguments for SBI ecall
+// It's possible to pass more but no SBI call uses more as of SBI 0.2.
+// The additional arguments would have to be passed on the stack instead of as
+// registers, like it's done now.
+//
+#define SBI_CALL_MAX_ARGS 6
+
+/**
+ Call SBI call using ecall instruction.
+
+ Asserts when NumArgs exceeds SBI_CALL_MAX_ARGS.
+
+ @param[in] ExtId SBI extension ID.
+ @param[in] FuncId SBI function ID.
+ @param[in] NumArgs Number of arguments to pass to the ecall.
+ @param[in] ... Argument list for the ecall.
+
+ @retval Returns SBI_RET structure with value and error code.
+
+**/
+STATIC
+SBI_RET
+EFIAPI
+SbiCall (
+ IN UINTN ExtId,
+ IN UINTN FuncId,
+ IN UINTN NumArgs,
+ ...
+ )
+{
+ UINTN I;
+ SBI_RET Ret;
+ UINTN Args[SBI_CALL_MAX_ARGS];
+ VA_LIST ArgList;
+
+ VA_START (ArgList, NumArgs);
+
+ ASSERT (NumArgs <= SBI_CALL_MAX_ARGS);
+
+ for (I = 0; I < SBI_CALL_MAX_ARGS; I++) {
+ if (I < NumArgs) {
+ Args[I] = VA_ARG (ArgList, UINTN);
+ } else {
+ // Default to 0 for all arguments that are not given
+ Args[I] = 0;
+ }
+ }
+
+ VA_END (ArgList);
+
+ register UINTN a0 asm ("a0") = Args[0];
+ register UINTN a1 asm ("a1") = Args[1];
+ register UINTN a2 asm ("a2") = Args[2];
+ register UINTN a3 asm ("a3") = Args[3];
+ register UINTN a4 asm ("a4") = Args[4];
+ register UINTN a5 asm ("a5") = Args[5];
+ register UINTN a6 asm ("a6") = (UINTN)(FuncId);
+ register UINTN a7 asm ("a7") = (UINTN)(ExtId);
+
+ asm volatile ("ecall" \
+ : "+r" (a0), "+r" (a1) \
+ : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) \
+ : "memory"); \
+ Ret.Error = a0;
+ Ret.Value = a1;
+ return Ret;
+}
+
+/**
+ Translate SBI error code to EFI status.
+
+ @param[in] SbiError SBI error code
+ @retval EFI_STATUS
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+TranslateError (
+ IN UINTN SbiError
+ )
+{
+ switch (SbiError) {
+ case SBI_SUCCESS:
+ return EFI_SUCCESS;
+ case SBI_ERR_FAILED:
+ return EFI_DEVICE_ERROR;
+ break;
+ case SBI_ERR_NOT_SUPPORTED:
+ return EFI_UNSUPPORTED;
+ break;
+ case SBI_ERR_INVALID_PARAM:
+ return EFI_INVALID_PARAMETER;
+ break;
+ case SBI_ERR_DENIED:
+ return EFI_ACCESS_DENIED;
+ break;
+ case SBI_ERR_INVALID_ADDRESS:
+ return EFI_LOAD_ERROR;
+ break;
+ case SBI_ERR_ALREADY_AVAILABLE:
+ return EFI_ALREADY_STARTED;
+ break;
+ default:
+ //
+ // Reaches here only if SBI has defined a new error type
+ //
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ break;
+ }
+}
+
+/**
+ Clear pending timer interrupt bit and set timer for next event after Time.
+
+ To clear the timer without scheduling a timer event, set Time to a
+ practically infinite value or mask the timer interrupt by clearing sie.STIE.
+
+ @param[in] Time The time offset to the next scheduled timer interrupt.
+**/
+VOID
+EFIAPI
+SbiSetTimer (
+ IN UINT64 Time
+ )
+{
+ SbiCall (SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, 1, Time);
+}
+
+EFI_STATUS
+EFIAPI
+SbiSystemReset (
+ IN UINTN ResetType,
+ IN UINTN ResetReason
+ )
+{
+ SBI_RET Ret;
+
+ Ret = SbiCall (
+ SBI_EXT_SRST,
+ SBI_EXT_SRST_RESET,
+ 2,
+ ResetType,
+ ResetReason
+ );
+
+ return TranslateError (Ret.Error);
+}
+
+/**
+ Get firmware context of the calling hart.
+
+ @param[out] FirmwareContext The firmware context pointer.
+ @retval EFI_SUCCESS The operation succeeds.
+**/
+VOID
+EFIAPI
+GetFirmwareContext (
+ OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContext
+ )
+{
+ *FirmwareContext = (EFI_RISCV_FIRMWARE_CONTEXT *)csr_read(CSR_SSCRATCH);
+}
+
+/**
+ Set firmware context of the calling hart.
+
+ @param[in] FirmwareContext The firmware context pointer.
+**/
+VOID
+EFIAPI
+SetFirmwareContext (
+ IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext
+ )
+{
+ csr_write(CSR_SSCRATCH, FirmwareContext);
+}
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context through OpenSBI FW Extension SBI.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr
+ )
+{
+ GetFirmwareContext (FirmwareContextPtr);
+}
+
+/**
+ Set the pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context through OpenSBI FW Extension SBI.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr
+ )
+{
+ SetFirmwareContext (FirmwareContextPtr);
+}
diff --git a/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf b/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf
new file mode 100644
index 0000000000..b01f909300
--- /dev/null
+++ b/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf
@@ -0,0 +1,28 @@
+## @file
+# RISC-V Library to call SBI ecalls
+#
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVSbiLib
+ FILE_GUID = D742CF3D-E600-4009-8FB5-318073008508
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVSbiLib
+
+[Sources]
+ RiscVSbiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseLib
+
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 09/17] UefiCpuPkg/DxeCpuExceptionHandlerLib: Refactor to add other architectures
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (7 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 08/17] MdePkg: Add RiscVSbiLib Library for RISC-V Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 10/17] UefiCpuPkg: Add RISC-V support in DxeCpuExceptionHandlerLib Sunil V L
` (8 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
Currently the common sources mean x86 only in this library. To add
support for other architectures like RISC-V, we need to build these
files only for x86.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index e7a81bebdb..bf33d54bae 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -32,7 +32,7 @@
X64/ArchExceptionHandler.c
X64/ArchInterruptDefs.h
-[Sources.common]
+[Sources.IA32, Sources.X64]
CpuExceptionCommon.h
CpuExceptionCommon.c
PeiDxeSmmCpuException.c
@@ -56,8 +56,10 @@
SerialPortLib
PrintLib
SynchronizationLib
- LocalApicLib
PeCoffGetEntryPointLib
MemoryAllocationLib
DebugLib
+
+[LibraryClasses.IA32, LibraryClasses.X64]
+ LocalApicLib
VmgExitLib
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 10/17] UefiCpuPkg: Add RISC-V support in DxeCpuExceptionHandlerLib
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (8 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 09/17] UefiCpuPkg/DxeCpuExceptionHandlerLib: Refactor to add other architectures Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 11/17] MdePkg/Library: Add ResetSystemLib library Sunil V L
` (7 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
Add low level interfaces to register exception and interrupt handlers
for RISC-V.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../DxeCpuExceptionHandlerLib.inf | 7 +-
.../RiscV64/CpuExceptionHandlerLib.c | 136 ++++++++++++++++++
.../RiscV64/CpuExceptionHandlerLib.h | 112 +++++++++++++++
.../RiscV64/SupervisorTrapHandler.S | 105 ++++++++++++++
4 files changed, 359 insertions(+), 1 deletion(-)
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h
create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index bf33d54bae..8570b83e8a 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -18,7 +18,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64
+# VALID_ARCHITECTURES = IA32 X64 RISCV64
#
[Sources.Ia32]
@@ -38,6 +38,11 @@
PeiDxeSmmCpuException.c
DxeException.c
+[Sources.RISCV64]
+ RiscV64/SupervisorTrapHandler.S
+ RiscV64/CpuExceptionHandlerLib.c
+ RiscV64/CpuExceptionHandlerLib.h
+
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c
new file mode 100644
index 0000000000..f4427599a6
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c
@@ -0,0 +1,136 @@
+/** @file
+ RISC-V Exception Handler library implementation.
+
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/CpuExceptionHandlerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Register/RiscV64/RiscVAsm.h>
+
+#include "CpuExceptionHandlerLib.h"
+
+STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];
+
+/**
+ Initializes all CPU exceptions entries and provides the default exception handlers.
+
+ Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+ persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+ If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
+ If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+ @param[in] VectorInfo Pointer to reserved vector list.
+
+ @retval EFI_SUCCESS CPU Exception Entries have been successfully initialized
+ with default exception handlers.
+ @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+ @retval EFI_UNSUPPORTED This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionHandlers (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ )
+{
+ csr_write (CSR_STVEC, SupervisorModeTrap);
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Registers a function to be called from the processor interrupt handler.
+
+ This function registers and enables the handler specified by InterruptHandler for a processor
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
+ The installed handler is called once for each processor interrupt or exception.
+ NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or
+ InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.
+
+ @param[in] InterruptType Defines which interrupt or exception to hook.
+ @param[in] InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. If this parameter is NULL, then the handler
+ will be uninstalled.
+
+ @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
+ previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+ previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported,
+ or this function is not supported.
+**/
+EFI_STATUS
+EFIAPI
+RegisterCpuInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ )
+{
+ DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, InterruptType, InterruptHandler));
+ mInterruptHandlers[InterruptType] = InterruptHandler;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Setup separate stacks for certain exception handlers.
+ If the input Buffer and BufferSize are both NULL, use global variable if possible.
+
+ @param[in] Buffer Point to buffer used to separate exception stack.
+ @param[in, out] BufferSize On input, it indicates the byte size of Buffer.
+ If the size is not enough, the return status will
+ be EFI_BUFFER_TOO_SMALL, and output BufferSize
+ will be the size it needs.
+
+ @retval EFI_SUCCESS The stacks are assigned successfully.
+ @retval EFI_UNSUPPORTED This function is not supported.
+ @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small.
+**/
+EFI_STATUS
+EFIAPI
+InitializeSeparateExceptionStacks (
+ IN VOID *Buffer,
+ IN OUT UINTN *BufferSize
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Supervisor mode trap handler.
+
+ @param[in] SmodeTrapReg Registers before trap occurred.
+
+**/
+VOID
+RiscVSupervisorModeTrapHandler (
+ SMODE_TRAP_REGISTERS *SmodeTrapReg
+ )
+{
+ UINTN SCause;
+ EFI_SYSTEM_CONTEXT RiscVSystemContext;
+
+ RiscVSystemContext.SystemContextRiscV64 = (EFI_SYSTEM_CONTEXT_RISCV64 *)SmodeTrapReg;
+ //
+ // Check scasue register.
+ //
+ SCause = (UINTN)csr_read (CSR_SCAUSE);
+ if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) != 0) {
+ //
+ // This is interrupt event.
+ //
+ SCause &= ~(1UL << (sizeof (UINTN) * 8- 1));
+ if ((SCause == IRQ_S_TIMER) && (mInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL)) {
+ mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, RiscVSystemContext);
+ }
+ }
+}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h
new file mode 100644
index 0000000000..1cc6dbe734
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h
@@ -0,0 +1,112 @@
+/** @file
+
+ RISC-V Exception Handler library definition file.
+
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_
+#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_
+
+#include <Register/RiscV64/RiscVAsm.h>
+#include <Register/RiscV64/RiscVImpl.h>
+extern void
+SupervisorModeTrap (
+ void
+ );
+
+//
+// Index of SMode trap register
+//
+#define SMODE_TRAP_REGS_zero 0
+#define SMODE_TRAP_REGS_ra 1
+#define SMODE_TRAP_REGS_sp 2
+#define SMODE_TRAP_REGS_gp 3
+#define SMODE_TRAP_REGS_tp 4
+#define SMODE_TRAP_REGS_t0 5
+#define SMODE_TRAP_REGS_t1 6
+#define SMODE_TRAP_REGS_t2 7
+#define SMODE_TRAP_REGS_s0 8
+#define SMODE_TRAP_REGS_s1 9
+#define SMODE_TRAP_REGS_a0 10
+#define SMODE_TRAP_REGS_a1 11
+#define SMODE_TRAP_REGS_a2 12
+#define SMODE_TRAP_REGS_a3 13
+#define SMODE_TRAP_REGS_a4 14
+#define SMODE_TRAP_REGS_a5 15
+#define SMODE_TRAP_REGS_a6 16
+#define SMODE_TRAP_REGS_a7 17
+#define SMODE_TRAP_REGS_s2 18
+#define SMODE_TRAP_REGS_s3 19
+#define SMODE_TRAP_REGS_s4 20
+#define SMODE_TRAP_REGS_s5 21
+#define SMODE_TRAP_REGS_s6 22
+#define SMODE_TRAP_REGS_s7 23
+#define SMODE_TRAP_REGS_s8 24
+#define SMODE_TRAP_REGS_s9 25
+#define SMODE_TRAP_REGS_s10 26
+#define SMODE_TRAP_REGS_s11 27
+#define SMODE_TRAP_REGS_t3 28
+#define SMODE_TRAP_REGS_t4 29
+#define SMODE_TRAP_REGS_t5 30
+#define SMODE_TRAP_REGS_t6 31
+#define SMODE_TRAP_REGS_sepc 32
+#define SMODE_TRAP_REGS_sstatus 33
+#define SMODE_TRAP_REGS_sie 34
+#define SMODE_TRAP_REGS_last 35
+
+#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINTER__)
+#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last)
+
+#pragma pack(1)
+typedef struct {
+ //
+ // Below are follow the format of EFI_SYSTEM_CONTEXT
+ //
+ UINT64 zero;
+ UINT64 ra;
+ UINT64 sp;
+ UINT64 gp;
+ UINT64 tp;
+ UINT64 t0;
+ UINT64 t1;
+ UINT64 t2;
+ UINT64 s0;
+ UINT64 s1;
+ UINT64 a0;
+ UINT64 a1;
+ UINT64 a2;
+ UINT64 a3;
+ UINT64 a4;
+ UINT64 a5;
+ UINT64 a6;
+ UINT64 a7;
+ UINT64 s2;
+ UINT64 s3;
+ UINT64 s4;
+ UINT64 s5;
+ UINT64 s6;
+ UINT64 s7;
+ UINT64 s8;
+ UINT64 s9;
+ UINT64 s10;
+ UINT64 s11;
+ UINT64 t3;
+ UINT64 t4;
+ UINT64 t5;
+ UINT64 t6;
+ //
+ // Below are the additional information to
+ // EFI_SYSTEM_CONTEXT, private to supervisor mode trap
+ // and not public to EFI environment.
+ //
+ UINT64 sepc;
+ UINT64 sstatus;
+ UINT64 sie;
+} SMODE_TRAP_REGISTERS;
+#pragma pack()
+
+#endif
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S
new file mode 100644
index 0000000000..649c4c5bec
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S
@@ -0,0 +1,105 @@
+/** @file
+ RISC-V Processor supervisor mode trap handler
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include "CpuExceptionHandlerLib.h"
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .globl SupervisorModeTrap
+SupervisorModeTrap:
+ addi sp, sp, -SMODE_TRAP_REGS_SIZE
+
+ /* Save all general regisers except SP */
+ sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
+
+ csrr t0, CSR_SSTATUS
+ and t0, t0, (SSTATUS_SIE | SSTATUS_SPIE)
+ sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
+ csrr t0, CSR_SEPC
+ sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
+ csrr t0, CSR_SIE
+ sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
+ ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
+
+ sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
+ sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
+ sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
+ sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
+ sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
+ sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
+ sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
+ sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
+ sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
+ sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
+ sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
+ sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
+ sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
+ sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
+ sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
+ sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
+ sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
+ sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
+ sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
+ sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
+ sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
+ sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
+ sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
+ sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
+ sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
+ sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
+ sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
+ sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
+ sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
+
+ /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */
+ call RiscVSupervisorModeTrapHandler
+
+ /* Restore all general regisers except SP */
+ ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)
+ ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)
+ ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)
+ ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)
+ ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)
+ ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)
+ ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)
+ ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)
+ ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)
+ ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)
+ ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)
+ ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)
+ ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)
+ ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)
+ ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)
+ ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)
+ ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)
+ ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)
+ ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)
+ ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)
+ ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)
+ ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)
+ ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)
+ ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)
+ ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)
+ ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)
+ ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)
+ ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)
+
+ ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)
+ csrw CSR_SEPC, t0
+ ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)
+ csrw CSR_SIE, t0
+ csrr t0, CSR_SSTATUS
+ ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)
+ or t0, t0, t1
+ csrw CSR_SSTATUS, t0
+ ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)
+ ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)
+ addi sp, sp, SMODE_TRAP_REGS_SIZE
+ sret
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 11/17] MdePkg/Library: Add ResetSystemLib library
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (9 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 10/17] UefiCpuPkg: Add RISC-V support in DxeCpuExceptionHandlerLib Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 12/17] UefiCpuPkg/SecCore: Add SEC startup code for RISC-V Sunil V L
` (6 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
This library implements system reset interfaces like cold reboot,
warm reboot etc. On RISC-V platforms, these are implemented using
SBI calls.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../Library/ResetSystemLib/ResetSystemLib.inf | 35 +++++
.../ResetSystemLib/RiscV64/ResetSystemLib.c | 128 ++++++++++++++++++
2 files changed, 163 insertions(+)
create mode 100644 MdePkg/Library/ResetSystemLib/ResetSystemLib.inf
create mode 100644 MdePkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c
diff --git a/MdePkg/Library/ResetSystemLib/ResetSystemLib.inf b/MdePkg/Library/ResetSystemLib/ResetSystemLib.inf
new file mode 100644
index 0000000000..7c8a7d1142
--- /dev/null
+++ b/MdePkg/Library/ResetSystemLib/ResetSystemLib.inf
@@ -0,0 +1,35 @@
+## @file
+# Library instance for ResetSystem library class
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ResetSystemLib
+ FILE_GUID = 425DC96A-BF26-4684-90F9-1B5FF43BE927
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ResetSystemLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources.RISCV64]
+ RiscV64/ResetSystemLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ DebugLib
+
+[LibraryClasses.RISCV64]
+ RiscVSbiLib
diff --git a/MdePkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c b/MdePkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c
new file mode 100644
index 0000000000..c077ef6ac7
--- /dev/null
+++ b/MdePkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c
@@ -0,0 +1,128 @@
+/** @file
+ Reset System Library functions for RISC-V
+
+ Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/ResetSystemLib.h>
+#include <Library/RiscVSbiLib.h>
+
+/**
+ This function causes a system-wide reset (cold reset), in which
+ all circuitry within the system returns to its initial state. This type of reset
+ is asynchronous to system operation and operates without regard to
+ cycle boundaries.
+
+ If this function returns, it means that the system does not support cold reset.
+**/
+VOID
+EFIAPI
+ResetCold (
+ VOID
+ )
+{
+ // Warm Reset via SBI ecall
+ SbiSystemReset (SBI_SRST_RESET_TYPE_COLD_REBOOT, SBI_SRST_RESET_REASON_NONE);
+}
+
+/**
+ This function causes a system-wide initialization (warm reset), in which all processors
+ are set to their initial state. Pending cycles are not corrupted.
+
+ If this function returns, it means that the system does not support warm reset.
+**/
+VOID
+EFIAPI
+ResetWarm (
+ VOID
+ )
+{
+ // Warm Reset via SBI ecall
+ SbiSystemReset (SBI_SRST_RESET_TYPE_WARM_REBOOT, SBI_SRST_RESET_REASON_NONE);
+}
+
+/**
+ This function causes the system to enter a power state equivalent
+ to the ACPI G2/S5 or G3 states.
+
+ If this function returns, it means that the system does not support shutdown reset.
+**/
+VOID
+EFIAPI
+ResetShutdown (
+ VOID
+ )
+{
+ // Shut down via SBI ecall
+ SbiSystemReset (SBI_SRST_RESET_TYPE_SHUTDOWN, SBI_SRST_RESET_REASON_NONE);
+}
+
+/**
+ This function causes a systemwide reset. The exact type of the reset is
+ defined by the EFI_GUID that follows the Null-terminated Unicode string passed
+ into ResetData. If the platform does not recognize the EFI_GUID in ResetData
+ the platform must pick a supported reset type to perform. The platform may
+ optionally log the parameters from any non-normal reset that occurs.
+
+ @param[in] DataSize The size, in bytes, of ResetData.
+ @param[in] ResetData The data buffer starts with a Null-terminated string,
+ followed by the EFI_GUID.
+**/
+VOID
+EFIAPI
+ResetPlatformSpecific (
+ IN UINTN DataSize,
+ IN VOID *ResetData
+ )
+{
+ //
+ // Can map to OpenSBI vendor or platform specific reset type.
+ //
+ return;
+}
+
+/**
+ The ResetSystem function resets the entire platform.
+
+ @param[in] ResetType The type of reset to perform.
+ @param[in] ResetStatus The status code for the reset.
+ @param[in] DataSize The size, in bytes, of ResetData.
+ @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm, or EfiResetShutdown
+ the data buffer starts with a Null-terminated string, optionally
+ followed by additional binary data. The string is a description
+ that the caller may use to further indicate the reason for the
+ system reset.
+**/
+VOID
+EFIAPI
+ResetSystem (
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN VOID *ResetData OPTIONAL
+ )
+{
+ switch (ResetType) {
+ case EfiResetWarm:
+ ResetWarm ();
+ break;
+
+ case EfiResetCold:
+ ResetCold ();
+ break;
+
+ case EfiResetShutdown:
+ ResetShutdown ();
+ return;
+
+ case EfiResetPlatformSpecific:
+ ResetPlatformSpecific (DataSize, ResetData);
+ return;
+
+ default:
+ return;
+ }
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 12/17] UefiCpuPkg/SecCore: Add SEC startup code for RISC-V
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (10 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 11/17] MdePkg/Library: Add ResetSystemLib library Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 13/17] MdePkg: Add PlatformPeiLib library Sunil V L
` (5 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
Generic RISC-V platforms will start in S-mode directly.
Previous M-mode firmware like opensbi will branch to the
entry point in this module. This module initializes the
firmware context pointer and branches to the PEI phase.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
UefiCpuPkg/SecCore/RiscV64/SecEntry.S | 23 +
UefiCpuPkg/SecCore/RiscV64/SecMain.c | 796 ++++++++++++++++++++++++++
UefiCpuPkg/SecCore/RiscV64/SecMain.h | 63 ++
UefiCpuPkg/SecCore/SecCoreRiscV.inf | 59 ++
4 files changed, 941 insertions(+)
create mode 100644 UefiCpuPkg/SecCore/RiscV64/SecEntry.S
create mode 100644 UefiCpuPkg/SecCore/RiscV64/SecMain.c
create mode 100644 UefiCpuPkg/SecCore/RiscV64/SecMain.h
create mode 100644 UefiCpuPkg/SecCore/SecCoreRiscV.inf
diff --git a/UefiCpuPkg/SecCore/RiscV64/SecEntry.S b/UefiCpuPkg/SecCore/RiscV64/SecEntry.S
new file mode 100644
index 0000000000..1bd0174e27
--- /dev/null
+++ b/UefiCpuPkg/SecCore/RiscV64/SecEntry.S
@@ -0,0 +1,23 @@
+/*
+ Copyright (c) 2021-2022 , Hewlett Packard Enterprise Development LP. All rights reserved.
+ Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ Copyright (c) 2022 Ventana Micro Systems Inc.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ */
+
+#include "SecMain.h"
+
+.text
+.align 3
+
+ASM_FUNC (_ModuleEntryPoint)
+ /* Use Temp memory as the stack for calling to C code */
+ li a4, FixedPcdGet32 (PcdSecPeiTempRamBase)
+ li a5, FixedPcdGet32 (PcdSecPeiTempRamSize)
+
+ /* Use Temp memory as the stack for calling to C code */
+ add sp, a4, a5
+
+ call SecStartup
diff --git a/UefiCpuPkg/SecCore/RiscV64/SecMain.c b/UefiCpuPkg/SecCore/RiscV64/SecMain.c
new file mode 100644
index 0000000000..d9dacce319
--- /dev/null
+++ b/UefiCpuPkg/SecCore/RiscV64/SecMain.c
@@ -0,0 +1,796 @@
+/** @file
+ RISC-V SEC phase module.
+
+ Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "SecMain.h"
+
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ );
+
+EFI_STATUS
+EFIAPI
+TemporaryRamDone (
+ VOID
+ );
+
+STATIC EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = {
+ TemporaryRamMigration
+};
+
+STATIC EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi = {
+ TemporaryRamDone
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gEfiTemporaryRamSupportPpiGuid,
+ &mTemporaryRamSupportPpi
+ },
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiTemporaryRamDonePpiGuid,
+ &mTemporaryRamDonePpi
+ },
+};
+
+/** Temporary RAM migration function.
+
+ This function migrates the data from temporary RAM to permanent
+ memory.
+
+ @param[in] PeiServices PEI service
+ @param[in] TemporaryMemoryBase Temporary memory base address
+ @param[in] PermanentMemoryBase Permanent memory base address
+ @param[in] CopySize Size to copy
+
+**/
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ )
+{
+ VOID *OldHeap;
+ VOID *NewHeap;
+ VOID *OldStack;
+ VOID *NewStack;
+ EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
+
+ DEBUG ((DEBUG_INFO,
+ "%a: Temp Mem Base:0x%Lx, Permanent Mem Base:0x%Lx, CopySize:0x%Lx\n",
+ __FUNCTION__,
+ TemporaryMemoryBase,
+ PermanentMemoryBase,
+ (UINT64)CopySize
+ ));
+
+ OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
+ NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1));
+
+ OldStack = (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1));
+ NewStack = (VOID*)(UINTN)PermanentMemoryBase;
+
+ CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap
+ CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack
+
+ //
+ // Reset firmware context pointer
+ //
+ GetFirmwareContextPointer (&FirmwareContext);
+ FirmwareContext = (VOID *)FirmwareContext + (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
+ SetFirmwareContextPointer (FirmwareContext);
+
+ DEBUG ((DEBUG_INFO, "%a: Firmware Context is relocated to 0x%x\n", __FUNCTION__, FirmwareContext));
+
+ register UINTN a0 asm ("a0") = (UINTN)((UINTN)NewStack - (UINTN)OldStack);
+ asm volatile ("add sp, sp, a0"::"r"(a0):);
+ return EFI_SUCCESS;
+}
+
+/** Temprary RAM done function.
+
+**/
+EFI_STATUS EFIAPI TemporaryRamDone (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "%a: 2nd time PEI core, temporary ram done.\n", __FUNCTION__));
+ return EFI_SUCCESS;
+}
+/** Return platform SEC PPI before PEI Core
+
+ @param[in,out] ThisPpiList Pointer to retrieve EFI_PEI_PPI_DESCRIPTOR.
+
+**/
+STATIC EFI_STATUS
+GetPlatformPrePeiCorePpiDescriptor (
+ IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList
+)
+{
+ *ThisPpiList = mPrivateDispatchTable;
+ return EFI_SUCCESS;
+}
+
+/**
+ Locates the main boot firmware volume.
+
+ @param[in,out] BootFv On input, the base of the BootFv
+ On output, the decompressed main firmware volume
+
+ @retval EFI_SUCCESS The main firmware volume was located and decompressed
+ @retval EFI_NOT_FOUND The main firmware volume was not found
+
+**/
+EFI_STATUS
+FindMainFv (
+ IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv
+ )
+{
+ EFI_FIRMWARE_VOLUME_HEADER *Fv;
+ UINTN Distance;
+
+ ASSERT (((UINTN)*BootFv & EFI_PAGE_MASK) == 0);
+
+ Fv = *BootFv;
+ Distance = (UINTN)(*BootFv)->FvLength;
+ do {
+ Fv = (EFI_FIRMWARE_VOLUME_HEADER *)((UINT8 *)Fv + EFI_PAGE_SIZE);
+ Distance += EFI_PAGE_SIZE;
+ if (Distance > SIZE_32MB) {
+ return EFI_NOT_FOUND;
+ }
+
+ if (Fv->Signature != EFI_FVH_SIGNATURE) {
+ continue;
+ }
+
+ if ((UINTN)Fv->FvLength < Distance) {
+ continue;
+ }
+
+ *BootFv = Fv;
+ return EFI_SUCCESS;
+ } while (TRUE);
+}
+
+/**
+ Locates a section within a series of sections
+ with the specified section type.
+
+ The Instance parameter indicates which instance of the section
+ type to return. (0 is first instance, 1 is second...)
+
+ @param[in] Sections The sections to search
+ @param[in] SizeOfSections Total size of all sections
+ @param[in] SectionType The section type to locate
+ @param[in] Instance The section instance number
+ @param[out] FoundSection The FFS section if found
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindFfsSectionInstance (
+ IN VOID *Sections,
+ IN UINTN SizeOfSections,
+ IN EFI_SECTION_TYPE SectionType,
+ IN UINTN Instance,
+ OUT EFI_COMMON_SECTION_HEADER **FoundSection
+ )
+{
+ EFI_PHYSICAL_ADDRESS CurrentAddress;
+ UINT32 Size;
+ EFI_PHYSICAL_ADDRESS EndOfSections;
+ EFI_COMMON_SECTION_HEADER *Section;
+ EFI_PHYSICAL_ADDRESS EndOfSection;
+
+ //
+ // Loop through the FFS file sections within the PEI Core FFS file
+ //
+ EndOfSection = (EFI_PHYSICAL_ADDRESS)(UINTN)Sections;
+ EndOfSections = EndOfSection + SizeOfSections;
+ for ( ; ;) {
+ if (EndOfSection == EndOfSections) {
+ break;
+ }
+
+ CurrentAddress = (EndOfSection + 3) & ~(3ULL);
+ if (CurrentAddress >= EndOfSections) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ Section = (EFI_COMMON_SECTION_HEADER *)(UINTN)CurrentAddress;
+
+ Size = SECTION_SIZE (Section);
+ if (Size < sizeof (*Section)) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ EndOfSection = CurrentAddress + Size;
+ if (EndOfSection > EndOfSections) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ //
+ // Look for the requested section type
+ //
+ if (Section->Type == SectionType) {
+ if (Instance == 0) {
+ *FoundSection = Section;
+ return EFI_SUCCESS;
+ } else {
+ Instance--;
+ }
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ Locates a section within a series of sections
+ with the specified section type.
+
+ @param[in] Sections The sections to search
+ @param[in] SizeOfSections Total size of all sections
+ @param[in] SectionType The section type to locate
+ @param[out] FoundSection The FFS section if found
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindFfsSectionInSections (
+ IN VOID *Sections,
+ IN UINTN SizeOfSections,
+ IN EFI_SECTION_TYPE SectionType,
+ OUT EFI_COMMON_SECTION_HEADER **FoundSection
+ )
+{
+ return FindFfsSectionInstance (
+ Sections,
+ SizeOfSections,
+ SectionType,
+ 0,
+ FoundSection
+ );
+}
+
+/**
+ Locates a FFS file with the specified file type and a section
+ within that file with the specified section type.
+
+ @param[in] Fv The firmware volume to search
+ @param[in] FileType The file type to locate
+ @param[in] SectionType The section type to locate
+ @param[out] FoundSection The FFS section if found
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindFfsFileAndSection (
+ IN EFI_FIRMWARE_VOLUME_HEADER *Fv,
+ IN EFI_FV_FILETYPE FileType,
+ IN EFI_SECTION_TYPE SectionType,
+ OUT EFI_COMMON_SECTION_HEADER **FoundSection
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS CurrentAddress;
+ EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume;
+ EFI_FFS_FILE_HEADER *File;
+ UINT32 Size;
+ EFI_PHYSICAL_ADDRESS EndOfFile;
+
+ if (Fv->Signature != EFI_FVH_SIGNATURE) {
+ DEBUG ((DEBUG_ERROR, "FV at %p does not have FV header signature\n", Fv));
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Fv;
+ EndOfFirmwareVolume = CurrentAddress + Fv->FvLength;
+
+ //
+ // Loop through the FFS files in the Boot Firmware Volume
+ //
+ for (EndOfFile = CurrentAddress + Fv->HeaderLength; ; ) {
+ CurrentAddress = (EndOfFile + 7) & ~(7ULL);
+ if (CurrentAddress > EndOfFirmwareVolume) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ File = (EFI_FFS_FILE_HEADER *)(UINTN)CurrentAddress;
+ Size = FFS_FILE_SIZE (File);
+ if (Size < (sizeof (*File) + sizeof (EFI_COMMON_SECTION_HEADER))) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ EndOfFile = CurrentAddress + Size;
+ if (EndOfFile > EndOfFirmwareVolume) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ //
+ // Look for the request file type
+ //
+ if (File->Type != FileType) {
+ continue;
+ }
+
+ Status = FindFfsSectionInSections (
+ (VOID *)(File + 1),
+ (UINTN)EndOfFile - (UINTN)(File + 1),
+ SectionType,
+ FoundSection
+ );
+ if (!EFI_ERROR (Status) || (Status == EFI_VOLUME_CORRUPTED)) {
+ return Status;
+ }
+ }
+}
+
+/**
+ Locates the compressed main firmware volume and decompresses it.
+
+ @param[in,out] Fv On input, the firmware volume to search
+ On output, the decompressed BOOT/PEI FV
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+EFI_STATUS
+DecompressMemFvs (
+ IN OUT EFI_FIRMWARE_VOLUME_HEADER **Fv
+ )
+{
+ EFI_STATUS Status;
+ EFI_GUID_DEFINED_SECTION *Section;
+ UINT32 OutputBufferSize;
+ UINT32 ScratchBufferSize;
+ UINT16 SectionAttribute;
+ UINT32 AuthenticationStatus;
+ VOID *OutputBuffer;
+ VOID *ScratchBuffer;
+ EFI_COMMON_SECTION_HEADER *FvSection;
+ EFI_FIRMWARE_VOLUME_HEADER *PeiMemFv;
+ EFI_FIRMWARE_VOLUME_HEADER *DxeMemFv;
+ UINT32 FvHeaderSize;
+ UINT32 FvSectionSize;
+
+ FvSection = (EFI_COMMON_SECTION_HEADER *)NULL;
+
+ Status = FindFfsFileAndSection (
+ *Fv,
+ EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE,
+ EFI_SECTION_GUID_DEFINED,
+ (EFI_COMMON_SECTION_HEADER **)&Section
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Unable to find GUID defined section\n"));
+ return Status;
+ }
+
+ Status = ExtractGuidedSectionGetInfo (
+ Section,
+ &OutputBufferSize,
+ &ScratchBufferSize,
+ &SectionAttribute
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Unable to GetInfo for GUIDed section\n"));
+ return Status;
+ }
+
+ OutputBuffer = (VOID *)((UINT8 *)(UINTN)PcdGet32 (PcdDxeMemFvBase) + SIZE_1MB);
+ ScratchBuffer = ALIGN_POINTER ((UINT8 *)OutputBuffer + OutputBufferSize, SIZE_1MB);
+
+ Status = ExtractGuidedSectionDecode (
+ Section,
+ &OutputBuffer,
+ ScratchBuffer,
+ &AuthenticationStatus
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Error during GUID section decode\n"));
+ return Status;
+ }
+
+ Status = FindFfsSectionInstance (
+ OutputBuffer,
+ OutputBufferSize,
+ EFI_SECTION_FIRMWARE_VOLUME_IMAGE,
+ 0,
+ &FvSection
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Unable to find PEI FV section\n"));
+ return Status;
+ }
+
+ ASSERT (
+ SECTION_SIZE (FvSection) ==
+ (PcdGet32 (PcdPeiMemFvSize) + sizeof (*FvSection))
+ );
+ ASSERT (FvSection->Type == EFI_SECTION_FIRMWARE_VOLUME_IMAGE);
+
+ PeiMemFv = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 (PcdPeiMemFvBase);
+ CopyMem (PeiMemFv, (VOID *)(FvSection + 1), PcdGet32 (PcdPeiMemFvSize));
+
+ if (PeiMemFv->Signature != EFI_FVH_SIGNATURE) {
+ DEBUG ((DEBUG_ERROR, "Extracted FV at %p does not have FV header signature\n", PeiMemFv));
+ CpuDeadLoop ();
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ Status = FindFfsSectionInstance (
+ OutputBuffer,
+ OutputBufferSize,
+ EFI_SECTION_FIRMWARE_VOLUME_IMAGE,
+ 1,
+ &FvSection
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Unable to find DXE FV section\n"));
+ return Status;
+ }
+
+ ASSERT (FvSection->Type == EFI_SECTION_FIRMWARE_VOLUME_IMAGE);
+
+ if (IS_SECTION2 (FvSection)) {
+ FvSectionSize = SECTION2_SIZE (FvSection);
+ FvHeaderSize = sizeof (EFI_COMMON_SECTION_HEADER2);
+ } else {
+ FvSectionSize = SECTION_SIZE (FvSection);
+ FvHeaderSize = sizeof (EFI_COMMON_SECTION_HEADER);
+ }
+
+ ASSERT (FvSectionSize == (PcdGet32 (PcdDxeMemFvSize) + FvHeaderSize));
+
+ DxeMemFv = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32 (PcdDxeMemFvBase);
+ CopyMem (DxeMemFv, (VOID *)((UINTN)FvSection + FvHeaderSize), PcdGet32 (PcdDxeMemFvSize));
+
+ if (DxeMemFv->Signature != EFI_FVH_SIGNATURE) {
+ DEBUG ((DEBUG_ERROR, "Extracted FV at %p does not have FV header signature\n", DxeMemFv));
+ CpuDeadLoop ();
+ return EFI_VOLUME_CORRUPTED;
+ }
+ *Fv = PeiMemFv;
+ return EFI_SUCCESS;
+}
+
+/**
+ Locates the PEI Core entry point address
+
+ @param[in] Fv The firmware volume to search
+ @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindPeiCoreImageBaseInFv (
+ IN EFI_FIRMWARE_VOLUME_HEADER *Fv,
+ OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
+ )
+{
+ EFI_STATUS Status;
+ EFI_COMMON_SECTION_HEADER *Section;
+
+ Status = FindFfsFileAndSection (
+ Fv,
+ EFI_FV_FILETYPE_PEI_CORE,
+ EFI_SECTION_PE32,
+ &Section
+ );
+ if (EFI_ERROR (Status)) {
+ Status = FindFfsFileAndSection (
+ Fv,
+ EFI_FV_FILETYPE_PEI_CORE,
+ EFI_SECTION_TE,
+ &Section
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Unable to find PEI Core image\n"));
+ return Status;
+ }
+ }
+
+ *PeiCoreImageBase = (EFI_PHYSICAL_ADDRESS)(UINTN)(Section + 1);
+ return EFI_SUCCESS;
+}
+
+/**
+ Locates the PEI Core entry point address
+
+ @param[in,out] Fv The firmware volume to search
+ @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+VOID
+FindPeiCoreImageBase (
+ IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv,
+ OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
+ )
+{
+
+ *PeiCoreImageBase = 0;
+
+ FindMainFv (BootFv);
+
+ DecompressMemFvs (BootFv);
+
+ FindPeiCoreImageBaseInFv (*BootFv, PeiCoreImageBase);
+}
+
+/**
+ Find core image base.
+
+**/
+EFI_STATUS
+FindImageBase (
+ IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,
+ OUT EFI_PHYSICAL_ADDRESS *SecCoreImageBase
+ )
+{
+ EFI_PHYSICAL_ADDRESS CurrentAddress;
+ EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume;
+ EFI_FFS_FILE_HEADER *File;
+ UINT32 Size;
+ EFI_PHYSICAL_ADDRESS EndOfFile;
+ EFI_COMMON_SECTION_HEADER *Section;
+ EFI_PHYSICAL_ADDRESS EndOfSection;
+
+ *SecCoreImageBase = 0;
+
+ CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)BootFirmwareVolumePtr;
+ EndOfFirmwareVolume = CurrentAddress + BootFirmwareVolumePtr->FvLength;
+
+ //
+ // Loop through the FFS files in the Boot Firmware Volume
+ //
+ for (EndOfFile = CurrentAddress + BootFirmwareVolumePtr->HeaderLength; ; ) {
+ CurrentAddress = (EndOfFile + 7) & 0xfffffffffffffff8ULL;
+ if (CurrentAddress > EndOfFirmwareVolume) {
+ return EFI_NOT_FOUND;
+ }
+
+ File = (EFI_FFS_FILE_HEADER *)(UINTN)CurrentAddress;
+ Size = FFS_FILE_SIZE (File);
+ if (Size < sizeof (*File)) {
+ return EFI_NOT_FOUND;
+ }
+
+ EndOfFile = CurrentAddress + Size;
+ if (EndOfFile > EndOfFirmwareVolume) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Look for SEC Core
+ //
+ if (File->Type != EFI_FV_FILETYPE_SECURITY_CORE) {
+ continue;
+ }
+
+ //
+ // Loop through the FFS file sections within the FFS file
+ //
+ EndOfSection = (EFI_PHYSICAL_ADDRESS)(UINTN)(File + 1);
+ for ( ; ;) {
+ CurrentAddress = (EndOfSection + 3) & 0xfffffffffffffffcULL;
+ Section = (EFI_COMMON_SECTION_HEADER *)(UINTN)CurrentAddress;
+
+ Size = SECTION_SIZE (Section);
+ if (Size < sizeof (*Section)) {
+ return EFI_NOT_FOUND;
+ }
+
+ EndOfSection = CurrentAddress + Size;
+ if (EndOfSection > EndOfFile) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Look for executable sections
+ //
+ if ((Section->Type == EFI_SECTION_PE32) || (Section->Type == EFI_SECTION_TE)) {
+ if (File->Type == EFI_FV_FILETYPE_SECURITY_CORE) {
+ *SecCoreImageBase = (PHYSICAL_ADDRESS)(UINTN)(Section + 1);
+ }
+
+ break;
+ }
+ }
+
+ //
+ // SEC Core image found
+ //
+ if (*SecCoreImageBase != 0) {
+ return EFI_SUCCESS;
+ }
+ }
+}
+
+/*
+ Find and return Pei Core entry point.
+
+ It also find SEC and PEI Core file debug information. It will report them if
+ remote debug is enabled.
+
+**/
+VOID
+FindAndReportEntryPoints (
+ IN EFI_FIRMWARE_VOLUME_HEADER **BootFirmwareVolumePtr,
+ OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS SecCoreImageBase;
+ EFI_PHYSICAL_ADDRESS PeiCoreImageBase;
+ PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
+
+ //
+ // Find SEC Core and PEI Core image base
+ //
+ Status = FindImageBase (*BootFirmwareVolumePtr, &SecCoreImageBase);
+ ASSERT_EFI_ERROR (Status);
+
+ FindPeiCoreImageBase (BootFirmwareVolumePtr, &PeiCoreImageBase);
+
+ ZeroMem ((VOID *)&ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT));
+ //
+ // Report SEC Core debug information when remote debug is enabled
+ //
+ ImageContext.ImageAddress = SecCoreImageBase;
+ ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)(UINTN)ImageContext.ImageAddress);
+ PeCoffLoaderRelocateImageExtraAction (&ImageContext);
+
+ //
+ // Report PEI Core debug information when remote debug is enabled
+ //
+ ImageContext.ImageAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)PeiCoreImageBase;
+ ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)(UINTN)ImageContext.ImageAddress);
+ PeCoffLoaderRelocateImageExtraAction (&ImageContext);
+
+ //
+ // Find PEI Core entry point
+ //
+ Status = PeCoffLoaderGetEntryPoint ((VOID *)(UINTN)PeiCoreImageBase, (VOID **)PeiCoreEntryPoint);
+ if (EFI_ERROR (Status)) {
+ *PeiCoreEntryPoint = 0;
+ }
+
+ return;
+}
+
+/**
+
+ Entry point to the C language phase of SEC. After the SEC assembly
+ code has initialized some temporary memory and set up the stack,
+ the control is transferred to this function.
+
+
+ @param[in] BootHartId Hardware thread ID of boot hart.
+ @param[in] DeviceTreeAddress Pointer to Device Tree (DTB)
+**/
+VOID
+NORETURN
+EFIAPI
+SecStartup (
+ IN UINTN BootHartId,
+ IN VOID *DeviceTreeAddress
+ )
+{
+ EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext;
+ EFI_FIRMWARE_VOLUME_HEADER *BootFv;
+ EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;
+ EFI_SEC_PEI_HAND_OFF SecCoreData;
+ EFI_STATUS Status;
+
+ //
+ // Report Status Code to indicate entering SEC core
+ //
+ DEBUG ((
+ DEBUG_INFO,
+ "%a() BootHartId: 0x%x, DeviceTreeAddress=0x%x\n",
+ __FUNCTION__,
+ BootHartId,
+ DeviceTreeAddress
+ ));
+
+ //
+ // Process all libraries constructor function linked to SecCore.
+ //
+ ProcessLibraryConstructorList ();
+
+ BootFv = (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdSecMemFvBase);
+
+ ASSERT(BootFv != NULL);
+ SecCoreData.DataSize = (UINT16)sizeof (EFI_SEC_PEI_HAND_OFF);
+ SecCoreData.BootFirmwareVolumeBase = BootFv;
+ SecCoreData.BootFirmwareVolumeSize = (UINTN)FixedPcdGet32 (PcdSecMemFvSize);
+ SecCoreData.TemporaryRamBase = (VOID *)(UINT64)FixedPcdGet32 (PcdSecPeiTempRamBase);
+ SecCoreData.TemporaryRamSize = (UINTN)FixedPcdGet32 (PcdSecPeiTempRamSize);
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
+ SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize >> 1;
+ SecCoreData.StackBase = (UINT8 *)SecCoreData.TemporaryRamBase + (SecCoreData.TemporaryRamSize >> 1);
+ SecCoreData.StackSize = SecCoreData.TemporaryRamSize >> 1;
+
+ DEBUG ((
+ DEBUG_INFO,
+ "%a() BFV Base: 0x%x, BFV Size: 0x%x, TempRAM Base: 0x%x, TempRAM Size: 0x%x, PeiTempRamBase: 0x%x, PeiTempRamSize: 0x%x, StackBase: 0x%x, StackSize: 0x%x\n",
+ __FUNCTION__,
+ SecCoreData.BootFirmwareVolumeBase,
+ SecCoreData.BootFirmwareVolumeSize,
+ SecCoreData.TemporaryRamBase,
+ SecCoreData.TemporaryRamSize,
+ SecCoreData.PeiTemporaryRamBase,
+ SecCoreData.PeiTemporaryRamSize,
+ SecCoreData.StackBase,
+ SecCoreData.StackSize
+ ));
+
+ FindAndReportEntryPoints (
+ &BootFv,
+ &PeiCoreEntryPoint
+ );
+ if (PeiCoreEntryPoint == NULL) {
+ CpuDeadLoop ();
+ }
+
+ SecCoreData.BootFirmwareVolumeBase = BootFv;
+ SecCoreData.BootFirmwareVolumeSize = (UINTN) BootFv->FvLength;
+
+ Status = GetPlatformPrePeiCorePpiDescriptor (&PpiList);
+ if (EFI_ERROR (Status)) {
+ PpiList = NULL;
+ }
+
+ FirmwareContext.BootHartId = BootHartId;
+ FirmwareContext.FlattenedDeviceTree = (UINT64)DeviceTreeAddress;
+ SetFirmwareContextPointer (&FirmwareContext);
+
+ //
+ // Transfer the control to the PEI core
+ //
+ ASSERT (PeiCoreEntryPoint != NULL);
+ (*PeiCoreEntryPoint)(&SecCoreData, PpiList);
+
+ //
+ // Should not come here.
+ //
+ UNREACHABLE ();
+}
diff --git a/UefiCpuPkg/SecCore/RiscV64/SecMain.h b/UefiCpuPkg/SecCore/RiscV64/SecMain.h
new file mode 100644
index 0000000000..eeb368de02
--- /dev/null
+++ b/UefiCpuPkg/SecCore/RiscV64/SecMain.h
@@ -0,0 +1,63 @@
+/** @file
+ Master header file for SecCore.
+
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _SEC_MAIN_H_
+#define _SEC_MAIN_H_
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugAgentLib.h>
+#include <Library/DebugLib.h>
+#include <Library/ExtractGuidedSectionLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeCoffExtraActionLib.h>
+#include <Library/PeCoffGetEntryPointLib.h>
+#include <Library/PeCoffLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Library/PrintLib.h>
+#include <Library/RiscVSbiLib.h>
+#include <Register/RiscV64/RiscVImpl.h>
+#include <Ppi/TemporaryRamDone.h>
+#include <Ppi/TemporaryRamSupport.h>
+
+/**
+ Entry point to the C language phase of SEC. After the SEC assembly
+ code has initialized some temporary memory and set up the stack,
+ the control is transferred to this function.
+
+ @param SizeOfRam Size of the temporary memory available for use.
+ @param TempRamBase Base address of temporary ram
+ @param BootFirmwareVolume Base address of the Boot Firmware Volume.
+**/
+VOID
+NORETURN
+EFIAPI
+SecStartup (
+ IN UINTN BootHartId,
+ IN VOID *DeviceTreeAddress
+ );
+
+/**
+ Auto-generated function that calls the library constructors for all of the module's
+ dependent libraries. This function must be called by the SEC Core once a stack has
+ been established.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryConstructorList (
+ VOID
+ );
+
+#endif
diff --git a/UefiCpuPkg/SecCore/SecCoreRiscV.inf b/UefiCpuPkg/SecCore/SecCoreRiscV.inf
new file mode 100644
index 0000000000..8ba6400f53
--- /dev/null
+++ b/UefiCpuPkg/SecCore/SecCoreRiscV.inf
@@ -0,0 +1,59 @@
+## @file
+# RISC-V SEC module which boots in S-mode.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = SecMain
+ FILE_GUID = 42C30D8E-BFAD-4E77-9041-E7DAAE88DF7A
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SecMain
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ RiscV64/SecEntry.S
+ RiscV64/SecMain.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ PlatformSecLib
+ PcdLib
+ CpuLib
+ PeCoffGetEntryPointLib
+ PeCoffExtraActionLib
+ RiscVSbiLib
+
+[Ppis]
+ gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED
+ gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSecMemFvBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSecMemFvSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSecPeiTempRamBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSecPeiTempRamSize
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ SecCoreExtra.uni
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 13/17] MdePkg: Add PlatformPeiLib library
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (11 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 12/17] UefiCpuPkg/SecCore: Add SEC startup code for RISC-V Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 14/17] MdeModulePkg/Universal: Add PlatformPei module for RISC-V Sunil V L
` (4 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
This library is required in RISC-V to build the FDT Hob. The
library can be leveraged by other architectures like ARM if
required.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
MdePkg/Include/Library/PlatformPeiLib.h | 15 ++++
.../Library/PlatformPeiLib/PlatformPeiLib.inf | 40 +++++++++++
.../PlatformPeiLib/RiscV64/PlatformPeiLib.c | 68 +++++++++++++++++++
3 files changed, 123 insertions(+)
create mode 100644 MdePkg/Include/Library/PlatformPeiLib.h
create mode 100644 MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf
create mode 100644 MdePkg/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c
diff --git a/MdePkg/Include/Library/PlatformPeiLib.h b/MdePkg/Include/Library/PlatformPeiLib.h
new file mode 100644
index 0000000000..1e8c5f98cf
--- /dev/null
+++ b/MdePkg/Include/Library/PlatformPeiLib.h
@@ -0,0 +1,15 @@
+/** @file
+ Library to initialize platform data at PEI phase
+
+ Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_PEI_LIB_H_
+#define _PLATFORM_PEI_LIB_H_
+
+EFI_STATUS PlatformPeim(VOID);
+
+#endif
diff --git a/MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf b/MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf
new file mode 100644
index 0000000000..d682b3c0f9
--- /dev/null
+++ b/MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf
@@ -0,0 +1,40 @@
+## @file
+# Platform Initialization Pei Library
+#
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformPeiLib
+ FILE_GUID = B35BD738-787B-47FB-8139-20193442CC49
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformPeiLib
+
+[Sources.RISCV64]
+ RiscV64/PlatformPeiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ FdtLib
+ PcdLib
+ PeimEntryPoint
+ BaseLib
+
+[LibraryClasses.RISCV64]
+ RiscVSbiLib
+
+[Guids]
+ gFdtHobGuid ## PRODUCES
diff --git a/MdePkg/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c b/MdePkg/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c
new file mode 100644
index 0000000000..e62aa26df9
--- /dev/null
+++ b/MdePkg/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c
@@ -0,0 +1,68 @@
+/** @file
+The library call to pass the device tree to DXE via HOB.
+
+Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/RiscVSbiLib.h>
+
+#include <libfdt.h>
+
+#include <Guid/FdtHob.h>
+
+/**
+ @retval EFI_SUCCESS The address of FDT is passed in HOB.
+ EFI_UNSUPPORTED Can't locate FDT.
+**/
+EFI_STATUS
+EFIAPI
+PlatformPeim (
+ VOID
+ )
+{
+ EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
+ VOID *FdtPointer;
+ VOID *Base;
+ VOID *NewBase;
+ UINTN FdtSize;
+ UINTN FdtPages;
+ UINT64 *FdtHobData;
+
+ FirmwareContext = NULL;
+ GetFirmwareContextPointer (&FirmwareContext);
+
+ if (FirmwareContext == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__));
+ return EFI_UNSUPPORTED;
+ }
+
+ FdtPointer = (VOID *)FirmwareContext->FlattenedDeviceTree;
+ if (FdtPointer == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__));
+ return EFI_UNSUPPORTED;
+ }
+
+ DEBUG ((DEBUG_INFO, "%a: Build FDT HOB - FDT at address: 0x%x \n", __FUNCTION__, FdtPointer));
+ Base = FdtPointer;
+ ASSERT (Base != NULL);
+ ASSERT (fdt_check_header (Base) == 0);
+
+ FdtSize = fdt_totalsize (Base);
+ FdtPages = EFI_SIZE_TO_PAGES (FdtSize);
+ NewBase = AllocatePages (FdtPages);
+ ASSERT (NewBase != NULL);
+ fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages));
+
+ FdtHobData = BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData);
+ ASSERT (FdtHobData != NULL);
+ *FdtHobData = (UINTN)NewBase;
+
+ return EFI_SUCCESS;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 14/17] MdeModulePkg/Universal: Add PlatformPei module for RISC-V
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (12 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 13/17] MdePkg: Add PlatformPeiLib library Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 15/17] UefiCpuPkg/CpuDxe: Refactor to allow other CPU architectures Sunil V L
` (3 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
Thie PEIM is required to do platform specific initialization like
detecting the permanent memory and install memory HOB, install the
FDT Hob etc.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../Universal/PlatformPei/PlatformPei.inf | 65 +++
.../Universal/PlatformPei/RiscV64/Fv.c | 83 ++++
.../Universal/PlatformPei/RiscV64/MemDetect.c | 179 +++++++++
.../Universal/PlatformPei/RiscV64/Platform.c | 372 ++++++++++++++++++
.../Universal/PlatformPei/RiscV64/Platform.h | 97 +++++
5 files changed, 796 insertions(+)
create mode 100644 MdeModulePkg/Universal/PlatformPei/PlatformPei.inf
create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c
create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c
create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c
create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h
diff --git a/MdeModulePkg/Universal/PlatformPei/PlatformPei.inf b/MdeModulePkg/Universal/PlatformPei/PlatformPei.inf
new file mode 100644
index 0000000000..220f4a7ee5
--- /dev/null
+++ b/MdeModulePkg/Universal/PlatformPei/PlatformPei.inf
@@ -0,0 +1,65 @@
+## @file
+# Platform PEI driver
+#
+# This module provides platform specific functions
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformPei
+ FILE_GUID = 0F26B9AF-3E38-46E8-9D35-0318E903E049
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitializePlatform
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ RiscV64/Fv.c
+ RiscV64/MemDetect.c
+ RiscV64/Platform.c
+ RiscV64/Platform.h
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[Guids]
+ gEfiMemoryTypeInformationGuid
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ FdtLib
+ IoLib
+ PcdLib
+ PeimEntryPoint
+ PeiResourcePublicationLib
+ PlatformPeiLib
+
+[LibraryClasses.RISCV64]
+ RiscVSbiLib
+
+[Pcd.RISCV64]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvSize
+
+[Ppis]
+ gEfiPeiMasterBootModePpiGuid
+
+[Depex]
+ TRUE
diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c b/MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c
new file mode 100644
index 0000000000..15e77fcf7e
--- /dev/null
+++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c
@@ -0,0 +1,83 @@
+/** @file
+ Build FV related hobs for platform.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PiPei.h"
+#include "Platform.h"
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+
+/**
+ Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
+ and DXE know about them.
+
+ @retval EFI_SUCCESS Platform PEI FVs were initialized successfully.
+
+**/
+EFI_STATUS
+PeiFvInitialization (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
+
+ // Create a memory allocation HOB for the DXE FV.
+ //
+ // If "secure" S3 is needed, then SEC will decompress both PEI and DXE
+ // firmware volumes at S3 resume too, hence we need to keep away the OS from
+ // DXEFV as well. Otherwise we only need to keep away DXE itself from the
+ // DXEFV area.
+ //
+ BuildMemoryAllocationHob (
+ PcdGet32 (PcdPeiMemFvBase),
+ PcdGet32 (PcdPeiMemFvSize),
+ EfiBootServicesData
+ );
+
+
+ //
+ // Let DXE know about the DXE FV
+ //
+ BuildFvHob (PcdGet32 (PcdDxeMemFvBase), PcdGet32 (PcdDxeMemFvSize));
+ DEBUG ((
+ DEBUG_INFO,
+ "Platform builds DXE FV at %x, size %x.\n",
+ PcdGet32 (PcdDxeMemFvBase),
+ PcdGet32 (PcdDxeMemFvSize)
+ ));
+
+ // Create a memory allocation HOB for the DXE FV.
+ //
+ // If "secure" S3 is needed, then SEC will decompress both PEI and DXE
+ // firmware volumes at S3 resume too, hence we need to keep away the OS from
+ // DXEFV as well. Otherwise we only need to keep away DXE itself from the
+ // DXEFV area.
+ //
+ BuildMemoryAllocationHob (
+ PcdGet32 (PcdDxeMemFvBase),
+ PcdGet32 (PcdDxeMemFvSize),
+ EfiBootServicesData
+ );
+
+ //
+ // Let PEI know about the DXE FV so it can find the DXE Core
+ //
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *)(UINTN)PcdGet32 (PcdDxeMemFvBase),
+ PcdGet32 (PcdDxeMemFvSize),
+ NULL,
+ NULL
+ );
+
+ return EFI_SUCCESS;
+}
diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c b/MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c
new file mode 100644
index 0000000000..3ebd29eba6
--- /dev/null
+++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c
@@ -0,0 +1,179 @@
+/** @file
+ Memory Detection for Virtual Machines.
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+Module Name:
+
+ MemDetect.c
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/ResourcePublicationLib.h>
+#include <Library/RiscVSbiLib.h>
+
+#include <libfdt.h>
+
+#include <Guid/FdtHob.h>
+
+#include "Platform.h"
+
+STATIC EFI_PHYSICAL_ADDRESS SystemMemoryBase;
+STATIC UINT64 SystemMemorySize;
+STATIC EFI_PHYSICAL_ADDRESS MmodeResvBase;
+STATIC UINT64 MmodeResvSize;
+
+/**
+ Publish PEI core memory.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+PublishPeiMemory (
+ VOID
+ )
+{
+ EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
+ EFI_PHYSICAL_ADDRESS MemoryBase;
+ CONST UINT64 *RegProp;
+ CONST CHAR8 *Type;
+ EFI_STATUS Status;
+ UINT64 CurBase, CurSize;
+ UINT64 NewBase = 0, NewSize = 0;
+ UINT64 MemorySize;
+ INT32 Node, Prev;
+ INT32 Len;
+ VOID *FdtPointer;
+
+ FirmwareContext = NULL;
+ GetFirmwareContextPointer (&FirmwareContext);
+
+ if (FirmwareContext == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__));
+ return EFI_UNSUPPORTED;
+ }
+
+ FdtPointer = (VOID *)FirmwareContext->FlattenedDeviceTree;
+ if (FdtPointer == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__));
+ return EFI_UNSUPPORTED;
+ }
+
+ // Look for the lowest memory node
+ for (Prev = 0;; Prev = Node) {
+ Node = fdt_next_node (FdtPointer, Prev, NULL);
+ if (Node < 0) {
+ break;
+ }
+ // Check for memory node
+ Type = fdt_getprop (FdtPointer, Node, "device_type", &Len);
+ if (Type && AsciiStrnCmp (Type, "memory", Len) == 0) {
+ // Get the 'reg' property of this node. For now, we will assume
+ // two 8 byte quantities for base and size, respectively.
+ RegProp = fdt_getprop (FdtPointer, Node, "reg", &Len);
+ if (RegProp != 0 && Len == (2 * sizeof (UINT64))) {
+
+ CurBase = fdt64_to_cpu (ReadUnaligned64 (RegProp));
+ CurSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1));
+
+ DEBUG ((DEBUG_INFO, "%a: System RAM @ 0x%lx - 0x%lx\n",
+ __FUNCTION__, CurBase, CurBase + CurSize - 1));
+
+ if (NewBase > CurBase || NewBase == 0) {
+ NewBase = CurBase;
+ NewSize = CurSize;
+ }
+ } else {
+ DEBUG ((DEBUG_ERROR, "%a: Failed to parse FDT memory node\n",
+ __FUNCTION__));
+ }
+ }
+ }
+
+ SystemMemoryBase = NewBase;
+ SystemMemorySize = NewSize;
+
+ /* try to locate the reserved memory opensbi node */
+ Node = fdt_path_offset(FdtPointer, "/reserved-memory/mmode_resv0");
+ if (Node >= 0) {
+ RegProp = fdt_getprop (FdtPointer, Node, "reg", &Len);
+ if (RegProp != 0 && Len == (2 * sizeof (UINT64))) {
+ NewBase = fdt64_to_cpu (ReadUnaligned64 (RegProp));
+ NewSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1));
+ DEBUG ((DEBUG_INFO, "%a: M-mode Base = 0x%lx, M-mode Size = 0x%lx\n",
+ __FUNCTION__, NewBase, NewSize));
+ MmodeResvBase = NewBase;
+ MmodeResvSize = NewSize;
+ }
+ }
+
+ DEBUG ((DEBUG_INFO, "%a: SystemMemoryBase:0x%x SystemMemorySize:%x\n",
+ __FUNCTION__, SystemMemoryBase, SystemMemorySize));
+
+ //
+ // Initial 16MB needs to be reserved
+ //
+ MemoryBase = SystemMemoryBase + SIZE_16MB;
+ MemorySize = SystemMemorySize - SIZE_16MB;
+
+ //
+ // Publish this memory to the PEI Core
+ //
+ Status = PublishSystemMemory (MemoryBase, MemorySize);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Publish system RAM and reserve memory regions.
+
+**/
+VOID
+InitializeRamRegions (
+ VOID
+ )
+{
+ /*
+ * M-mode FW can be loaded anywhere in memory but should not overlap
+ * with the EDK2. This can happen if some other boot code loads the
+ * M-mode firmware.
+ *
+ * The M-mode firmware memory should be marked as reserved memory
+ * so that OS doesn't use it.
+ */
+ DEBUG ((DEBUG_INFO, "%a: M-mode FW Memory Start:0x%lx End:0x%lx\n",
+ __FUNCTION__, MmodeResvBase, MmodeResvBase + MmodeResvSize));
+ AddReservedMemoryBaseSizeHob(MmodeResvBase, MmodeResvSize);
+
+ if (MmodeResvBase > SystemMemoryBase) {
+ DEBUG ((DEBUG_INFO, "%a: Free Memory Start:0x%lx End:0x%lx\n",
+ __FUNCTION__, SystemMemoryBase, MmodeResvBase));
+ AddMemoryRangeHob(SystemMemoryBase, MmodeResvBase);
+ }
+
+ DEBUG ((DEBUG_INFO, "%a: Free Memory Start:0x%lx End:0x%lx\n",
+ __FUNCTION__, MmodeResvBase + MmodeResvSize,
+ SystemMemoryBase + SystemMemorySize));
+ AddMemoryRangeHob(MmodeResvBase + MmodeResvSize,
+ SystemMemoryBase + SystemMemorySize);
+}
diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c b/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c
new file mode 100644
index 0000000000..27d50a0e56
--- /dev/null
+++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c
@@ -0,0 +1,372 @@
+/** @file
+ Platform PEI driver
+
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ResourcePublicationLib.h>
+#include <Library/PlatformPeiLib.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Ppi/MasterBootMode.h>
+#include <IndustryStandard/Pci22.h>
+
+#include "Platform.h"
+
+EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+ { EfiACPIMemoryNVS, 0x004 },
+ { EfiACPIReclaimMemory, 0x008 },
+ { EfiReservedMemoryType, 0x004 },
+ { EfiRuntimeServicesData, 0x024 },
+ { EfiRuntimeServicesCode, 0x030 },
+ { EfiBootServicesCode, 0x180 },
+ { EfiBootServicesData, 0xF00 },
+ { EfiMaxMemoryType, 0x000 }
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPeiMasterBootModePpiGuid,
+ NULL
+ }
+};
+
+STATIC EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+/**
+ Build memory map I/O range resource HOB using the
+ base address and size.
+
+ @param MemoryBase Memory map I/O base.
+ @param MemorySize Memory map I/O size.
+
+**/
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+/**
+ Build reserved memory range resource HOB.
+
+ @param MemoryBase Reserved memory range base address.
+ @param MemorySize Reserved memory range size.
+
+**/
+VOID
+AddReservedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_RESERVED,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+/**
+ Build memory map I/O resource using the base address
+ and the top address of memory range.
+
+ @param MemoryBase Memory map I/O range base address.
+ @param MemoryLimit The top address of memory map I/O range
+
+**/
+VOID
+AddIoMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+/**
+ Create memory range resource HOB using the memory base
+ address and size.
+
+ @param MemoryBase Memory range base address.
+ @param MemorySize Memory range size.
+
+**/
+VOID
+AddMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+/**
+ Create memory range resource HOB using memory base
+ address and top address of the memory range.
+
+ @param MemoryBase Memory range base address.
+ @param MemoryLimit Memory range size.
+
+**/
+VOID
+AddMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+/**
+ Create untested memory range resource HOB using memory base
+ address and top address of the memory range.
+
+ @param MemoryBase Memory range base address.
+ @param MemorySize Memory range size.
+
+**/
+VOID
+AddUntestedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+/**
+ Create untested memory range resource HOB using memory base
+ address and top address of the memory range.
+
+ @param MemoryBase Memory range base address.
+ @param MemoryLimit Memory range size.
+
+**/
+VOID
+AddUntestedMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+/**
+ Add PCI resource.
+
+**/
+VOID
+AddPciResource (
+ VOID
+ )
+{
+ //
+ // Platform-specific
+ //
+}
+
+/**
+ Platform memory map initialization.
+
+**/
+VOID
+MemMapInitialization (
+ VOID
+ )
+{
+ //
+ // Create Memory Type Information HOB
+ //
+ BuildGuidDataHob (
+ &gEfiMemoryTypeInformationGuid,
+ mDefaultMemoryTypeInformation,
+ sizeof (mDefaultMemoryTypeInformation)
+ );
+
+ //
+ // Add PCI IO Port space available for PCI resource allocations.
+ //
+ AddPciResource ();
+}
+
+/**
+ Platform misc initialization.
+
+**/
+VOID
+MiscInitialization (
+ VOID
+ )
+{
+ //
+ // Build the CPU HOB with guest RAM size dependent address width and 16-bits
+ // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
+ // S3 resume as well, so we build it unconditionally.)
+ //
+ // TODO: Determine this dynamically from the platform
+ // setting or the HART configuration.
+ //
+ BuildCpuHob (56, 32);
+}
+
+/**
+ Check if system returns from S3.
+
+ @return BOOLEAN TRUE, system returned from S3
+ FALSE, system is not returned from S3
+
+**/
+BOOLEAN
+CheckResumeFromS3 (
+ VOID
+ )
+{
+ //
+ // Platform implementation-specific
+ //
+ return FALSE;
+}
+
+/**
+ Platform boot mode initialization.
+
+**/
+VOID
+BootModeInitialization (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ if (CheckResumeFromS3()) {
+ DEBUG ((DEBUG_INFO, "This is wake from S3\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "This is normal boot\n"));
+ }
+
+ Status = PeiServicesSetBootMode (mBootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PeiServicesInstallPpi (mPpiBootMode);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Build processor information for U54 Coreplex processor.
+
+ @return EFI_SUCCESS Status.
+
+**/
+EFI_STATUS
+BuildCoreInformationHob (
+ VOID
+ )
+{
+// return BuildRiscVSmbiosHobs ();
+ return EFI_SUCCESS;
+}
+
+/**
+ Perform Platform PEI initialization.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializePlatform (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
+ Status = PlatformPeim();
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "PlatformPeim failed\n"));
+ ASSERT (FALSE);
+ }
+ BootModeInitialization ();
+ DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n"));
+ PublishPeiMemory ();
+ DEBUG ((DEBUG_INFO, "PEI memory published.\n"));
+ InitializeRamRegions ();
+ DEBUG ((DEBUG_INFO, "Platform RAM regions initiated.\n"));
+
+ if (mBootMode != BOOT_ON_S3_RESUME) {
+ PeiFvInitialization ();
+ MemMapInitialization ();
+ }
+
+ MiscInitialization ();
+ Status = BuildCoreInformationHob ();
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to build processor information HOB.\n"));
+ ASSERT (FALSE);
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h b/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h
new file mode 100644
index 0000000000..6c23c722a3
--- /dev/null
+++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h
@@ -0,0 +1,97 @@
+/** @file
+ Platform PEI module include file.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PLATFORM_PEI_H_INCLUDED_
+#define PLATFORM_PEI_H_INCLUDED_
+
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddIoMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddUntestedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddReservedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddUntestedMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddressWidthInitialization (
+ VOID
+ );
+
+EFI_STATUS
+PublishPeiMemory (
+ VOID
+ );
+
+UINT32
+GetSystemMemorySizeBelow4gb (
+ VOID
+ );
+
+VOID
+InitializeRamRegions (
+ VOID
+ );
+
+EFI_STATUS
+PeiFvInitialization (
+ VOID
+ );
+
+EFI_STATUS
+InitializeXen (
+ VOID
+ );
+
+/**
+ Build processor and platform information for the U5 platform
+
+ @return EFI_SUCCESS Status.
+
+**/
+EFI_STATUS
+BuildRiscVSmbiosHobs (
+ VOID
+ );
+
+#endif // _PLATFORM_PEI_H_INCLUDED_
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 15/17] UefiCpuPkg/CpuDxe: Refactor to allow other CPU architectures
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (13 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 14/17] MdeModulePkg/Universal: Add PlatformPei module for RISC-V Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-06 17:08 ` [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module Sunil V L
` (2 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
Currently, CpuDxe driver is mostly x86 specific. Refactor the INF
to allow other architectures like RISC-V.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
UefiCpuPkg/CpuDxe/CpuDxe.inf | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
index 2352418992..4f2ea42f16 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
@@ -29,20 +29,22 @@
DebugLib
DxeServicesTableLib
MemoryAllocationLib
- MtrrLib
UefiBootServicesTableLib
UefiDriverEntryPoint
- LocalApicLib
- UefiCpuLib
UefiLib
CpuExceptionHandlerLib
HobLib
ReportStatusCodeLib
- MpInitLib
TimerLib
PeCoffGetEntryPointLib
-[Sources]
+[LibraryClasses.IA32, LibraryClasses.X64]
+ LocalApicLib
+ MpInitLib
+ MtrrLib
+ UefiCpuLib
+
+[Sources.IA32, Sources.X64]
CpuDxe.c
CpuDxe.h
CpuGdt.c
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (14 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 15/17] UefiCpuPkg/CpuDxe: Refactor to allow other CPU architectures Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-07 9:32 ` Chang, Abner
2022-09-06 17:08 ` [RFC PATCH 17/17] MdeModulePkg/Universal: Add TimerDxe module Sunil V L
2022-09-07 5:54 ` [edk2-devel] [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Gerd Hoffmann
17 siblings, 1 reply; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
This DXE module initializes the RISC-V CPU by installing
the CPU specific ARCH protocol handlers. This also initializes
the RISCV_EFI_BOOT_PROTOCOL which is required on RISC-V
platforms.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
UefiCpuPkg/CpuDxe/CpuDxe.inf | 16 +-
UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 337 +++++++++++++++++++++++++++++
UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 200 +++++++++++++++++
3 files changed, 552 insertions(+), 1 deletion(-)
create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
index 4f2ea42f16..17cf2b1ecd 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
@@ -1,8 +1,12 @@
## @file
-# CPU driver installs CPU Architecture Protocol and CPU MP protocol.
+# On X86, CPU driver installs CPU Architecture Protocol and CPU MP protocol.
+#
+# On RISC-V, CPU driver installs CPU Architecture Protocol and RISC-V boot
+# protocol
#
# Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -44,6 +48,9 @@
MtrrLib
UefiCpuLib
+[LibraryClasses.RISCV64]
+ RiscVSbiLib
+
[Sources.IA32, Sources.X64]
CpuDxe.c
CpuDxe.h
@@ -62,11 +69,18 @@
X64/CpuAsm.nasm
X64/PagingAttribute.c
+[Sources.RISCV64]
+ RiscV64/CpuDxe.c
+ RiscV64/CpuDxe.h
+
[Protocols]
gEfiCpuArchProtocolGuid ## PRODUCES
gEfiMpServiceProtocolGuid ## PRODUCES
gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES
+[Protocols.RISCV64]
+ gRiscVEfiBootProtocolGuid ## PRODUCES
+
[Guids]
gIdleLoopEventGuid ## CONSUMES ## Event
gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES ## SystemTable
diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
new file mode 100644
index 0000000000..4112b6b8c6
--- /dev/null
+++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
@@ -0,0 +1,337 @@
+/** @file
+ RISC-V CPU DXE driver.
+
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/PcdLib.h>
+#include <Register/RiscV64/RiscVAsm.h>
+#include "CpuDxe.h"
+
+//
+// Global Variables
+//
+STATIC BOOLEAN mInterruptState = FALSE;
+STATIC EFI_HANDLE mCpuHandle = NULL;
+STATIC UINTN mBootHartId;
+RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol;
+
+EFI_STATUS
+EFIAPI
+RiscvGetBootHartId (
+ IN RISCV_EFI_BOOT_PROTOCOL *This,
+ OUT UINTN *BootHartId
+ )
+{
+ if((This != &gRiscvBootProtocol) || (BootHartId == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *BootHartId = mBootHartId;
+ return EFI_SUCCESS;
+}
+
+RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol = {
+ RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION,
+ RiscvGetBootHartId
+};
+
+EFI_CPU_ARCH_PROTOCOL gCpu = {
+ CpuFlushCpuDataCache,
+ CpuEnableInterrupt,
+ CpuDisableInterrupt,
+ CpuGetInterruptState,
+ CpuInit,
+ CpuRegisterInterruptHandler,
+ CpuGetTimerValue,
+ CpuSetMemoryAttributes,
+ 1, // NumberOfTimers
+ 4 // DmaBufferAlignment
+};
+
+//
+// CPU Arch Protocol Functions
+//
+
+/**
+ Flush CPU data cache. If the instruction cache is fully coherent
+ with all DMA operations then function can just return EFI_SUCCESS.
+
+ @param This Protocol instance structure
+ @param Start Physical address to start flushing from.
+ @param Length Number of bytes to flush. Round up to chipset
+ granularity.
+ @param FlushType Specifies the type of flush operation to perform.
+
+ @retval EFI_SUCCESS If cache was flushed
+ @retval EFI_UNSUPPORTED If flush type is not supported.
+ @retval EFI_DEVICE_ERROR If requested range could not be flushed.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Enables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were enabled in the CPU
+ @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ EnableInterrupts ();
+ mInterruptState = TRUE;
+ return EFI_SUCCESS;
+}
+
+/**
+ Disables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuDisableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ DisableInterrupts ();
+ mInterruptState = FALSE;
+ return EFI_SUCCESS;
+}
+
+/**
+ Return the state of interrupts.
+
+ @param This Protocol instance structure
+ @param State Pointer to the CPU's current interrupt state
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_INVALID_PARAMETER State is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetInterruptState (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
+ )
+{
+ if (State == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *State = mInterruptState;
+ return EFI_SUCCESS;
+}
+
+/**
+ Generates an INIT to the CPU.
+
+ @param This Protocol instance structure
+ @param InitType Type of CPU INIT to perform
+
+ @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
+ seen.
+ @retval EFI_DEVICE_ERROR If CPU INIT failed.
+ @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInit (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Registers a function to be called from the CPU interrupt handler.
+
+ @param This Protocol instance structure
+ @param InterruptType Defines which interrupt to hook. IA-32
+ valid range is 0x00 through 0xFF
+ @param InterruptHandler A pointer to a function of type
+ EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. A null
+ pointer is an error condition.
+
+ @retval EFI_SUCCESS If handler installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
+ for InterruptType was previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
+ InterruptType was not previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
+ is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuRegisterInterruptHandler (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ )
+{
+ return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
+}
+
+/**
+ Returns a timer value from one of the CPU's internal timers. There is no
+ inherent time interval between ticks but is a function of the CPU frequency.
+
+ @param This - Protocol instance structure.
+ @param TimerIndex - Specifies which CPU timer is requested.
+ @param TimerValue - Pointer to the returned timer value.
+ @param TimerPeriod - A pointer to the amount of time that passes
+ in femtoseconds (10-15) for each increment
+ of TimerValue. If TimerValue does not
+ increment at a predictable rate, then 0 is
+ returned. The amount of time that has
+ passed between two calls to GetTimerValue()
+ can be calculated with the formula
+ (TimerValue2 - TimerValue1) * TimerPeriod.
+ This parameter is optional and may be NULL.
+
+ @retval EFI_SUCCESS - If the CPU timer count was returned.
+ @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
+ @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
+ @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetTimerValue (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
+
+ This function modifies the attributes for the memory region specified by BaseAddress and
+ Length from their current attributes to the attributes specified by Attributes.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param BaseAddress The physical address that is the start address of a memory region.
+ @param Length The size in bytes of the memory region.
+ @param Attributes The bit mask of attributes to set for the memory region.
+
+ @retval EFI_SUCCESS The attributes were set for the memory region.
+ @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
+ BaseAddress and Length cannot be modified.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ Attributes specified an illegal combination of attributes that
+ cannot be set together.
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
+ the memory resource range.
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
+ resource range specified by BaseAddress and Length.
+ The bit mask of attributes is not support for the memory resource
+ range specified by BaseAddress and Length.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuSetMemoryAttributes (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ )
+{
+ DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __FUNCTION__));
+ return EFI_SUCCESS;
+}
+
+/**
+ Initialize the state information for the CPU Architectural Protocol.
+
+ @param ImageHandle Image handle this driver.
+ @param SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS Thread can be successfully created
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Cannot create the thread
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpu (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
+
+ GetFirmwareContextPointer (&FirmwareContext);
+ ASSERT (FirmwareContext != NULL);
+ if (FirmwareContext == NULL) {
+ DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_CONTEXT\n"));
+ return EFI_NOT_FOUND;
+ }
+ DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__, FirmwareContext));
+
+ mBootHartId = FirmwareContext->BootHartId;
+ DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n", __FUNCTION__, mBootHartId));
+
+
+ InitializeCpuExceptionHandlers(NULL);
+
+ //
+ // Make sure interrupts are disabled
+ //
+ DisableInterrupts ();
+
+ Status = gBS->InstallProtocolInterface (&ImageHandle,
+ &gRiscVEfiBootProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &gRiscvBootProtocol
+ );
+
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install CPU Architectural Protocol
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mCpuHandle,
+ &gEfiCpuArchProtocolGuid,
+ &gCpu,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
new file mode 100644
index 0000000000..f039759dbd
--- /dev/null
+++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
@@ -0,0 +1,200 @@
+/** @file
+ RISC-V CPU DXE module header file.
+
+ Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CPU_DXE_H_
+#define CPU_DXE_H_
+
+#include <PiDxe.h>
+
+#include <Protocol/Cpu.h>
+#include <Protocol/RiscVBootProtocol.h>
+#include <Library/RiscVSbiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/CpuExceptionHandlerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+
+/**
+ Flush CPU data cache. If the instruction cache is fully coherent
+ with all DMA operations then function can just return EFI_SUCCESS.
+
+ @param This Protocol instance structure
+ @param Start Physical address to start flushing from.
+ @param Length Number of bytes to flush. Round up to chipset
+ granularity.
+ @param FlushType Specifies the type of flush operation to perform.
+
+ @retval EFI_SUCCESS If cache was flushed
+ @retval EFI_UNSUPPORTED If flush type is not supported.
+ @retval EFI_DEVICE_ERROR If requested range could not be flushed.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ );
+
+/**
+ Enables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were enabled in the CPU
+ @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ );
+
+/**
+ Disables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuDisableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ );
+
+/**
+ Return the state of interrupts.
+
+ @param This Protocol instance structure
+ @param State Pointer to the CPU's current interrupt state
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_INVALID_PARAMETER State is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetInterruptState (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
+ );
+
+/**
+ Generates an INIT to the CPU.
+
+ @param This Protocol instance structure
+ @param InitType Type of CPU INIT to perform
+
+ @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
+ seen.
+ @retval EFI_DEVICE_ERROR If CPU INIT failed.
+ @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInit (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
+ );
+
+/**
+ Registers a function to be called from the CPU interrupt handler.
+
+ @param This Protocol instance structure
+ @param InterruptType Defines which interrupt to hook. IA-32
+ valid range is 0x00 through 0xFF
+ @param InterruptHandler A pointer to a function of type
+ EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. A null
+ pointer is an error condition.
+
+ @retval EFI_SUCCESS If handler installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
+ for InterruptType was previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
+ InterruptType was not previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
+ is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuRegisterInterruptHandler (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ );
+
+/**
+ Returns a timer value from one of the CPU's internal timers. There is no
+ inherent time interval between ticks but is a function of the CPU frequency.
+
+ @param This - Protocol instance structure.
+ @param TimerIndex - Specifies which CPU timer is requested.
+ @param TimerValue - Pointer to the returned timer value.
+ @param TimerPeriod - A pointer to the amount of time that passes
+ in femtoseconds (10-15) for each increment
+ of TimerValue. If TimerValue does not
+ increment at a predictable rate, then 0 is
+ returned. The amount of time that has
+ passed between two calls to GetTimerValue()
+ can be calculated with the formula
+ (TimerValue2 - TimerValue1) * TimerPeriod.
+ This parameter is optional and may be NULL.
+
+ @retval EFI_SUCCESS - If the CPU timer count was returned.
+ @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
+ @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
+ @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetTimerValue (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
+ );
+
+/**
+ Set memory cacheability attributes for given range of memeory.
+
+ @param This Protocol instance structure
+ @param BaseAddress Specifies the start address of the
+ memory range
+ @param Length Specifies the length of the memory range
+ @param Attributes The memory cacheability for the memory range
+
+ @retval EFI_SUCCESS If the cacheability of that memory range is
+ set successfully
+ @retval EFI_UNSUPPORTED If the desired operation cannot be done
+ @retval EFI_INVALID_PARAMETER The input parameter is not correct,
+ such as Length = 0
+
+**/
+EFI_STATUS
+EFIAPI
+CpuSetMemoryAttributes (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ );
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [RFC PATCH 17/17] MdeModulePkg/Universal: Add TimerDxe module
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (15 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module Sunil V L
@ 2022-09-06 17:08 ` Sunil V L
2022-09-07 5:54 ` [edk2-devel] [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Gerd Hoffmann
17 siblings, 0 replies; 24+ messages in thread
From: Sunil V L @ 2022-09-06 17:08 UTC (permalink / raw)
To: devel
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel,
Sunil V L
This DXE module initializes the timer interrupt handler
and installs the Arch Timer protocol.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
.../Universal/TimerDxe/RiscV64/Timer.c | 293 ++++++++++++++++++
.../Universal/TimerDxe/RiscV64/Timer.h | 174 +++++++++++
MdeModulePkg/Universal/TimerDxe/Timer.uni | 15 +
MdeModulePkg/Universal/TimerDxe/TimerDxe.inf | 52 ++++
| 13 +
5 files changed, 547 insertions(+)
create mode 100644 MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.c
create mode 100644 MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.h
create mode 100644 MdeModulePkg/Universal/TimerDxe/Timer.uni
create mode 100644 MdeModulePkg/Universal/TimerDxe/TimerDxe.inf
create mode 100644 MdeModulePkg/Universal/TimerDxe/TimerExtra.uni
diff --git a/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.c b/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.c
new file mode 100644
index 0000000000..4deb91766d
--- /dev/null
+++ b/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.c
@@ -0,0 +1,293 @@
+/** @file
+ RISC-V Timer Architectural Protocol
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Timer.h"
+#include <Library/RiscVSbiLib.h>
+#include <Register/RiscV64/RiscVAsm.h>
+
+//
+// The handle onto which the Timer Architectural Protocol will be installed
+//
+STATIC EFI_HANDLE mTimerHandle = NULL;
+
+//
+// The Timer Architectural Protocol that this driver produces
+//
+EFI_TIMER_ARCH_PROTOCOL mTimer = {
+ TimerDriverRegisterHandler,
+ TimerDriverSetTimerPeriod,
+ TimerDriverGetTimerPeriod,
+ TimerDriverGenerateSoftInterrupt
+};
+
+//
+// Pointer to the CPU Architectural Protocol instance
+//
+EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+//
+// The notification function to call on every timer interrupt.
+// A bug in the compiler prevents us from initializing this here.
+//
+STATIC EFI_TIMER_NOTIFY mTimerNotifyFunction;
+
+//
+// The current period of the timer interrupt
+//
+STATIC UINT64 mTimerPeriod = 0;
+
+/**
+ Timer Interrupt Handler.
+
+ @param InterruptType The type of interrupt that occured
+ @param SystemContext A pointer to the system context when the interrupt occured
+**/
+
+VOID
+EFIAPI
+TimerInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ EFI_TPL OriginalTPL;
+ UINT64 RiscvTimer;
+
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+ if (mTimerNotifyFunction != NULL) {
+ mTimerNotifyFunction (mTimerPeriod);
+ }
+ csr_clear(CSR_SIE, SIP_STIP); // Disable SMode timer int
+ csr_clear(CSR_SIP, SIP_STIP);
+ if (mTimerPeriod == 0) {
+ gBS->RestoreTPL (OriginalTPL);
+ csr_clear(CSR_SIE, SIP_STIP); // Disable SMode timer int
+ return;
+ }
+ RiscvTimer = csr_read(CSR_TIME);
+ SbiSetTimer (RiscvTimer += mTimerPeriod);
+ gBS->RestoreTPL (OriginalTPL);
+ csr_set(CSR_SIE, SIP_STIP); // enable SMode timer int
+}
+
+/**
+
+ This function registers the handler NotifyFunction so it is called every time
+ the timer interrupt fires. It also passes the amount of time since the last
+ handler call to the NotifyFunction. If NotifyFunction is NULL, then the
+ handler is unregistered. If the handler is registered, then EFI_SUCCESS is
+ returned. If the CPU does not support registering a timer interrupt handler,
+ then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
+ when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not registered,
+ then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
+ register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+ is returned.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The function to call when a timer interrupt fires. This
+ function executes at TPL_HIGH_LEVEL. The DXE Core will
+ register a handler for the timer interrupt, so it can know
+ how much time has passed. This information is used to
+ signal timer based events. NULL will unregister the handler.
+
+ @retval EFI_SUCCESS The timer handler was registered.
+ @retval EFI_UNSUPPORTED The platform does not support timer interrupts.
+ @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
+ registered.
+ @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+ previously registered.
+ @retval EFI_DEVICE_ERROR The timer handler could not be registered.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverRegisterHandler (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN EFI_TIMER_NOTIFY NotifyFunction
+ )
+{
+ DEBUG ((DEBUG_INFO, "TimerDriverRegisterHandler(0x%lx) called\n", NotifyFunction));
+ mTimerNotifyFunction = NotifyFunction;
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+ by TimerPeriod. If the timer period is updated, then the selected timer
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+ If an error occurs while attempting to update the timer period, then the
+ timer hardware will be put back in its state prior to this call, and
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+ is disabled. This is not the same as disabling the CPU's interrupts.
+ Instead, it must either turn off the timer hardware, or it must adjust the
+ interrupt controller so that a CPU interrupt is not generated when the timer
+ interrupt fires.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+ returned. If the timer is programmable, then the timer period
+ will be rounded up to the nearest timer period that is supported
+ by the timer hardware. If TimerPeriod is set to 0, then the
+ timer interrupts will be disabled.
+
+ @retval EFI_SUCCESS The timer period was changed.
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverSetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN UINT64 TimerPeriod
+ )
+{
+ UINT64 RiscvTimer;
+
+ DEBUG ((DEBUG_INFO, "TimerDriverSetTimerPeriod(0x%lx)\n", TimerPeriod));
+
+ if (TimerPeriod == 0) {
+ mTimerPeriod = 0;
+ csr_clear(CSR_SIE, SIP_STIP); // disable timer int
+ return EFI_SUCCESS;
+ }
+
+ mTimerPeriod = TimerPeriod / 10; // convert unit from 100ns to 1us
+ RiscvTimer = csr_read(CSR_TIME);
+ SbiSetTimer(RiscvTimer + mTimerPeriod);
+
+ mCpu->EnableInterrupt(mCpu);
+ csr_set(CSR_SIE, SIP_STIP); // enable timer int
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function retrieves the period of timer interrupts in 100 ns units,
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+ returned, then the timer is currently disabled.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
+ 0 is returned, then the timer is currently disabled.
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
+ )
+{
+ *TimerPeriod = mTimerPeriod;
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function generates a soft timer interrupt. If the platform does not support soft
+ timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
+ If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
+ service, then a soft timer interrupt will be generated. If the timer interrupt is
+ enabled when this service is called, then the registered handler will be invoked. The
+ registered handler should not be able to distinguish a hardware-generated timer
+ interrupt from a software-generated timer interrupt.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The soft timer interrupt was generated.
+ @retval EFI_UNSUPPORTEDT The platform does not support the generation of soft timer interrupts.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGenerateSoftInterrupt (
+ IN EFI_TIMER_ARCH_PROTOCOL *This
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Initialize the Timer Architectural Protocol driver
+
+ @param ImageHandle ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Timer Architectural Protocol created
+ @retval EFI_OUT_OF_RESOURCES Not enough resources available to initialize driver.
+ @retval EFI_DEVICE_ERROR A device error occured attempting to initialize the driver.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Initialize the pointer to our notify function.
+ //
+ mTimerNotifyFunction = NULL;
+
+ //
+ // Make sure the Timer Architectural Protocol is not already installed in the system
+ //
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiTimerArchProtocolGuid);
+
+ //
+ // Find the CPU architectural protocol.
+ //
+ Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **) &mCpu);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Force the timer to be disabled
+ //
+ Status = TimerDriverSetTimerPeriod (&mTimer, 0);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install interrupt handler for RISC-V Timer.
+ //
+ Status = mCpu->RegisterInterruptHandler (mCpu, EXCEPT_RISCV_TIMER_INT, TimerInterruptHandler);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Force the timer to be enabled at its default period
+ //
+ Status = TimerDriverSetTimerPeriod (&mTimer, DEFAULT_TIMER_TICK_DURATION);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install the Timer Architectural Protocol onto a new handle
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mTimerHandle,
+ &gEfiTimerArchProtocolGuid, &mTimer,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.h b/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.h
new file mode 100644
index 0000000000..32f56f8fe1
--- /dev/null
+++ b/MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.h
@@ -0,0 +1,174 @@
+/** @file
+ RISC-V Timer Architectural Protocol definitions
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _TIMER_H_
+#define _TIMER_H_
+
+#include <PiDxe.h>
+
+#include <Protocol/Cpu.h>
+#include <Protocol/Timer.h>
+
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+
+//
+// RISC-V use 100us timer.
+// The default timer tick duration is set to 10 ms = 10 * 1000 * 10 100 ns units
+//
+#define DEFAULT_TIMER_TICK_DURATION 100000
+
+extern VOID RiscvSetTimerPeriod (UINT32 TimerPeriod);
+
+//
+// Function Prototypes
+//
+/**
+ Initialize the Timer Architectural Protocol driver
+
+ @param ImageHandle ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Timer Architectural Protocol created
+ @retval EFI_OUT_OF_RESOURCES Not enough resources available to initialize driver.
+ @retval EFI_DEVICE_ERROR A device error occured attempting to initialize the driver.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+;
+
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+ by TimerPeriod. If the timer period is updated, then the selected timer
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+ If an error occurs while attempting to update the timer period, then the
+ timer hardware will be put back in its state prior to this call, and
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+ is disabled. This is not the same as disabling the CPU's interrupts.
+ Instead, it must either turn off the timer hardware, or it must adjust the
+ interrupt controller so that a CPU interrupt is not generated when the timer
+ interrupt fires.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The rate to program the timer interrupt in 100 nS units. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+ returned. If the timer is programmable, then the timer period
+ will be rounded up to the nearest timer period that is supported
+ by the timer hardware. If TimerPeriod is set to 0, then the
+ timer interrupts will be disabled.
+
+ @retval EFI_SUCCESS The timer period was changed.
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverRegisterHandler (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN EFI_TIMER_NOTIFY NotifyFunction
+ )
+;
+
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+ by TimerPeriod. If the timer period is updated, then the selected timer
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+ If an error occurs while attempting to update the timer period, then the
+ timer hardware will be put back in its state prior to this call, and
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+ is disabled. This is not the same as disabling the CPU's interrupts.
+ Instead, it must either turn off the timer hardware, or it must adjust the
+ interrupt controller so that a CPU interrupt is not generated when the timer
+ interrupt fires.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+ returned. If the timer is programmable, then the timer period
+ will be rounded up to the nearest timer period that is supported
+ by the timer hardware. If TimerPeriod is set to 0, then the
+ timer interrupts will be disabled.
+
+ @retval EFI_SUCCESS The timer period was changed.
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverSetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN UINT64 TimerPeriod
+ )
+;
+
+/**
+
+ This function retrieves the period of timer interrupts in 100 ns units,
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+ returned, then the timer is currently disabled.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
+ 0 is returned, then the timer is currently disabled.
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
+ )
+;
+
+/**
+
+ This function generates a soft timer interrupt. If the platform does not support soft
+ timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
+ If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
+ service, then a soft timer interrupt will be generated. If the timer interrupt is
+ enabled when this service is called, then the registered handler will be invoked. The
+ registered handler should not be able to distinguish a hardware-generated timer
+ interrupt from a software-generated timer interrupt.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The soft timer interrupt was generated.
+ @retval EFI_UNSUPPORTEDT The platform does not support the generation of soft timer interrupts.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGenerateSoftInterrupt (
+ IN EFI_TIMER_ARCH_PROTOCOL *This
+ )
+;
+
+#endif
diff --git a/MdeModulePkg/Universal/TimerDxe/Timer.uni b/MdeModulePkg/Universal/TimerDxe/Timer.uni
new file mode 100644
index 0000000000..07272a8a78
--- /dev/null
+++ b/MdeModulePkg/Universal/TimerDxe/Timer.uni
@@ -0,0 +1,15 @@
+// /** @file
+//
+// Timer Arch protocol strings.
+//
+// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Timer driver that provides Timer Arch protocol"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Timer driver that provides Timer Arch protocol."
diff --git a/MdeModulePkg/Universal/TimerDxe/TimerDxe.inf b/MdeModulePkg/Universal/TimerDxe/TimerDxe.inf
new file mode 100644
index 0000000000..b291a1fcec
--- /dev/null
+++ b/MdeModulePkg/Universal/TimerDxe/TimerDxe.inf
@@ -0,0 +1,52 @@
+## @file
+# Timer Arch protocol module
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = Timer
+ MODULE_UNI_FILE = Timer.uni
+ FILE_GUID = 055DDAC6-9142-4013-BF20-FC2E5BC325C9
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = TimerDriverInitialize
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Packages]
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+ CpuLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[LibraryClasses.RISCV64]
+ RiscVSbiLib
+
+[Sources.RISCV64]
+ RiscV64/Timer.h
+ RiscV64/Timer.c
+
+[Protocols]
+ gEfiCpuArchProtocolGuid ## CONSUMES
+ gEfiTimerArchProtocolGuid ## PRODUCES
+
+[Depex]
+ gEfiCpuArchProtocolGuid
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ TimerExtra.uni
--git a/MdeModulePkg/Universal/TimerDxe/TimerExtra.uni b/MdeModulePkg/Universal/TimerDxe/TimerExtra.uni
new file mode 100644
index 0000000000..ad80afe267
--- /dev/null
+++ b/MdeModulePkg/Universal/TimerDxe/TimerExtra.uni
@@ -0,0 +1,13 @@
+// /** @file
+// Timer Localized Strings and Content
+//
+// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"Timer DXE Driver"
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [edk2-devel] [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
` (16 preceding siblings ...)
2022-09-06 17:08 ` [RFC PATCH 17/17] MdeModulePkg/Universal: Add TimerDxe module Sunil V L
@ 2022-09-07 5:54 ` Gerd Hoffmann
17 siblings, 0 replies; 24+ messages in thread
From: Gerd Hoffmann @ 2022-09-07 5:54 UTC (permalink / raw)
To: devel, sunilvl
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Abner Chang,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel
Hi,
> RISC-V virt needs following packages from ARM. Need feedback whether they can
> be moved to a common location. Current RISC-V virt model DSC file include them
> directly.
> - ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> - ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
> - ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf
> - ArmVirtPkg/Library/NorFlashQemuLib/NorFlashQemuLib.inf
OvmfPkg is the place for both the x64 code and code shared by virt
platforms (like virtio drivers). So the ArmVirtPkg code should move to
OvmfPkg (and I think some modules have already been moved over from
armvirt because riscv needs them too).
Not sure about ArmPlatformPkg
take care,
Gerd
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module
2022-09-06 17:08 ` [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module Sunil V L
@ 2022-09-07 9:32 ` Chang, Abner
2022-09-07 11:22 ` Sunil V L
0 siblings, 1 reply; 24+ messages in thread
From: Chang, Abner @ 2022-09-07 9:32 UTC (permalink / raw)
To: Sunil V L, devel@edk2.groups.io
Cc: Jian J Wang, Liming Gao, Eric Dong, Ray Ni, Rahul Kumar,
Debkumar De, Catharine West, Daniel Schaefer, Leif Lindholm,
Ard Biesheuvel, Heinrich Schuchardt, Anup Patel
[AMD Official Use Only - General]
Hi Sunil and UefiCpuPkg maintainers,
For CpuDxe case, I think we should abstract CpuDxe to accommodate all processor architectures instead of having copy for each archs. CpuDxeCommon.c can have the generic protocol structure and the installation functions, and CpuDxeCommon.h has the general definitions. So does CpuMp related files. Move processor architecture dependent files to under arch folders. AMD may have some differences with Intel so we will have CpuDxeAmd.inf under CpuDxe\. AMD is revising SmmFeatureCpuLib base on the similar concept. I think this makes the module looks simple and architectural. Furthermore, the similar concept should apply to all modules (if necessary) under UefiCpuPkg.
I think we should revise CpuDxe before adding new arch such as RISC-V and Loongson64 to this module.
Here is a BZ for UefiCpuPkg rearchitecture, https://bugzilla.tianocore.org/show_bug.cgi?id=3860
Abner
Something looks like below,
CpuDxe\X86\Ia32\
\IA32\CpuAsm.asm
\IA32\PageAttribute.c
\X86\X64\
\X64\CpuAsm.asm
\X64\PageAttribute.c
\X86\CpuGdt.c
\CpuGdt.h
\CpuPageTable.C
\CpuPageTableh.h
\CpuDxe.c
\RISCV\RISCV64\
\RISCV64\CpuDxe.h
\CpuDxe.c
\ARM\ARM\
\AARCH64\
\CpuDxe.c
\CpuDxeCommon.c
\CpuMpCommon.c
\CpuDxeCommon.h
\CpuMpCommon.h
\CpuDxe.inf
> -----Original Message-----
> From: Sunil V L <sunilvl@ventanamicro.com>
> Sent: Wednesday, September 7, 2022 1:09 AM
> To: devel@edk2.groups.io
> Cc: Jian J Wang <jian.j.wang@intel.com>; Liming Gao
> <gaoliming@byosoft.com.cn>; Eric Dong <eric.dong@intel.com>; Ray Ni
> <ray.ni@intel.com>; Rahul Kumar <rahul1.kumar@intel.com>; Debkumar De
> <debkumar.de@intel.com>; Catharine West <catharine.west@intel.com>;
> Daniel Schaefer <git@danielschaefer.me>; Chang, Abner
> <Abner.Chang@amd.com>; Leif Lindholm <quic_llindhol@quicinc.com>; Ard
> Biesheuvel <ardb@kernel.org>; Heinrich Schuchardt
> <heinrich.schuchardt@canonical.com>; Anup Patel
> <apatel@ventanamicro.com>; Sunil V L <sunilvl@ventanamicro.com>
> Subject: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in
> CpuDxe module
>
> [CAUTION: External Email]
>
> This DXE module initializes the RISC-V CPU by installing the CPU specific ARCH
> protocol handlers. This also initializes the RISCV_EFI_BOOT_PROTOCOL which
> is required on RISC-V platforms.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
> UefiCpuPkg/CpuDxe/CpuDxe.inf | 16 +-
> UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 337
> +++++++++++++++++++++++++++++
> UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 200 +++++++++++++++++
> 3 files changed, 552 insertions(+), 1 deletion(-) create mode 100644
> UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
>
> diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 4f2ea42f16..17cf2b1ecd 100644
> --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> @@ -1,8 +1,12 @@
> ## @file
>
> -# CPU driver installs CPU Architecture Protocol and CPU MP protocol.
>
> +# On X86, CPU driver installs CPU Architecture Protocol and CPU MP
> protocol.
>
> +#
>
> +# On RISC-V, CPU driver installs CPU Architecture Protocol and RISC-V
> +boot
>
> +# protocol
>
> #
>
> # Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>
>
> # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>
> +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> +reserved.<BR>
>
> #
>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #
>
> @@ -44,6 +48,9 @@
> MtrrLib
>
> UefiCpuLib
>
>
>
> +[LibraryClasses.RISCV64]
>
> + RiscVSbiLib
>
> +
>
> [Sources.IA32, Sources.X64]
>
> CpuDxe.c
>
> CpuDxe.h
>
> @@ -62,11 +69,18 @@
> X64/CpuAsm.nasm
>
> X64/PagingAttribute.c
>
>
>
> +[Sources.RISCV64]
>
> + RiscV64/CpuDxe.c
>
> + RiscV64/CpuDxe.h
>
> +
>
> [Protocols]
>
> gEfiCpuArchProtocolGuid ## PRODUCES
>
> gEfiMpServiceProtocolGuid ## PRODUCES
>
> gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES
>
>
>
> +[Protocols.RISCV64]
>
> + gRiscVEfiBootProtocolGuid ## PRODUCES
>
> +
>
> [Guids]
>
> gIdleLoopEventGuid ## CONSUMES ## Event
>
> gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES ##
> SystemTable
>
> diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> new file mode 100644
> index 0000000000..4112b6b8c6
> --- /dev/null
> +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> @@ -0,0 +1,337 @@
> +/** @file
>
> + RISC-V CPU DXE driver.
>
> +
>
> + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
>
> + Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> + reserved.<BR>
>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +#include <Library/PcdLib.h>
>
> +#include <Register/RiscV64/RiscVAsm.h>
>
> +#include "CpuDxe.h"
>
> +
>
> +//
>
> +// Global Variables
>
> +//
>
> +STATIC BOOLEAN mInterruptState = FALSE;
>
> +STATIC EFI_HANDLE mCpuHandle = NULL;
>
> +STATIC UINTN mBootHartId;
>
> +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol;
>
> +
>
> +EFI_STATUS
>
> +EFIAPI
>
> +RiscvGetBootHartId (
>
> + IN RISCV_EFI_BOOT_PROTOCOL *This,
>
> + OUT UINTN *BootHartId
>
> + )
>
> +{
>
> + if((This != &gRiscvBootProtocol) || (BootHartId == NULL)) {
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + *BootHartId = mBootHartId;
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol = {
>
> + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION,
>
> + RiscvGetBootHartId
>
> +};
>
> +
>
> +EFI_CPU_ARCH_PROTOCOL gCpu = {
>
> + CpuFlushCpuDataCache,
>
> + CpuEnableInterrupt,
>
> + CpuDisableInterrupt,
>
> + CpuGetInterruptState,
>
> + CpuInit,
>
> + CpuRegisterInterruptHandler,
>
> + CpuGetTimerValue,
>
> + CpuSetMemoryAttributes,
>
> + 1, // NumberOfTimers
>
> + 4 // DmaBufferAlignment
>
> +};
>
> +
>
> +//
>
> +// CPU Arch Protocol Functions
>
> +//
>
> +
>
> +/**
>
> + Flush CPU data cache. If the instruction cache is fully coherent
>
> + with all DMA operations then function can just return EFI_SUCCESS.
>
> +
>
> + @param This Protocol instance structure
>
> + @param Start Physical address to start flushing from.
>
> + @param Length Number of bytes to flush. Round up to chipset
>
> + granularity.
>
> + @param FlushType Specifies the type of flush operation to perform.
>
> +
>
> + @retval EFI_SUCCESS If cache was flushed
>
> + @retval EFI_UNSUPPORTED If flush type is not supported.
>
> + @retval EFI_DEVICE_ERROR If requested range could not be flushed.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuFlushCpuDataCache (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This,
>
> + IN EFI_PHYSICAL_ADDRESS Start,
>
> + IN UINT64 Length,
>
> + IN EFI_CPU_FLUSH_TYPE FlushType
>
> + )
>
> +{
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + Enables CPU interrupts.
>
> +
>
> + @param This Protocol instance structure
>
> +
>
> + @retval EFI_SUCCESS If interrupts were enabled in the CPU
>
> + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuEnableInterrupt (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This
>
> + )
>
> +{
>
> + EnableInterrupts ();
>
> + mInterruptState = TRUE;
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + Disables CPU interrupts.
>
> +
>
> + @param This Protocol instance structure
>
> +
>
> + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
>
> + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuDisableInterrupt (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This
>
> + )
>
> +{
>
> + DisableInterrupts ();
>
> + mInterruptState = FALSE;
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + Return the state of interrupts.
>
> +
>
> + @param This Protocol instance structure
>
> + @param State Pointer to the CPU's current interrupt state
>
> +
>
> + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
>
> + @retval EFI_INVALID_PARAMETER State is NULL.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuGetInterruptState (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This,
>
> + OUT BOOLEAN *State
>
> + )
>
> +{
>
> + if (State == NULL) {
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + *State = mInterruptState;
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + Generates an INIT to the CPU.
>
> +
>
> + @param This Protocol instance structure
>
> + @param InitType Type of CPU INIT to perform
>
> +
>
> + @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
>
> + seen.
>
> + @retval EFI_DEVICE_ERROR If CPU INIT failed.
>
> + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuInit (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This,
>
> + IN EFI_CPU_INIT_TYPE InitType
>
> + )
>
> +{
>
> + return EFI_UNSUPPORTED;
>
> +}
>
> +
>
> +/**
>
> + Registers a function to be called from the CPU interrupt handler.
>
> +
>
> + @param This Protocol instance structure
>
> + @param InterruptType Defines which interrupt to hook. IA-32
>
> + valid range is 0x00 through 0xFF
>
> + @param InterruptHandler A pointer to a function of type
>
> + EFI_CPU_INTERRUPT_HANDLER that is
> + called
>
> + when a processor interrupt occurs. A
> + null
>
> + pointer is an error condition.
>
> +
>
> + @retval EFI_SUCCESS If handler installed or uninstalled.
>
> + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a
> handler
>
> + for InterruptType was previously installed.
>
> + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a
> + handler for
>
> + InterruptType was not previously installed.
>
> + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
>
> + is not supported.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuRegisterInterruptHandler (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This,
>
> + IN EFI_EXCEPTION_TYPE InterruptType,
>
> + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
>
> + )
>
> +{
>
> + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
>
> +}
>
> +
>
> +/**
>
> + Returns a timer value from one of the CPU's internal timers. There is
> + no
>
> + inherent time interval between ticks but is a function of the CPU
> frequency.
>
> +
>
> + @param This - Protocol instance structure.
>
> + @param TimerIndex - Specifies which CPU timer is requested.
>
> + @param TimerValue - Pointer to the returned timer value.
>
> + @param TimerPeriod - A pointer to the amount of time that passes
>
> + in femtoseconds (10-15) for each
> + increment
>
> + of TimerValue. If TimerValue does not
>
> + increment at a predictable rate, then 0
> + is
>
> + returned. The amount of time that has
>
> + passed between two calls to
> + GetTimerValue()
>
> + can be calculated with the formula
>
> + (TimerValue2 - TimerValue1) * TimerPeriod.
>
> + This parameter is optional and may be NULL.
>
> +
>
> + @retval EFI_SUCCESS - If the CPU timer count was returned.
>
> + @retval EFI_UNSUPPORTED - If the CPU does not have any readable
> timers.
>
> + @retval EFI_DEVICE_ERROR - If an error occurred while reading the
> timer.
>
> + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue
> is NULL.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuGetTimerValue (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This,
>
> + IN UINT32 TimerIndex,
>
> + OUT UINT64 *TimerValue,
>
> + OUT UINT64 *TimerPeriod OPTIONAL
>
> + )
>
> +{
>
> + return EFI_UNSUPPORTED;
>
> +}
>
> +
>
> +/**
>
> + Implementation of SetMemoryAttributes() service of CPU Architecture
> Protocol.
>
> +
>
> + This function modifies the attributes for the memory region specified
> + by BaseAddress and
>
> + Length from their current attributes to the attributes specified by
> Attributes.
>
> +
>
> + @param This The EFI_CPU_ARCH_PROTOCOL instance.
>
> + @param BaseAddress The physical address that is the start address of a
> memory region.
>
> + @param Length The size in bytes of the memory region.
>
> + @param Attributes The bit mask of attributes to set for the memory
> region.
>
> +
>
> + @retval EFI_SUCCESS The attributes were set for the memory region.
>
> + @retval EFI_ACCESS_DENIED The attributes for the memory resource
> range specified by
>
> + BaseAddress and Length cannot be modified.
>
> + @retval EFI_INVALID_PARAMETER Length is zero.
>
> + Attributes specified an illegal
> + combination of attributes that
>
> + cannot be set together.
>
> + @retval EFI_OUT_OF_RESOURCES There are not enough system
> resources
> + to modify the attributes of
>
> + the memory resource range.
>
> + @retval EFI_UNSUPPORTED The processor does not support one or
> more bytes of the memory
>
> + resource range specified by BaseAddress and Length.
>
> + The bit mask of attributes is not
> + support for the memory resource
>
> + range specified by BaseAddress and Length.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuSetMemoryAttributes (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This,
>
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
>
> + IN UINT64 Length,
>
> + IN UINT64 Attributes
>
> + )
>
> +{
>
> + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n",
> + __FUNCTION__));
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + Initialize the state information for the CPU Architectural Protocol.
>
> +
>
> + @param ImageHandle Image handle this driver.
>
> + @param SystemTable Pointer to the System Table.
>
> +
>
> + @retval EFI_SUCCESS Thread can be successfully created
>
> + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
>
> + @retval EFI_DEVICE_ERROR Cannot create the thread
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +InitializeCpu (
>
> + IN EFI_HANDLE ImageHandle,
>
> + IN EFI_SYSTEM_TABLE *SystemTable
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
>
> +
>
> + GetFirmwareContextPointer (&FirmwareContext);
>
> + ASSERT (FirmwareContext != NULL);
>
> + if (FirmwareContext == NULL) {
>
> + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of
> + EFI_RISCV_FIRMWARE_CONTEXT\n"));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n",
> + __FUNCTION__, FirmwareContext));
>
> +
>
> + mBootHartId = FirmwareContext->BootHartId;
>
> + DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n", __FUNCTION__,
> + mBootHartId));
>
> +
>
> +
>
> + InitializeCpuExceptionHandlers(NULL);
>
> +
>
> + //
>
> + // Make sure interrupts are disabled
>
> + //
>
> + DisableInterrupts ();
>
> +
>
> + Status = gBS->InstallProtocolInterface (&ImageHandle,
>
> + &gRiscVEfiBootProtocolGuid,
>
> + EFI_NATIVE_INTERFACE,
>
> + &gRiscvBootProtocol
>
> + );
>
> +
>
> + ASSERT_EFI_ERROR (Status);
>
> +
>
> + //
>
> + // Install CPU Architectural Protocol
>
> + //
>
> + Status = gBS->InstallMultipleProtocolInterfaces (
>
> + &mCpuHandle,
>
> + &gEfiCpuArchProtocolGuid,
>
> + &gCpu,
>
> + NULL
>
> + );
>
> + ASSERT_EFI_ERROR (Status);
>
> + return Status;
>
> +}
>
> diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> new file mode 100644
> index 0000000000..f039759dbd
> --- /dev/null
> +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> @@ -0,0 +1,200 @@
> +/** @file
>
> + RISC-V CPU DXE module header file.
>
> +
>
> + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>
>
> + Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> + reserved.<BR>
>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +#ifndef CPU_DXE_H_
>
> +#define CPU_DXE_H_
>
> +
>
> +#include <PiDxe.h>
>
> +
>
> +#include <Protocol/Cpu.h>
>
> +#include <Protocol/RiscVBootProtocol.h>
>
> +#include <Library/RiscVSbiLib.h>
>
> +#include <Library/BaseLib.h>
>
> +#include <Library/CpuExceptionHandlerLib.h>
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/UefiBootServicesTableLib.h>
>
> +#include <Library/UefiDriverEntryPoint.h>
>
> +
>
> +/**
>
> + Flush CPU data cache. If the instruction cache is fully coherent
>
> + with all DMA operations then function can just return EFI_SUCCESS.
>
> +
>
> + @param This Protocol instance structure
>
> + @param Start Physical address to start flushing from.
>
> + @param Length Number of bytes to flush. Round up to chipset
>
> + granularity.
>
> + @param FlushType Specifies the type of flush operation to perform.
>
> +
>
> + @retval EFI_SUCCESS If cache was flushed
>
> + @retval EFI_UNSUPPORTED If flush type is not supported.
>
> + @retval EFI_DEVICE_ERROR If requested range could not be flushed.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuFlushCpuDataCache (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This,
>
> + IN EFI_PHYSICAL_ADDRESS Start,
>
> + IN UINT64 Length,
>
> + IN EFI_CPU_FLUSH_TYPE FlushType
>
> + );
>
> +
>
> +/**
>
> + Enables CPU interrupts.
>
> +
>
> + @param This Protocol instance structure
>
> +
>
> + @retval EFI_SUCCESS If interrupts were enabled in the CPU
>
> + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuEnableInterrupt (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This
>
> + );
>
> +
>
> +/**
>
> + Disables CPU interrupts.
>
> +
>
> + @param This Protocol instance structure
>
> +
>
> + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
>
> + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuDisableInterrupt (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This
>
> + );
>
> +
>
> +/**
>
> + Return the state of interrupts.
>
> +
>
> + @param This Protocol instance structure
>
> + @param State Pointer to the CPU's current interrupt state
>
> +
>
> + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
>
> + @retval EFI_INVALID_PARAMETER State is NULL.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuGetInterruptState (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This,
>
> + OUT BOOLEAN *State
>
> + );
>
> +
>
> +/**
>
> + Generates an INIT to the CPU.
>
> +
>
> + @param This Protocol instance structure
>
> + @param InitType Type of CPU INIT to perform
>
> +
>
> + @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
>
> + seen.
>
> + @retval EFI_DEVICE_ERROR If CPU INIT failed.
>
> + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuInit (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This,
>
> + IN EFI_CPU_INIT_TYPE InitType
>
> + );
>
> +
>
> +/**
>
> + Registers a function to be called from the CPU interrupt handler.
>
> +
>
> + @param This Protocol instance structure
>
> + @param InterruptType Defines which interrupt to hook. IA-32
>
> + valid range is 0x00 through 0xFF
>
> + @param InterruptHandler A pointer to a function of type
>
> + EFI_CPU_INTERRUPT_HANDLER that is
> + called
>
> + when a processor interrupt occurs. A
> + null
>
> + pointer is an error condition.
>
> +
>
> + @retval EFI_SUCCESS If handler installed or uninstalled.
>
> + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a
> handler
>
> + for InterruptType was previously installed.
>
> + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a
> + handler for
>
> + InterruptType was not previously installed.
>
> + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
>
> + is not supported.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuRegisterInterruptHandler (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This,
>
> + IN EFI_EXCEPTION_TYPE InterruptType,
>
> + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
>
> + );
>
> +
>
> +/**
>
> + Returns a timer value from one of the CPU's internal timers. There is
> + no
>
> + inherent time interval between ticks but is a function of the CPU
> frequency.
>
> +
>
> + @param This - Protocol instance structure.
>
> + @param TimerIndex - Specifies which CPU timer is requested.
>
> + @param TimerValue - Pointer to the returned timer value.
>
> + @param TimerPeriod - A pointer to the amount of time that passes
>
> + in femtoseconds (10-15) for each
> + increment
>
> + of TimerValue. If TimerValue does not
>
> + increment at a predictable rate, then 0
> + is
>
> + returned. The amount of time that has
>
> + passed between two calls to
> + GetTimerValue()
>
> + can be calculated with the formula
>
> + (TimerValue2 - TimerValue1) * TimerPeriod.
>
> + This parameter is optional and may be NULL.
>
> +
>
> + @retval EFI_SUCCESS - If the CPU timer count was returned.
>
> + @retval EFI_UNSUPPORTED - If the CPU does not have any readable
> timers.
>
> + @retval EFI_DEVICE_ERROR - If an error occurred while reading the
> timer.
>
> + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue
> is NULL.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuGetTimerValue (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This,
>
> + IN UINT32 TimerIndex,
>
> + OUT UINT64 *TimerValue,
>
> + OUT UINT64 *TimerPeriod OPTIONAL
>
> + );
>
> +
>
> +/**
>
> + Set memory cacheability attributes for given range of memeory.
>
> +
>
> + @param This Protocol instance structure
>
> + @param BaseAddress Specifies the start address of the
>
> + memory range
>
> + @param Length Specifies the length of the memory range
>
> + @param Attributes The memory cacheability for the memory range
>
> +
>
> + @retval EFI_SUCCESS If the cacheability of that memory range is
>
> + set successfully
>
> + @retval EFI_UNSUPPORTED If the desired operation cannot be done
>
> + @retval EFI_INVALID_PARAMETER The input parameter is not correct,
>
> + such as Length = 0
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuSetMemoryAttributes (
>
> + IN EFI_CPU_ARCH_PROTOCOL *This,
>
> + IN EFI_PHYSICAL_ADDRESS BaseAddress,
>
> + IN UINT64 Length,
>
> + IN UINT64 Attributes
>
> + );
>
> +
>
> +#endif
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module
2022-09-07 9:32 ` Chang, Abner
@ 2022-09-07 11:22 ` Sunil V L
2022-09-07 12:46 ` Chang, Abner
0 siblings, 1 reply; 24+ messages in thread
From: Sunil V L @ 2022-09-07 11:22 UTC (permalink / raw)
To: Chang, Abner
Cc: devel@edk2.groups.io, Jian J Wang, Liming Gao, Eric Dong, Ray Ni,
Rahul Kumar, Debkumar De, Catharine West, Daniel Schaefer,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel
On Wed, Sep 07, 2022 at 09:32:12AM +0000, Chang, Abner wrote:
> [AMD Official Use Only - General]
>
> Hi Sunil and UefiCpuPkg maintainers,
> For CpuDxe case, I think we should abstract CpuDxe to accommodate all processor architectures instead of having copy for each archs. CpuDxeCommon.c can have the generic protocol structure and the installation functions, and CpuDxeCommon.h has the general definitions. So does CpuMp related files. Move processor architecture dependent files to under arch folders. AMD may have some differences with Intel so we will have CpuDxeAmd.inf under CpuDxe\. AMD is revising SmmFeatureCpuLib base on the similar concept. I think this makes the module looks simple and architectural. Furthermore, the similar concept should apply to all modules (if necessary) under UefiCpuPkg.
> I think we should revise CpuDxe before adding new arch such as RISC-V and Loongson64 to this module.
Thanks Abner!. I have sent V2 in the current form itself since I had to
move DSC to OvmfPkg instead of edk2-platforms.
I am not sure whether we really need this level of restructuring since I
didn't find much to share between architectures. Thats why,
I just made current sources as x86 speicifc and added RISC-V sources.
Anyway, let me wait for maintainers feedback. Do you have a patch
already for this restructuring? If so, I can rebase RISC-V changes on
top of it if maintainers accept the approach.
Thanks
Sunil
>
> Here is a BZ for UefiCpuPkg rearchitecture, https://bugzilla.tianocore.org/show_bug.cgi?id=3860
>
> Abner
>
> Something looks like below,
> CpuDxe\X86\Ia32\
> \IA32\CpuAsm.asm
> \IA32\PageAttribute.c
> \X86\X64\
> \X64\CpuAsm.asm
> \X64\PageAttribute.c
> \X86\CpuGdt.c
> \CpuGdt.h
> \CpuPageTable.C
> \CpuPageTableh.h
> \CpuDxe.c
> \RISCV\RISCV64\
> \RISCV64\CpuDxe.h
> \CpuDxe.c
> \ARM\ARM\
> \AARCH64\
> \CpuDxe.c
> \CpuDxeCommon.c
> \CpuMpCommon.c
> \CpuDxeCommon.h
> \CpuMpCommon.h
> \CpuDxe.inf
>
>
> > -----Original Message-----
> > From: Sunil V L <sunilvl@ventanamicro.com>
> > Sent: Wednesday, September 7, 2022 1:09 AM
> > To: devel@edk2.groups.io
> > Cc: Jian J Wang <jian.j.wang@intel.com>; Liming Gao
> > <gaoliming@byosoft.com.cn>; Eric Dong <eric.dong@intel.com>; Ray Ni
> > <ray.ni@intel.com>; Rahul Kumar <rahul1.kumar@intel.com>; Debkumar De
> > <debkumar.de@intel.com>; Catharine West <catharine.west@intel.com>;
> > Daniel Schaefer <git@danielschaefer.me>; Chang, Abner
> > <Abner.Chang@amd.com>; Leif Lindholm <quic_llindhol@quicinc.com>; Ard
> > Biesheuvel <ardb@kernel.org>; Heinrich Schuchardt
> > <heinrich.schuchardt@canonical.com>; Anup Patel
> > <apatel@ventanamicro.com>; Sunil V L <sunilvl@ventanamicro.com>
> > Subject: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in
> > CpuDxe module
> >
> > [CAUTION: External Email]
> >
> > This DXE module initializes the RISC-V CPU by installing the CPU specific ARCH
> > protocol handlers. This also initializes the RISCV_EFI_BOOT_PROTOCOL which
> > is required on RISC-V platforms.
> >
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > ---
> > UefiCpuPkg/CpuDxe/CpuDxe.inf | 16 +-
> > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 337
> > +++++++++++++++++++++++++++++
> > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 200 +++++++++++++++++
> > 3 files changed, 552 insertions(+), 1 deletion(-) create mode 100644
> > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> >
> > diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 4f2ea42f16..17cf2b1ecd 100644
> > --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > @@ -1,8 +1,12 @@
> > ## @file
> >
> > -# CPU driver installs CPU Architecture Protocol and CPU MP protocol.
> >
> > +# On X86, CPU driver installs CPU Architecture Protocol and CPU MP
> > protocol.
> >
> > +#
> >
> > +# On RISC-V, CPU driver installs CPU Architecture Protocol and RISC-V
> > +boot
> >
> > +# protocol
> >
> > #
> >
> > # Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>
> >
> > # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> >
> > +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > +reserved.<BR>
> >
> > #
> >
> > # SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > #
> >
> > @@ -44,6 +48,9 @@
> > MtrrLib
> >
> > UefiCpuLib
> >
> >
> >
> > +[LibraryClasses.RISCV64]
> >
> > + RiscVSbiLib
> >
> > +
> >
> > [Sources.IA32, Sources.X64]
> >
> > CpuDxe.c
> >
> > CpuDxe.h
> >
> > @@ -62,11 +69,18 @@
> > X64/CpuAsm.nasm
> >
> > X64/PagingAttribute.c
> >
> >
> >
> > +[Sources.RISCV64]
> >
> > + RiscV64/CpuDxe.c
> >
> > + RiscV64/CpuDxe.h
> >
> > +
> >
> > [Protocols]
> >
> > gEfiCpuArchProtocolGuid ## PRODUCES
> >
> > gEfiMpServiceProtocolGuid ## PRODUCES
> >
> > gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES
> >
> >
> >
> > +[Protocols.RISCV64]
> >
> > + gRiscVEfiBootProtocolGuid ## PRODUCES
> >
> > +
> >
> > [Guids]
> >
> > gIdleLoopEventGuid ## CONSUMES ## Event
> >
> > gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES ##
> > SystemTable
> >
> > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > new file mode 100644
> > index 0000000000..4112b6b8c6
> > --- /dev/null
> > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > @@ -0,0 +1,337 @@
> > +/** @file
> >
> > + RISC-V CPU DXE driver.
> >
> > +
> >
> > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP.
> > + All rights reserved.<BR>
> >
> > + Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > + reserved.<BR>
> >
> > +
> >
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > +
> >
> > +**/
> >
> > +
> >
> > +#include <Library/PcdLib.h>
> >
> > +#include <Register/RiscV64/RiscVAsm.h>
> >
> > +#include "CpuDxe.h"
> >
> > +
> >
> > +//
> >
> > +// Global Variables
> >
> > +//
> >
> > +STATIC BOOLEAN mInterruptState = FALSE;
> >
> > +STATIC EFI_HANDLE mCpuHandle = NULL;
> >
> > +STATIC UINTN mBootHartId;
> >
> > +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol;
> >
> > +
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +RiscvGetBootHartId (
> >
> > + IN RISCV_EFI_BOOT_PROTOCOL *This,
> >
> > + OUT UINTN *BootHartId
> >
> > + )
> >
> > +{
> >
> > + if((This != &gRiscvBootProtocol) || (BootHartId == NULL)) {
> >
> > + return EFI_INVALID_PARAMETER;
> >
> > + }
> >
> > +
> >
> > + *BootHartId = mBootHartId;
> >
> > + return EFI_SUCCESS;
> >
> > +}
> >
> > +
> >
> > +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol = {
> >
> > + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION,
> >
> > + RiscvGetBootHartId
> >
> > +};
> >
> > +
> >
> > +EFI_CPU_ARCH_PROTOCOL gCpu = {
> >
> > + CpuFlushCpuDataCache,
> >
> > + CpuEnableInterrupt,
> >
> > + CpuDisableInterrupt,
> >
> > + CpuGetInterruptState,
> >
> > + CpuInit,
> >
> > + CpuRegisterInterruptHandler,
> >
> > + CpuGetTimerValue,
> >
> > + CpuSetMemoryAttributes,
> >
> > + 1, // NumberOfTimers
> >
> > + 4 // DmaBufferAlignment
> >
> > +};
> >
> > +
> >
> > +//
> >
> > +// CPU Arch Protocol Functions
> >
> > +//
> >
> > +
> >
> > +/**
> >
> > + Flush CPU data cache. If the instruction cache is fully coherent
> >
> > + with all DMA operations then function can just return EFI_SUCCESS.
> >
> > +
> >
> > + @param This Protocol instance structure
> >
> > + @param Start Physical address to start flushing from.
> >
> > + @param Length Number of bytes to flush. Round up to chipset
> >
> > + granularity.
> >
> > + @param FlushType Specifies the type of flush operation to perform.
> >
> > +
> >
> > + @retval EFI_SUCCESS If cache was flushed
> >
> > + @retval EFI_UNSUPPORTED If flush type is not supported.
> >
> > + @retval EFI_DEVICE_ERROR If requested range could not be flushed.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuFlushCpuDataCache (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This,
> >
> > + IN EFI_PHYSICAL_ADDRESS Start,
> >
> > + IN UINT64 Length,
> >
> > + IN EFI_CPU_FLUSH_TYPE FlushType
> >
> > + )
> >
> > +{
> >
> > + return EFI_SUCCESS;
> >
> > +}
> >
> > +
> >
> > +/**
> >
> > + Enables CPU interrupts.
> >
> > +
> >
> > + @param This Protocol instance structure
> >
> > +
> >
> > + @retval EFI_SUCCESS If interrupts were enabled in the CPU
> >
> > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuEnableInterrupt (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This
> >
> > + )
> >
> > +{
> >
> > + EnableInterrupts ();
> >
> > + mInterruptState = TRUE;
> >
> > + return EFI_SUCCESS;
> >
> > +}
> >
> > +
> >
> > +/**
> >
> > + Disables CPU interrupts.
> >
> > +
> >
> > + @param This Protocol instance structure
> >
> > +
> >
> > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> >
> > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuDisableInterrupt (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This
> >
> > + )
> >
> > +{
> >
> > + DisableInterrupts ();
> >
> > + mInterruptState = FALSE;
> >
> > + return EFI_SUCCESS;
> >
> > +}
> >
> > +
> >
> > +/**
> >
> > + Return the state of interrupts.
> >
> > +
> >
> > + @param This Protocol instance structure
> >
> > + @param State Pointer to the CPU's current interrupt state
> >
> > +
> >
> > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> >
> > + @retval EFI_INVALID_PARAMETER State is NULL.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuGetInterruptState (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This,
> >
> > + OUT BOOLEAN *State
> >
> > + )
> >
> > +{
> >
> > + if (State == NULL) {
> >
> > + return EFI_INVALID_PARAMETER;
> >
> > + }
> >
> > +
> >
> > + *State = mInterruptState;
> >
> > + return EFI_SUCCESS;
> >
> > +}
> >
> > +
> >
> > +/**
> >
> > + Generates an INIT to the CPU.
> >
> > +
> >
> > + @param This Protocol instance structure
> >
> > + @param InitType Type of CPU INIT to perform
> >
> > +
> >
> > + @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
> >
> > + seen.
> >
> > + @retval EFI_DEVICE_ERROR If CPU INIT failed.
> >
> > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuInit (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This,
> >
> > + IN EFI_CPU_INIT_TYPE InitType
> >
> > + )
> >
> > +{
> >
> > + return EFI_UNSUPPORTED;
> >
> > +}
> >
> > +
> >
> > +/**
> >
> > + Registers a function to be called from the CPU interrupt handler.
> >
> > +
> >
> > + @param This Protocol instance structure
> >
> > + @param InterruptType Defines which interrupt to hook. IA-32
> >
> > + valid range is 0x00 through 0xFF
> >
> > + @param InterruptHandler A pointer to a function of type
> >
> > + EFI_CPU_INTERRUPT_HANDLER that is
> > + called
> >
> > + when a processor interrupt occurs. A
> > + null
> >
> > + pointer is an error condition.
> >
> > +
> >
> > + @retval EFI_SUCCESS If handler installed or uninstalled.
> >
> > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a
> > handler
> >
> > + for InterruptType was previously installed.
> >
> > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a
> > + handler for
> >
> > + InterruptType was not previously installed.
> >
> > + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
> >
> > + is not supported.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuRegisterInterruptHandler (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This,
> >
> > + IN EFI_EXCEPTION_TYPE InterruptType,
> >
> > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
> >
> > + )
> >
> > +{
> >
> > + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
> >
> > +}
> >
> > +
> >
> > +/**
> >
> > + Returns a timer value from one of the CPU's internal timers. There is
> > + no
> >
> > + inherent time interval between ticks but is a function of the CPU
> > frequency.
> >
> > +
> >
> > + @param This - Protocol instance structure.
> >
> > + @param TimerIndex - Specifies which CPU timer is requested.
> >
> > + @param TimerValue - Pointer to the returned timer value.
> >
> > + @param TimerPeriod - A pointer to the amount of time that passes
> >
> > + in femtoseconds (10-15) for each
> > + increment
> >
> > + of TimerValue. If TimerValue does not
> >
> > + increment at a predictable rate, then 0
> > + is
> >
> > + returned. The amount of time that has
> >
> > + passed between two calls to
> > + GetTimerValue()
> >
> > + can be calculated with the formula
> >
> > + (TimerValue2 - TimerValue1) * TimerPeriod.
> >
> > + This parameter is optional and may be NULL.
> >
> > +
> >
> > + @retval EFI_SUCCESS - If the CPU timer count was returned.
> >
> > + @retval EFI_UNSUPPORTED - If the CPU does not have any readable
> > timers.
> >
> > + @retval EFI_DEVICE_ERROR - If an error occurred while reading the
> > timer.
> >
> > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue
> > is NULL.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuGetTimerValue (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This,
> >
> > + IN UINT32 TimerIndex,
> >
> > + OUT UINT64 *TimerValue,
> >
> > + OUT UINT64 *TimerPeriod OPTIONAL
> >
> > + )
> >
> > +{
> >
> > + return EFI_UNSUPPORTED;
> >
> > +}
> >
> > +
> >
> > +/**
> >
> > + Implementation of SetMemoryAttributes() service of CPU Architecture
> > Protocol.
> >
> > +
> >
> > + This function modifies the attributes for the memory region specified
> > + by BaseAddress and
> >
> > + Length from their current attributes to the attributes specified by
> > Attributes.
> >
> > +
> >
> > + @param This The EFI_CPU_ARCH_PROTOCOL instance.
> >
> > + @param BaseAddress The physical address that is the start address of a
> > memory region.
> >
> > + @param Length The size in bytes of the memory region.
> >
> > + @param Attributes The bit mask of attributes to set for the memory
> > region.
> >
> > +
> >
> > + @retval EFI_SUCCESS The attributes were set for the memory region.
> >
> > + @retval EFI_ACCESS_DENIED The attributes for the memory resource
> > range specified by
> >
> > + BaseAddress and Length cannot be modified.
> >
> > + @retval EFI_INVALID_PARAMETER Length is zero.
> >
> > + Attributes specified an illegal
> > + combination of attributes that
> >
> > + cannot be set together.
> >
> > + @retval EFI_OUT_OF_RESOURCES There are not enough system
> > resources
> > + to modify the attributes of
> >
> > + the memory resource range.
> >
> > + @retval EFI_UNSUPPORTED The processor does not support one or
> > more bytes of the memory
> >
> > + resource range specified by BaseAddress and Length.
> >
> > + The bit mask of attributes is not
> > + support for the memory resource
> >
> > + range specified by BaseAddress and Length.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuSetMemoryAttributes (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This,
> >
> > + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> >
> > + IN UINT64 Length,
> >
> > + IN UINT64 Attributes
> >
> > + )
> >
> > +{
> >
> > + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n",
> > + __FUNCTION__));
> >
> > + return EFI_SUCCESS;
> >
> > +}
> >
> > +
> >
> > +/**
> >
> > + Initialize the state information for the CPU Architectural Protocol.
> >
> > +
> >
> > + @param ImageHandle Image handle this driver.
> >
> > + @param SystemTable Pointer to the System Table.
> >
> > +
> >
> > + @retval EFI_SUCCESS Thread can be successfully created
> >
> > + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
> >
> > + @retval EFI_DEVICE_ERROR Cannot create the thread
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +InitializeCpu (
> >
> > + IN EFI_HANDLE ImageHandle,
> >
> > + IN EFI_SYSTEM_TABLE *SystemTable
> >
> > + )
> >
> > +{
> >
> > + EFI_STATUS Status;
> >
> > + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
> >
> > +
> >
> > + GetFirmwareContextPointer (&FirmwareContext);
> >
> > + ASSERT (FirmwareContext != NULL);
> >
> > + if (FirmwareContext == NULL) {
> >
> > + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of
> > + EFI_RISCV_FIRMWARE_CONTEXT\n"));
> >
> > + return EFI_NOT_FOUND;
> >
> > + }
> >
> > + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n",
> > + __FUNCTION__, FirmwareContext));
> >
> > +
> >
> > + mBootHartId = FirmwareContext->BootHartId;
> >
> > + DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n", __FUNCTION__,
> > + mBootHartId));
> >
> > +
> >
> > +
> >
> > + InitializeCpuExceptionHandlers(NULL);
> >
> > +
> >
> > + //
> >
> > + // Make sure interrupts are disabled
> >
> > + //
> >
> > + DisableInterrupts ();
> >
> > +
> >
> > + Status = gBS->InstallProtocolInterface (&ImageHandle,
> >
> > + &gRiscVEfiBootProtocolGuid,
> >
> > + EFI_NATIVE_INTERFACE,
> >
> > + &gRiscvBootProtocol
> >
> > + );
> >
> > +
> >
> > + ASSERT_EFI_ERROR (Status);
> >
> > +
> >
> > + //
> >
> > + // Install CPU Architectural Protocol
> >
> > + //
> >
> > + Status = gBS->InstallMultipleProtocolInterfaces (
> >
> > + &mCpuHandle,
> >
> > + &gEfiCpuArchProtocolGuid,
> >
> > + &gCpu,
> >
> > + NULL
> >
> > + );
> >
> > + ASSERT_EFI_ERROR (Status);
> >
> > + return Status;
> >
> > +}
> >
> > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > new file mode 100644
> > index 0000000000..f039759dbd
> > --- /dev/null
> > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > @@ -0,0 +1,200 @@
> > +/** @file
> >
> > + RISC-V CPU DXE module header file.
> >
> > +
> >
> > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP.
> > + All rights reserved.<BR>
> >
> > + Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > + reserved.<BR>
> >
> > +
> >
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > +
> >
> > +**/
> >
> > +
> >
> > +#ifndef CPU_DXE_H_
> >
> > +#define CPU_DXE_H_
> >
> > +
> >
> > +#include <PiDxe.h>
> >
> > +
> >
> > +#include <Protocol/Cpu.h>
> >
> > +#include <Protocol/RiscVBootProtocol.h>
> >
> > +#include <Library/RiscVSbiLib.h>
> >
> > +#include <Library/BaseLib.h>
> >
> > +#include <Library/CpuExceptionHandlerLib.h>
> >
> > +#include <Library/DebugLib.h>
> >
> > +#include <Library/UefiBootServicesTableLib.h>
> >
> > +#include <Library/UefiDriverEntryPoint.h>
> >
> > +
> >
> > +/**
> >
> > + Flush CPU data cache. If the instruction cache is fully coherent
> >
> > + with all DMA operations then function can just return EFI_SUCCESS.
> >
> > +
> >
> > + @param This Protocol instance structure
> >
> > + @param Start Physical address to start flushing from.
> >
> > + @param Length Number of bytes to flush. Round up to chipset
> >
> > + granularity.
> >
> > + @param FlushType Specifies the type of flush operation to perform.
> >
> > +
> >
> > + @retval EFI_SUCCESS If cache was flushed
> >
> > + @retval EFI_UNSUPPORTED If flush type is not supported.
> >
> > + @retval EFI_DEVICE_ERROR If requested range could not be flushed.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuFlushCpuDataCache (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This,
> >
> > + IN EFI_PHYSICAL_ADDRESS Start,
> >
> > + IN UINT64 Length,
> >
> > + IN EFI_CPU_FLUSH_TYPE FlushType
> >
> > + );
> >
> > +
> >
> > +/**
> >
> > + Enables CPU interrupts.
> >
> > +
> >
> > + @param This Protocol instance structure
> >
> > +
> >
> > + @retval EFI_SUCCESS If interrupts were enabled in the CPU
> >
> > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuEnableInterrupt (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This
> >
> > + );
> >
> > +
> >
> > +/**
> >
> > + Disables CPU interrupts.
> >
> > +
> >
> > + @param This Protocol instance structure
> >
> > +
> >
> > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> >
> > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuDisableInterrupt (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This
> >
> > + );
> >
> > +
> >
> > +/**
> >
> > + Return the state of interrupts.
> >
> > +
> >
> > + @param This Protocol instance structure
> >
> > + @param State Pointer to the CPU's current interrupt state
> >
> > +
> >
> > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> >
> > + @retval EFI_INVALID_PARAMETER State is NULL.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuGetInterruptState (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This,
> >
> > + OUT BOOLEAN *State
> >
> > + );
> >
> > +
> >
> > +/**
> >
> > + Generates an INIT to the CPU.
> >
> > +
> >
> > + @param This Protocol instance structure
> >
> > + @param InitType Type of CPU INIT to perform
> >
> > +
> >
> > + @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
> >
> > + seen.
> >
> > + @retval EFI_DEVICE_ERROR If CPU INIT failed.
> >
> > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuInit (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This,
> >
> > + IN EFI_CPU_INIT_TYPE InitType
> >
> > + );
> >
> > +
> >
> > +/**
> >
> > + Registers a function to be called from the CPU interrupt handler.
> >
> > +
> >
> > + @param This Protocol instance structure
> >
> > + @param InterruptType Defines which interrupt to hook. IA-32
> >
> > + valid range is 0x00 through 0xFF
> >
> > + @param InterruptHandler A pointer to a function of type
> >
> > + EFI_CPU_INTERRUPT_HANDLER that is
> > + called
> >
> > + when a processor interrupt occurs. A
> > + null
> >
> > + pointer is an error condition.
> >
> > +
> >
> > + @retval EFI_SUCCESS If handler installed or uninstalled.
> >
> > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a
> > handler
> >
> > + for InterruptType was previously installed.
> >
> > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a
> > + handler for
> >
> > + InterruptType was not previously installed.
> >
> > + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
> >
> > + is not supported.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuRegisterInterruptHandler (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This,
> >
> > + IN EFI_EXCEPTION_TYPE InterruptType,
> >
> > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
> >
> > + );
> >
> > +
> >
> > +/**
> >
> > + Returns a timer value from one of the CPU's internal timers. There is
> > + no
> >
> > + inherent time interval between ticks but is a function of the CPU
> > frequency.
> >
> > +
> >
> > + @param This - Protocol instance structure.
> >
> > + @param TimerIndex - Specifies which CPU timer is requested.
> >
> > + @param TimerValue - Pointer to the returned timer value.
> >
> > + @param TimerPeriod - A pointer to the amount of time that passes
> >
> > + in femtoseconds (10-15) for each
> > + increment
> >
> > + of TimerValue. If TimerValue does not
> >
> > + increment at a predictable rate, then 0
> > + is
> >
> > + returned. The amount of time that has
> >
> > + passed between two calls to
> > + GetTimerValue()
> >
> > + can be calculated with the formula
> >
> > + (TimerValue2 - TimerValue1) * TimerPeriod.
> >
> > + This parameter is optional and may be NULL.
> >
> > +
> >
> > + @retval EFI_SUCCESS - If the CPU timer count was returned.
> >
> > + @retval EFI_UNSUPPORTED - If the CPU does not have any readable
> > timers.
> >
> > + @retval EFI_DEVICE_ERROR - If an error occurred while reading the
> > timer.
> >
> > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue
> > is NULL.
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuGetTimerValue (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This,
> >
> > + IN UINT32 TimerIndex,
> >
> > + OUT UINT64 *TimerValue,
> >
> > + OUT UINT64 *TimerPeriod OPTIONAL
> >
> > + );
> >
> > +
> >
> > +/**
> >
> > + Set memory cacheability attributes for given range of memeory.
> >
> > +
> >
> > + @param This Protocol instance structure
> >
> > + @param BaseAddress Specifies the start address of the
> >
> > + memory range
> >
> > + @param Length Specifies the length of the memory range
> >
> > + @param Attributes The memory cacheability for the memory range
> >
> > +
> >
> > + @retval EFI_SUCCESS If the cacheability of that memory range is
> >
> > + set successfully
> >
> > + @retval EFI_UNSUPPORTED If the desired operation cannot be done
> >
> > + @retval EFI_INVALID_PARAMETER The input parameter is not correct,
> >
> > + such as Length = 0
> >
> > +
> >
> > +**/
> >
> > +EFI_STATUS
> >
> > +EFIAPI
> >
> > +CpuSetMemoryAttributes (
> >
> > + IN EFI_CPU_ARCH_PROTOCOL *This,
> >
> > + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> >
> > + IN UINT64 Length,
> >
> > + IN UINT64 Attributes
> >
> > + );
> >
> > +
> >
> > +#endif
> >
> > --
> > 2.25.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module
2022-09-07 11:22 ` Sunil V L
@ 2022-09-07 12:46 ` Chang, Abner
2022-09-08 10:53 ` Sunil V L
0 siblings, 1 reply; 24+ messages in thread
From: Chang, Abner @ 2022-09-07 12:46 UTC (permalink / raw)
To: Sunil V L
Cc: devel@edk2.groups.io, Jian J Wang, Liming Gao, Eric Dong, Ray Ni,
Rahul Kumar, Debkumar De, Catharine West, Daniel Schaefer,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel
[AMD Official Use Only - General]
> -----Original Message-----
> From: Sunil V L <sunilvl@ventanamicro.com>
> Sent: Wednesday, September 7, 2022 7:22 PM
> To: Chang, Abner <Abner.Chang@amd.com>
> Cc: devel@edk2.groups.io; Jian J Wang <jian.j.wang@intel.com>; Liming Gao
> <gaoliming@byosoft.com.cn>; Eric Dong <eric.dong@intel.com>; Ray Ni
> <ray.ni@intel.com>; Rahul Kumar <rahul1.kumar@intel.com>; Debkumar De
> <debkumar.de@intel.com>; Catharine West <catharine.west@intel.com>;
> Daniel Schaefer <git@danielschaefer.me>; Leif Lindholm
> <quic_llindhol@quicinc.com>; Ard Biesheuvel <ardb@kernel.org>; Heinrich
> Schuchardt <heinrich.schuchardt@canonical.com>; Anup Patel
> <apatel@ventanamicro.com>
> Subject: Re: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in
> CpuDxe module
>
> [CAUTION: External Email]
>
> On Wed, Sep 07, 2022 at 09:32:12AM +0000, Chang, Abner wrote:
> > [AMD Official Use Only - General]
> >
> > Hi Sunil and UefiCpuPkg maintainers,
> > For CpuDxe case, I think we should abstract CpuDxe to accommodate all
> processor architectures instead of having copy for each archs.
> CpuDxeCommon.c can have the generic protocol structure and the
> installation functions, and CpuDxeCommon.h has the general definitions. So
> does CpuMp related files. Move processor architecture dependent files to
> under arch folders. AMD may have some differences with Intel so we will
> have CpuDxeAmd.inf under CpuDxe\. AMD is revising SmmFeatureCpuLib
> base on the similar concept. I think this makes the module looks simple and
> architectural. Furthermore, the similar concept should apply to all modules (if
> necessary) under UefiCpuPkg.
> > I think we should revise CpuDxe before adding new arch such as RISC-V
> and Loongson64 to this module.
> Thanks Abner!. I have sent V2 in the current form itself since I had to move
> DSC to OvmfPkg instead of edk2-platforms.
>
> I am not sure whether we really need this level of restructuring since I didn't
> find much to share between architectures. Thats why, I just made current
> sources as x86 speicifc and added RISC-V sources.
> Anyway, let me wait for maintainers feedback.
I was also struggled with UefiCpuPkg when I tried to move RISC-V stuff over here. Some modules are easy to be abstracted but some are not. Some as you mentioned have not much to share among processor archs. For these cases we can use folder or a separate module for the abstraction. Having X86 source code on the module root and other processor archs in the folder look weird though.
>Do you have a patch already
> for this restructuring? If so, I can rebase RISC-V changes on top of it if
> maintainers accept the approach.
No, I don't have that yet. But I am willing to help on restructuring this module and others if maintainers agree with this.
Thanks
Abner
>
> Thanks
> Sunil
> >
> > Here is a BZ for UefiCpuPkg rearchitecture,
> >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> >
> illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D3860&data=05%7C01%7CA
> bner
> > .Chang%40amd.com%7Cc9bca42bd85c489c38ff08da90c33618%7C3dd8961fe
> 4884e60
> >
> 8e11a82d994e183d%7C0%7C0%7C637981465382450232%7CUnknown%7CTW
> FpbGZsb3d8
> >
> eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> D%7C3
> >
> 000%7C%7C%7C&sdata=iDjOPZCMAH6BSBhR2kx567ibVHza2ZfhjzLHC77
> cfI8%3D&
> > amp;reserved=0
> >
> > Abner
> >
> > Something looks like below,
> > CpuDxe\X86\Ia32\
> > \IA32\CpuAsm.asm
> > \IA32\PageAttribute.c
> > \X86\X64\
> > \X64\CpuAsm.asm
> > \X64\PageAttribute.c
> > \X86\CpuGdt.c
> > \CpuGdt.h
> > \CpuPageTable.C
> > \CpuPageTableh.h
> > \CpuDxe.c
> > \RISCV\RISCV64\
> > \RISCV64\CpuDxe.h
> > \CpuDxe.c
> > \ARM\ARM\
> > \AARCH64\
> > \CpuDxe.c
> > \CpuDxeCommon.c
> > \CpuMpCommon.c
> > \CpuDxeCommon.h
> > \CpuMpCommon.h
> > \CpuDxe.inf
> >
> >
> > > -----Original Message-----
> > > From: Sunil V L <sunilvl@ventanamicro.com>
> > > Sent: Wednesday, September 7, 2022 1:09 AM
> > > To: devel@edk2.groups.io
> > > Cc: Jian J Wang <jian.j.wang@intel.com>; Liming Gao
> > > <gaoliming@byosoft.com.cn>; Eric Dong <eric.dong@intel.com>; Ray Ni
> > > <ray.ni@intel.com>; Rahul Kumar <rahul1.kumar@intel.com>; Debkumar
> > > De <debkumar.de@intel.com>; Catharine West
> > > <catharine.west@intel.com>; Daniel Schaefer <git@danielschaefer.me>;
> > > Chang, Abner <Abner.Chang@amd.com>; Leif Lindholm
> > > <quic_llindhol@quicinc.com>; Ard Biesheuvel <ardb@kernel.org>;
> > > Heinrich Schuchardt <heinrich.schuchardt@canonical.com>; Anup Patel
> > > <apatel@ventanamicro.com>; Sunil V L <sunilvl@ventanamicro.com>
> > > Subject: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in
> > > CpuDxe module
> > >
> > > [CAUTION: External Email]
> > >
> > > This DXE module initializes the RISC-V CPU by installing the CPU
> > > specific ARCH protocol handlers. This also initializes the
> > > RISCV_EFI_BOOT_PROTOCOL which is required on RISC-V platforms.
> > >
> > > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > > ---
> > > UefiCpuPkg/CpuDxe/CpuDxe.inf | 16 +-
> > > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 337
> > > +++++++++++++++++++++++++++++
> > > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 200 +++++++++++++++++
> > > 3 files changed, 552 insertions(+), 1 deletion(-) create mode
> > > 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > >
> > > diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 4f2ea42f16..17cf2b1ecd 100644
> > > --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > @@ -1,8 +1,12 @@
> > > ## @file
> > >
> > > -# CPU driver installs CPU Architecture Protocol and CPU MP protocol.
> > >
> > > +# On X86, CPU driver installs CPU Architecture Protocol and CPU MP
> > > protocol.
> > >
> > > +#
> > >
> > > +# On RISC-V, CPU driver installs CPU Architecture Protocol and
> > > +RISC-V boot
> > >
> > > +# protocol
> > >
> > > #
> > >
> > > # Copyright (c) 2008 - 2019, Intel Corporation. All rights
> > > reserved.<BR>
> > >
> > > # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> > >
> > > +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > > +reserved.<BR>
> > >
> > > #
> > >
> > > # SPDX-License-Identifier: BSD-2-Clause-Patent
> > >
> > > #
> > >
> > > @@ -44,6 +48,9 @@
> > > MtrrLib
> > >
> > > UefiCpuLib
> > >
> > >
> > >
> > > +[LibraryClasses.RISCV64]
> > >
> > > + RiscVSbiLib
> > >
> > > +
> > >
> > > [Sources.IA32, Sources.X64]
> > >
> > > CpuDxe.c
> > >
> > > CpuDxe.h
> > >
> > > @@ -62,11 +69,18 @@
> > > X64/CpuAsm.nasm
> > >
> > > X64/PagingAttribute.c
> > >
> > >
> > >
> > > +[Sources.RISCV64]
> > >
> > > + RiscV64/CpuDxe.c
> > >
> > > + RiscV64/CpuDxe.h
> > >
> > > +
> > >
> > > [Protocols]
> > >
> > > gEfiCpuArchProtocolGuid ## PRODUCES
> > >
> > > gEfiMpServiceProtocolGuid ## PRODUCES
> > >
> > > gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES
> > >
> > >
> > >
> > > +[Protocols.RISCV64]
> > >
> > > + gRiscVEfiBootProtocolGuid ## PRODUCES
> > >
> > > +
> > >
> > > [Guids]
> > >
> > > gIdleLoopEventGuid ## CONSUMES ## Event
> > >
> > > gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES ##
> > > SystemTable
> > >
> > > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > new file mode 100644
> > > index 0000000000..4112b6b8c6
> > > --- /dev/null
> > > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > @@ -0,0 +1,337 @@
> > > +/** @file
> > >
> > > + RISC-V CPU DXE driver.
> > >
> > > +
> > >
> > > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP.
> > > + All rights reserved.<BR>
> > >
> > > + Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > > + reserved.<BR>
> > >
> > > +
> > >
> > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > >
> > > +
> > >
> > > +**/
> > >
> > > +
> > >
> > > +#include <Library/PcdLib.h>
> > >
> > > +#include <Register/RiscV64/RiscVAsm.h>
> > >
> > > +#include "CpuDxe.h"
> > >
> > > +
> > >
> > > +//
> > >
> > > +// Global Variables
> > >
> > > +//
> > >
> > > +STATIC BOOLEAN mInterruptState = FALSE;
> > >
> > > +STATIC EFI_HANDLE mCpuHandle = NULL;
> > >
> > > +STATIC UINTN mBootHartId;
> > >
> > > +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol;
> > >
> > > +
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +RiscvGetBootHartId (
> > >
> > > + IN RISCV_EFI_BOOT_PROTOCOL *This,
> > >
> > > + OUT UINTN *BootHartId
> > >
> > > + )
> > >
> > > +{
> > >
> > > + if((This != &gRiscvBootProtocol) || (BootHartId == NULL)) {
> > >
> > > + return EFI_INVALID_PARAMETER;
> > >
> > > + }
> > >
> > > +
> > >
> > > + *BootHartId = mBootHartId;
> > >
> > > + return EFI_SUCCESS;
> > >
> > > +}
> > >
> > > +
> > >
> > > +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol = {
> > >
> > > + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION,
> > >
> > > + RiscvGetBootHartId
> > >
> > > +};
> > >
> > > +
> > >
> > > +EFI_CPU_ARCH_PROTOCOL gCpu = {
> > >
> > > + CpuFlushCpuDataCache,
> > >
> > > + CpuEnableInterrupt,
> > >
> > > + CpuDisableInterrupt,
> > >
> > > + CpuGetInterruptState,
> > >
> > > + CpuInit,
> > >
> > > + CpuRegisterInterruptHandler,
> > >
> > > + CpuGetTimerValue,
> > >
> > > + CpuSetMemoryAttributes,
> > >
> > > + 1, // NumberOfTimers
> > >
> > > + 4 // DmaBufferAlignment
> > >
> > > +};
> > >
> > > +
> > >
> > > +//
> > >
> > > +// CPU Arch Protocol Functions
> > >
> > > +//
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Flush CPU data cache. If the instruction cache is fully coherent
> > >
> > > + with all DMA operations then function can just return EFI_SUCCESS.
> > >
> > > +
> > >
> > > + @param This Protocol instance structure
> > >
> > > + @param Start Physical address to start flushing from.
> > >
> > > + @param Length Number of bytes to flush. Round up to chipset
> > >
> > > + granularity.
> > >
> > > + @param FlushType Specifies the type of flush operation to
> perform.
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS If cache was flushed
> > >
> > > + @retval EFI_UNSUPPORTED If flush type is not supported.
> > >
> > > + @retval EFI_DEVICE_ERROR If requested range could not be flushed.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuFlushCpuDataCache (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > >
> > > + IN EFI_PHYSICAL_ADDRESS Start,
> > >
> > > + IN UINT64 Length,
> > >
> > > + IN EFI_CPU_FLUSH_TYPE FlushType
> > >
> > > + )
> > >
> > > +{
> > >
> > > + return EFI_SUCCESS;
> > >
> > > +}
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Enables CPU interrupts.
> > >
> > > +
> > >
> > > + @param This Protocol instance structure
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS If interrupts were enabled in the CPU
> > >
> > > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the
> CPU.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuEnableInterrupt (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > >
> > > + )
> > >
> > > +{
> > >
> > > + EnableInterrupts ();
> > >
> > > + mInterruptState = TRUE;
> > >
> > > + return EFI_SUCCESS;
> > >
> > > +}
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Disables CPU interrupts.
> > >
> > > +
> > >
> > > + @param This Protocol instance structure
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > >
> > > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the
> CPU.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuDisableInterrupt (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > >
> > > + )
> > >
> > > +{
> > >
> > > + DisableInterrupts ();
> > >
> > > + mInterruptState = FALSE;
> > >
> > > + return EFI_SUCCESS;
> > >
> > > +}
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Return the state of interrupts.
> > >
> > > +
> > >
> > > + @param This Protocol instance structure
> > >
> > > + @param State Pointer to the CPU's current interrupt state
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > >
> > > + @retval EFI_INVALID_PARAMETER State is NULL.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuGetInterruptState (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > >
> > > + OUT BOOLEAN *State
> > >
> > > + )
> > >
> > > +{
> > >
> > > + if (State == NULL) {
> > >
> > > + return EFI_INVALID_PARAMETER;
> > >
> > > + }
> > >
> > > +
> > >
> > > + *State = mInterruptState;
> > >
> > > + return EFI_SUCCESS;
> > >
> > > +}
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Generates an INIT to the CPU.
> > >
> > > +
> > >
> > > + @param This Protocol instance structure
> > >
> > > + @param InitType Type of CPU INIT to perform
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS If CPU INIT occurred. This value should never
> be
> > >
> > > + seen.
> > >
> > > + @retval EFI_DEVICE_ERROR If CPU INIT failed.
> > >
> > > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not
> supported.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuInit (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > >
> > > + IN EFI_CPU_INIT_TYPE InitType
> > >
> > > + )
> > >
> > > +{
> > >
> > > + return EFI_UNSUPPORTED;
> > >
> > > +}
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Registers a function to be called from the CPU interrupt handler.
> > >
> > > +
> > >
> > > + @param This Protocol instance structure
> > >
> > > + @param InterruptType Defines which interrupt to hook. IA-32
> > >
> > > + valid range is 0x00 through 0xFF
> > >
> > > + @param InterruptHandler A pointer to a function of type
> > >
> > > + EFI_CPU_INTERRUPT_HANDLER that is
> > > + called
> > >
> > > + when a processor interrupt occurs.
> > > + A null
> > >
> > > + pointer is an error condition.
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS If handler installed or uninstalled.
> > >
> > > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a
> > > handler
> > >
> > > + for InterruptType was previously installed.
> > >
> > > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a
> > > + handler for
> > >
> > > + InterruptType was not previously installed.
> > >
> > > + @retval EFI_UNSUPPORTED The interrupt specified by
> InterruptType
> > >
> > > + is not supported.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuRegisterInterruptHandler (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > >
> > > + IN EFI_EXCEPTION_TYPE InterruptType,
> > >
> > > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
> > >
> > > + )
> > >
> > > +{
> > >
> > > + return RegisterCpuInterruptHandler (InterruptType,
> > > + InterruptHandler);
> > >
> > > +}
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Returns a timer value from one of the CPU's internal timers.
> > > + There is no
> > >
> > > + inherent time interval between ticks but is a function of the CPU
> > > frequency.
> > >
> > > +
> > >
> > > + @param This - Protocol instance structure.
> > >
> > > + @param TimerIndex - Specifies which CPU timer is requested.
> > >
> > > + @param TimerValue - Pointer to the returned timer value.
> > >
> > > + @param TimerPeriod - A pointer to the amount of time that
> passes
> > >
> > > + in femtoseconds (10-15) for each
> > > + increment
> > >
> > > + of TimerValue. If TimerValue does
> > > + not
> > >
> > > + increment at a predictable rate,
> > > + then 0 is
> > >
> > > + returned. The amount of time that
> > > + has
> > >
> > > + passed between two calls to
> > > + GetTimerValue()
> > >
> > > + can be calculated with the formula
> > >
> > > + (TimerValue2 - TimerValue1) * TimerPeriod.
> > >
> > > + This parameter is optional and may be NULL.
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS - If the CPU timer count was returned.
> > >
> > > + @retval EFI_UNSUPPORTED - If the CPU does not have any readable
> > > timers.
> > >
> > > + @retval EFI_DEVICE_ERROR - If an error occurred while reading the
> > > timer.
> > >
> > > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or
> > > + TimerValue
> > > is NULL.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuGetTimerValue (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > >
> > > + IN UINT32 TimerIndex,
> > >
> > > + OUT UINT64 *TimerValue,
> > >
> > > + OUT UINT64 *TimerPeriod OPTIONAL
> > >
> > > + )
> > >
> > > +{
> > >
> > > + return EFI_UNSUPPORTED;
> > >
> > > +}
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Implementation of SetMemoryAttributes() service of CPU
> > > + Architecture
> > > Protocol.
> > >
> > > +
> > >
> > > + This function modifies the attributes for the memory region
> > > + specified by BaseAddress and
> > >
> > > + Length from their current attributes to the attributes specified
> > > + by
> > > Attributes.
> > >
> > > +
> > >
> > > + @param This The EFI_CPU_ARCH_PROTOCOL instance.
> > >
> > > + @param BaseAddress The physical address that is the start address
> of a
> > > memory region.
> > >
> > > + @param Length The size in bytes of the memory region.
> > >
> > > + @param Attributes The bit mask of attributes to set for the
> memory
> > > region.
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS The attributes were set for the memory
> region.
> > >
> > > + @retval EFI_ACCESS_DENIED The attributes for the memory
> resource
> > > range specified by
> > >
> > > + BaseAddress and Length cannot be modified.
> > >
> > > + @retval EFI_INVALID_PARAMETER Length is zero.
> > >
> > > + Attributes specified an illegal
> > > + combination of attributes that
> > >
> > > + cannot be set together.
> > >
> > > + @retval EFI_OUT_OF_RESOURCES There are not enough system
> > > resources
> > > + to modify the attributes of
> > >
> > > + the memory resource range.
> > >
> > > + @retval EFI_UNSUPPORTED The processor does not support one or
> > > more bytes of the memory
> > >
> > > + resource range specified by BaseAddress and Length.
> > >
> > > + The bit mask of attributes is not
> > > + support for the memory resource
> > >
> > > + range specified by BaseAddress and Length.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuSetMemoryAttributes (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > >
> > > + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> > >
> > > + IN UINT64 Length,
> > >
> > > + IN UINT64 Attributes
> > >
> > > + )
> > >
> > > +{
> > >
> > > + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported
> > > + yet\n", __FUNCTION__));
> > >
> > > + return EFI_SUCCESS;
> > >
> > > +}
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Initialize the state information for the CPU Architectural Protocol.
> > >
> > > +
> > >
> > > + @param ImageHandle Image handle this driver.
> > >
> > > + @param SystemTable Pointer to the System Table.
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS Thread can be successfully created
> > >
> > > + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data
> > > + structure
> > >
> > > + @retval EFI_DEVICE_ERROR Cannot create the thread
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +InitializeCpu (
> > >
> > > + IN EFI_HANDLE ImageHandle,
> > >
> > > + IN EFI_SYSTEM_TABLE *SystemTable
> > >
> > > + )
> > >
> > > +{
> > >
> > > + EFI_STATUS Status;
> > >
> > > + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
> > >
> > > +
> > >
> > > + GetFirmwareContextPointer (&FirmwareContext);
> > >
> > > + ASSERT (FirmwareContext != NULL);
> > >
> > > + if (FirmwareContext == NULL) {
> > >
> > > + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of
> > > + EFI_RISCV_FIRMWARE_CONTEXT\n"));
> > >
> > > + return EFI_NOT_FOUND;
> > >
> > > + }
> > >
> > > + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n",
> > > + __FUNCTION__, FirmwareContext));
> > >
> > > +
> > >
> > > + mBootHartId = FirmwareContext->BootHartId;
> > >
> > > + DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n",
> __FUNCTION__,
> > > + mBootHartId));
> > >
> > > +
> > >
> > > +
> > >
> > > + InitializeCpuExceptionHandlers(NULL);
> > >
> > > +
> > >
> > > + //
> > >
> > > + // Make sure interrupts are disabled
> > >
> > > + //
> > >
> > > + DisableInterrupts ();
> > >
> > > +
> > >
> > > + Status = gBS->InstallProtocolInterface (&ImageHandle,
> > >
> > > +
> > > + &gRiscVEfiBootProtocolGuid,
> > >
> > > + EFI_NATIVE_INTERFACE,
> > >
> > > + &gRiscvBootProtocol
> > >
> > > + );
> > >
> > > +
> > >
> > > + ASSERT_EFI_ERROR (Status);
> > >
> > > +
> > >
> > > + //
> > >
> > > + // Install CPU Architectural Protocol
> > >
> > > + //
> > >
> > > + Status = gBS->InstallMultipleProtocolInterfaces (
> > >
> > > + &mCpuHandle,
> > >
> > > + &gEfiCpuArchProtocolGuid,
> > >
> > > + &gCpu,
> > >
> > > + NULL
> > >
> > > + );
> > >
> > > + ASSERT_EFI_ERROR (Status);
> > >
> > > + return Status;
> > >
> > > +}
> > >
> > > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > new file mode 100644
> > > index 0000000000..f039759dbd
> > > --- /dev/null
> > > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > @@ -0,0 +1,200 @@
> > > +/** @file
> > >
> > > + RISC-V CPU DXE module header file.
> > >
> > > +
> > >
> > > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP.
> > > + All rights reserved.<BR>
> > >
> > > + Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > > + reserved.<BR>
> > >
> > > +
> > >
> > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > >
> > > +
> > >
> > > +**/
> > >
> > > +
> > >
> > > +#ifndef CPU_DXE_H_
> > >
> > > +#define CPU_DXE_H_
> > >
> > > +
> > >
> > > +#include <PiDxe.h>
> > >
> > > +
> > >
> > > +#include <Protocol/Cpu.h>
> > >
> > > +#include <Protocol/RiscVBootProtocol.h>
> > >
> > > +#include <Library/RiscVSbiLib.h>
> > >
> > > +#include <Library/BaseLib.h>
> > >
> > > +#include <Library/CpuExceptionHandlerLib.h>
> > >
> > > +#include <Library/DebugLib.h>
> > >
> > > +#include <Library/UefiBootServicesTableLib.h>
> > >
> > > +#include <Library/UefiDriverEntryPoint.h>
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Flush CPU data cache. If the instruction cache is fully coherent
> > >
> > > + with all DMA operations then function can just return EFI_SUCCESS.
> > >
> > > +
> > >
> > > + @param This Protocol instance structure
> > >
> > > + @param Start Physical address to start flushing from.
> > >
> > > + @param Length Number of bytes to flush. Round up to chipset
> > >
> > > + granularity.
> > >
> > > + @param FlushType Specifies the type of flush operation to
> perform.
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS If cache was flushed
> > >
> > > + @retval EFI_UNSUPPORTED If flush type is not supported.
> > >
> > > + @retval EFI_DEVICE_ERROR If requested range could not be flushed.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuFlushCpuDataCache (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > >
> > > + IN EFI_PHYSICAL_ADDRESS Start,
> > >
> > > + IN UINT64 Length,
> > >
> > > + IN EFI_CPU_FLUSH_TYPE FlushType
> > >
> > > + );
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Enables CPU interrupts.
> > >
> > > +
> > >
> > > + @param This Protocol instance structure
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS If interrupts were enabled in the CPU
> > >
> > > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the
> CPU.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuEnableInterrupt (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > >
> > > + );
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Disables CPU interrupts.
> > >
> > > +
> > >
> > > + @param This Protocol instance structure
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > >
> > > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the
> CPU.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuDisableInterrupt (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > >
> > > + );
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Return the state of interrupts.
> > >
> > > +
> > >
> > > + @param This Protocol instance structure
> > >
> > > + @param State Pointer to the CPU's current interrupt state
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > >
> > > + @retval EFI_INVALID_PARAMETER State is NULL.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuGetInterruptState (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > >
> > > + OUT BOOLEAN *State
> > >
> > > + );
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Generates an INIT to the CPU.
> > >
> > > +
> > >
> > > + @param This Protocol instance structure
> > >
> > > + @param InitType Type of CPU INIT to perform
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS If CPU INIT occurred. This value should never
> be
> > >
> > > + seen.
> > >
> > > + @retval EFI_DEVICE_ERROR If CPU INIT failed.
> > >
> > > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not
> supported.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuInit (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > >
> > > + IN EFI_CPU_INIT_TYPE InitType
> > >
> > > + );
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Registers a function to be called from the CPU interrupt handler.
> > >
> > > +
> > >
> > > + @param This Protocol instance structure
> > >
> > > + @param InterruptType Defines which interrupt to hook. IA-32
> > >
> > > + valid range is 0x00 through 0xFF
> > >
> > > + @param InterruptHandler A pointer to a function of type
> > >
> > > + EFI_CPU_INTERRUPT_HANDLER that is
> > > + called
> > >
> > > + when a processor interrupt occurs.
> > > + A null
> > >
> > > + pointer is an error condition.
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS If handler installed or uninstalled.
> > >
> > > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a
> > > handler
> > >
> > > + for InterruptType was previously installed.
> > >
> > > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a
> > > + handler for
> > >
> > > + InterruptType was not previously installed.
> > >
> > > + @retval EFI_UNSUPPORTED The interrupt specified by
> InterruptType
> > >
> > > + is not supported.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuRegisterInterruptHandler (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > >
> > > + IN EFI_EXCEPTION_TYPE InterruptType,
> > >
> > > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
> > >
> > > + );
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Returns a timer value from one of the CPU's internal timers.
> > > + There is no
> > >
> > > + inherent time interval between ticks but is a function of the CPU
> > > frequency.
> > >
> > > +
> > >
> > > + @param This - Protocol instance structure.
> > >
> > > + @param TimerIndex - Specifies which CPU timer is requested.
> > >
> > > + @param TimerValue - Pointer to the returned timer value.
> > >
> > > + @param TimerPeriod - A pointer to the amount of time that
> passes
> > >
> > > + in femtoseconds (10-15) for each
> > > + increment
> > >
> > > + of TimerValue. If TimerValue does
> > > + not
> > >
> > > + increment at a predictable rate,
> > > + then 0 is
> > >
> > > + returned. The amount of time that
> > > + has
> > >
> > > + passed between two calls to
> > > + GetTimerValue()
> > >
> > > + can be calculated with the formula
> > >
> > > + (TimerValue2 - TimerValue1) * TimerPeriod.
> > >
> > > + This parameter is optional and may be NULL.
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS - If the CPU timer count was returned.
> > >
> > > + @retval EFI_UNSUPPORTED - If the CPU does not have any readable
> > > timers.
> > >
> > > + @retval EFI_DEVICE_ERROR - If an error occurred while reading the
> > > timer.
> > >
> > > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or
> > > + TimerValue
> > > is NULL.
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuGetTimerValue (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > >
> > > + IN UINT32 TimerIndex,
> > >
> > > + OUT UINT64 *TimerValue,
> > >
> > > + OUT UINT64 *TimerPeriod OPTIONAL
> > >
> > > + );
> > >
> > > +
> > >
> > > +/**
> > >
> > > + Set memory cacheability attributes for given range of memeory.
> > >
> > > +
> > >
> > > + @param This Protocol instance structure
> > >
> > > + @param BaseAddress Specifies the start address of the
> > >
> > > + memory range
> > >
> > > + @param Length Specifies the length of the memory range
> > >
> > > + @param Attributes The memory cacheability for the memory
> range
> > >
> > > +
> > >
> > > + @retval EFI_SUCCESS If the cacheability of that memory range is
> > >
> > > + set successfully
> > >
> > > + @retval EFI_UNSUPPORTED If the desired operation cannot be
> done
> > >
> > > + @retval EFI_INVALID_PARAMETER The input parameter is not
> > > + correct,
> > >
> > > + such as Length = 0
> > >
> > > +
> > >
> > > +**/
> > >
> > > +EFI_STATUS
> > >
> > > +EFIAPI
> > >
> > > +CpuSetMemoryAttributes (
> > >
> > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > >
> > > + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> > >
> > > + IN UINT64 Length,
> > >
> > > + IN UINT64 Attributes
> > >
> > > + );
> > >
> > > +
> > >
> > > +#endif
> > >
> > > --
> > > 2.25.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module
2022-09-07 12:46 ` Chang, Abner
@ 2022-09-08 10:53 ` Sunil V L
2022-09-08 12:02 ` Chang, Abner
0 siblings, 1 reply; 24+ messages in thread
From: Sunil V L @ 2022-09-08 10:53 UTC (permalink / raw)
To: Chang, Abner
Cc: devel@edk2.groups.io, Jian J Wang, Liming Gao, Eric Dong, Ray Ni,
Rahul Kumar, Debkumar De, Catharine West, Daniel Schaefer,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel
On Wed, Sep 07, 2022 at 12:46:59PM +0000, Chang, Abner wrote:
> [AMD Official Use Only - General]
>
>
>
> > -----Original Message-----
> > From: Sunil V L <sunilvl@ventanamicro.com>
> > Sent: Wednesday, September 7, 2022 7:22 PM
> > To: Chang, Abner <Abner.Chang@amd.com>
> > Cc: devel@edk2.groups.io; Jian J Wang <jian.j.wang@intel.com>; Liming Gao
> > <gaoliming@byosoft.com.cn>; Eric Dong <eric.dong@intel.com>; Ray Ni
> > <ray.ni@intel.com>; Rahul Kumar <rahul1.kumar@intel.com>; Debkumar De
> > <debkumar.de@intel.com>; Catharine West <catharine.west@intel.com>;
> > Daniel Schaefer <git@danielschaefer.me>; Leif Lindholm
> > <quic_llindhol@quicinc.com>; Ard Biesheuvel <ardb@kernel.org>; Heinrich
> > Schuchardt <heinrich.schuchardt@canonical.com>; Anup Patel
> > <apatel@ventanamicro.com>
> > Subject: Re: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in
> > CpuDxe module
> >
> > [CAUTION: External Email]
> >
> > On Wed, Sep 07, 2022 at 09:32:12AM +0000, Chang, Abner wrote:
> > > [AMD Official Use Only - General]
> > >
> > > Hi Sunil and UefiCpuPkg maintainers,
> > > For CpuDxe case, I think we should abstract CpuDxe to accommodate all
> > processor architectures instead of having copy for each archs.
> > CpuDxeCommon.c can have the generic protocol structure and the
> > installation functions, and CpuDxeCommon.h has the general definitions. So
> > does CpuMp related files. Move processor architecture dependent files to
> > under arch folders. AMD may have some differences with Intel so we will
> > have CpuDxeAmd.inf under CpuDxe\. AMD is revising SmmFeatureCpuLib
> > base on the similar concept. I think this makes the module looks simple and
> > architectural. Furthermore, the similar concept should apply to all modules (if
> > necessary) under UefiCpuPkg.
> > > I think we should revise CpuDxe before adding new arch such as RISC-V
> > and Loongson64 to this module.
> > Thanks Abner!. I have sent V2 in the current form itself since I had to move
> > DSC to OvmfPkg instead of edk2-platforms.
> >
> > I am not sure whether we really need this level of restructuring since I didn't
> > find much to share between architectures. Thats why, I just made current
> > sources as x86 speicifc and added RISC-V sources.
> > Anyway, let me wait for maintainers feedback.
> I was also struggled with UefiCpuPkg when I tried to move RISC-V stuff over here. Some modules are easy to be abstracted but some are not. Some as you mentioned have not much to share among processor archs. For these cases we can use folder or a separate module for the abstraction. Having X86 source code on the module root and other processor archs in the folder look weird though.
>
> >Do you have a patch already
> > for this restructuring? If so, I can rebase RISC-V changes on top of it if
> > maintainers accept the approach.
> No, I don't have that yet. But I am willing to help on restructuring this module and others if maintainers agree with this.
That's great!. Could you please take care of refactoring
DxeCpuExceptionHandlerLib also in UefiCpuPkg along with CpuDxe as soon
as maintainers agree? That would be very helful.
Thanks
Sunil
> Thanks
> Abner
> >
> > Thanks
> > Sunil
> > >
> > > Here is a BZ for UefiCpuPkg rearchitecture,
> > >
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> > >
> > illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D3860&data=05%7C01%7CA
> > bner
> > > .Chang%40amd.com%7Cc9bca42bd85c489c38ff08da90c33618%7C3dd8961fe
> > 4884e60
> > >
> > 8e11a82d994e183d%7C0%7C0%7C637981465382450232%7CUnknown%7CTW
> > FpbGZsb3d8
> > >
> > eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> > D%7C3
> > >
> > 000%7C%7C%7C&sdata=iDjOPZCMAH6BSBhR2kx567ibVHza2ZfhjzLHC77
> > cfI8%3D&
> > > amp;reserved=0
> > >
> > > Abner
> > >
> > > Something looks like below,
> > > CpuDxe\X86\Ia32\
> > > \IA32\CpuAsm.asm
> > > \IA32\PageAttribute.c
> > > \X86\X64\
> > > \X64\CpuAsm.asm
> > > \X64\PageAttribute.c
> > > \X86\CpuGdt.c
> > > \CpuGdt.h
> > > \CpuPageTable.C
> > > \CpuPageTableh.h
> > > \CpuDxe.c
> > > \RISCV\RISCV64\
> > > \RISCV64\CpuDxe.h
> > > \CpuDxe.c
> > > \ARM\ARM\
> > > \AARCH64\
> > > \CpuDxe.c
> > > \CpuDxeCommon.c
> > > \CpuMpCommon.c
> > > \CpuDxeCommon.h
> > > \CpuMpCommon.h
> > > \CpuDxe.inf
> > >
> > >
> > > > -----Original Message-----
> > > > From: Sunil V L <sunilvl@ventanamicro.com>
> > > > Sent: Wednesday, September 7, 2022 1:09 AM
> > > > To: devel@edk2.groups.io
> > > > Cc: Jian J Wang <jian.j.wang@intel.com>; Liming Gao
> > > > <gaoliming@byosoft.com.cn>; Eric Dong <eric.dong@intel.com>; Ray Ni
> > > > <ray.ni@intel.com>; Rahul Kumar <rahul1.kumar@intel.com>; Debkumar
> > > > De <debkumar.de@intel.com>; Catharine West
> > > > <catharine.west@intel.com>; Daniel Schaefer <git@danielschaefer.me>;
> > > > Chang, Abner <Abner.Chang@amd.com>; Leif Lindholm
> > > > <quic_llindhol@quicinc.com>; Ard Biesheuvel <ardb@kernel.org>;
> > > > Heinrich Schuchardt <heinrich.schuchardt@canonical.com>; Anup Patel
> > > > <apatel@ventanamicro.com>; Sunil V L <sunilvl@ventanamicro.com>
> > > > Subject: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in
> > > > CpuDxe module
> > > >
> > > > [CAUTION: External Email]
> > > >
> > > > This DXE module initializes the RISC-V CPU by installing the CPU
> > > > specific ARCH protocol handlers. This also initializes the
> > > > RISCV_EFI_BOOT_PROTOCOL which is required on RISC-V platforms.
> > > >
> > > > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > > > ---
> > > > UefiCpuPkg/CpuDxe/CpuDxe.inf | 16 +-
> > > > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 337
> > > > +++++++++++++++++++++++++++++
> > > > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 200 +++++++++++++++++
> > > > 3 files changed, 552 insertions(+), 1 deletion(-) create mode
> > > > 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > > create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > >
> > > > diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > > b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 4f2ea42f16..17cf2b1ecd 100644
> > > > --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > > +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > > @@ -1,8 +1,12 @@
> > > > ## @file
> > > >
> > > > -# CPU driver installs CPU Architecture Protocol and CPU MP protocol.
> > > >
> > > > +# On X86, CPU driver installs CPU Architecture Protocol and CPU MP
> > > > protocol.
> > > >
> > > > +#
> > > >
> > > > +# On RISC-V, CPU driver installs CPU Architecture Protocol and
> > > > +RISC-V boot
> > > >
> > > > +# protocol
> > > >
> > > > #
> > > >
> > > > # Copyright (c) 2008 - 2019, Intel Corporation. All rights
> > > > reserved.<BR>
> > > >
> > > > # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> > > >
> > > > +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > > > +reserved.<BR>
> > > >
> > > > #
> > > >
> > > > # SPDX-License-Identifier: BSD-2-Clause-Patent
> > > >
> > > > #
> > > >
> > > > @@ -44,6 +48,9 @@
> > > > MtrrLib
> > > >
> > > > UefiCpuLib
> > > >
> > > >
> > > >
> > > > +[LibraryClasses.RISCV64]
> > > >
> > > > + RiscVSbiLib
> > > >
> > > > +
> > > >
> > > > [Sources.IA32, Sources.X64]
> > > >
> > > > CpuDxe.c
> > > >
> > > > CpuDxe.h
> > > >
> > > > @@ -62,11 +69,18 @@
> > > > X64/CpuAsm.nasm
> > > >
> > > > X64/PagingAttribute.c
> > > >
> > > >
> > > >
> > > > +[Sources.RISCV64]
> > > >
> > > > + RiscV64/CpuDxe.c
> > > >
> > > > + RiscV64/CpuDxe.h
> > > >
> > > > +
> > > >
> > > > [Protocols]
> > > >
> > > > gEfiCpuArchProtocolGuid ## PRODUCES
> > > >
> > > > gEfiMpServiceProtocolGuid ## PRODUCES
> > > >
> > > > gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES
> > > >
> > > >
> > > >
> > > > +[Protocols.RISCV64]
> > > >
> > > > + gRiscVEfiBootProtocolGuid ## PRODUCES
> > > >
> > > > +
> > > >
> > > > [Guids]
> > > >
> > > > gIdleLoopEventGuid ## CONSUMES ## Event
> > > >
> > > > gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES ##
> > > > SystemTable
> > > >
> > > > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > > new file mode 100644
> > > > index 0000000000..4112b6b8c6
> > > > --- /dev/null
> > > > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > > @@ -0,0 +1,337 @@
> > > > +/** @file
> > > >
> > > > + RISC-V CPU DXE driver.
> > > >
> > > > +
> > > >
> > > > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP.
> > > > + All rights reserved.<BR>
> > > >
> > > > + Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > > > + reserved.<BR>
> > > >
> > > > +
> > > >
> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +
> > > >
> > > > +#include <Library/PcdLib.h>
> > > >
> > > > +#include <Register/RiscV64/RiscVAsm.h>
> > > >
> > > > +#include "CpuDxe.h"
> > > >
> > > > +
> > > >
> > > > +//
> > > >
> > > > +// Global Variables
> > > >
> > > > +//
> > > >
> > > > +STATIC BOOLEAN mInterruptState = FALSE;
> > > >
> > > > +STATIC EFI_HANDLE mCpuHandle = NULL;
> > > >
> > > > +STATIC UINTN mBootHartId;
> > > >
> > > > +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol;
> > > >
> > > > +
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +RiscvGetBootHartId (
> > > >
> > > > + IN RISCV_EFI_BOOT_PROTOCOL *This,
> > > >
> > > > + OUT UINTN *BootHartId
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + if((This != &gRiscvBootProtocol) || (BootHartId == NULL)) {
> > > >
> > > > + return EFI_INVALID_PARAMETER;
> > > >
> > > > + }
> > > >
> > > > +
> > > >
> > > > + *BootHartId = mBootHartId;
> > > >
> > > > + return EFI_SUCCESS;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol = {
> > > >
> > > > + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION,
> > > >
> > > > + RiscvGetBootHartId
> > > >
> > > > +};
> > > >
> > > > +
> > > >
> > > > +EFI_CPU_ARCH_PROTOCOL gCpu = {
> > > >
> > > > + CpuFlushCpuDataCache,
> > > >
> > > > + CpuEnableInterrupt,
> > > >
> > > > + CpuDisableInterrupt,
> > > >
> > > > + CpuGetInterruptState,
> > > >
> > > > + CpuInit,
> > > >
> > > > + CpuRegisterInterruptHandler,
> > > >
> > > > + CpuGetTimerValue,
> > > >
> > > > + CpuSetMemoryAttributes,
> > > >
> > > > + 1, // NumberOfTimers
> > > >
> > > > + 4 // DmaBufferAlignment
> > > >
> > > > +};
> > > >
> > > > +
> > > >
> > > > +//
> > > >
> > > > +// CPU Arch Protocol Functions
> > > >
> > > > +//
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Flush CPU data cache. If the instruction cache is fully coherent
> > > >
> > > > + with all DMA operations then function can just return EFI_SUCCESS.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param Start Physical address to start flushing from.
> > > >
> > > > + @param Length Number of bytes to flush. Round up to chipset
> > > >
> > > > + granularity.
> > > >
> > > > + @param FlushType Specifies the type of flush operation to
> > perform.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If cache was flushed
> > > >
> > > > + @retval EFI_UNSUPPORTED If flush type is not supported.
> > > >
> > > > + @retval EFI_DEVICE_ERROR If requested range could not be flushed.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuFlushCpuDataCache (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_PHYSICAL_ADDRESS Start,
> > > >
> > > > + IN UINT64 Length,
> > > >
> > > > + IN EFI_CPU_FLUSH_TYPE FlushType
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + return EFI_SUCCESS;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Enables CPU interrupts.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If interrupts were enabled in the CPU
> > > >
> > > > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the
> > CPU.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuEnableInterrupt (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + EnableInterrupts ();
> > > >
> > > > + mInterruptState = TRUE;
> > > >
> > > > + return EFI_SUCCESS;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Disables CPU interrupts.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > > >
> > > > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the
> > CPU.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuDisableInterrupt (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + DisableInterrupts ();
> > > >
> > > > + mInterruptState = FALSE;
> > > >
> > > > + return EFI_SUCCESS;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Return the state of interrupts.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param State Pointer to the CPU's current interrupt state
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER State is NULL.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuGetInterruptState (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + OUT BOOLEAN *State
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + if (State == NULL) {
> > > >
> > > > + return EFI_INVALID_PARAMETER;
> > > >
> > > > + }
> > > >
> > > > +
> > > >
> > > > + *State = mInterruptState;
> > > >
> > > > + return EFI_SUCCESS;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Generates an INIT to the CPU.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param InitType Type of CPU INIT to perform
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If CPU INIT occurred. This value should never
> > be
> > > >
> > > > + seen.
> > > >
> > > > + @retval EFI_DEVICE_ERROR If CPU INIT failed.
> > > >
> > > > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not
> > supported.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuInit (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_CPU_INIT_TYPE InitType
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + return EFI_UNSUPPORTED;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Registers a function to be called from the CPU interrupt handler.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param InterruptType Defines which interrupt to hook. IA-32
> > > >
> > > > + valid range is 0x00 through 0xFF
> > > >
> > > > + @param InterruptHandler A pointer to a function of type
> > > >
> > > > + EFI_CPU_INTERRUPT_HANDLER that is
> > > > + called
> > > >
> > > > + when a processor interrupt occurs.
> > > > + A null
> > > >
> > > > + pointer is an error condition.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If handler installed or uninstalled.
> > > >
> > > > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a
> > > > handler
> > > >
> > > > + for InterruptType was previously installed.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a
> > > > + handler for
> > > >
> > > > + InterruptType was not previously installed.
> > > >
> > > > + @retval EFI_UNSUPPORTED The interrupt specified by
> > InterruptType
> > > >
> > > > + is not supported.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuRegisterInterruptHandler (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_EXCEPTION_TYPE InterruptType,
> > > >
> > > > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + return RegisterCpuInterruptHandler (InterruptType,
> > > > + InterruptHandler);
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Returns a timer value from one of the CPU's internal timers.
> > > > + There is no
> > > >
> > > > + inherent time interval between ticks but is a function of the CPU
> > > > frequency.
> > > >
> > > > +
> > > >
> > > > + @param This - Protocol instance structure.
> > > >
> > > > + @param TimerIndex - Specifies which CPU timer is requested.
> > > >
> > > > + @param TimerValue - Pointer to the returned timer value.
> > > >
> > > > + @param TimerPeriod - A pointer to the amount of time that
> > passes
> > > >
> > > > + in femtoseconds (10-15) for each
> > > > + increment
> > > >
> > > > + of TimerValue. If TimerValue does
> > > > + not
> > > >
> > > > + increment at a predictable rate,
> > > > + then 0 is
> > > >
> > > > + returned. The amount of time that
> > > > + has
> > > >
> > > > + passed between two calls to
> > > > + GetTimerValue()
> > > >
> > > > + can be calculated with the formula
> > > >
> > > > + (TimerValue2 - TimerValue1) * TimerPeriod.
> > > >
> > > > + This parameter is optional and may be NULL.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS - If the CPU timer count was returned.
> > > >
> > > > + @retval EFI_UNSUPPORTED - If the CPU does not have any readable
> > > > timers.
> > > >
> > > > + @retval EFI_DEVICE_ERROR - If an error occurred while reading the
> > > > timer.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or
> > > > + TimerValue
> > > > is NULL.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuGetTimerValue (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN UINT32 TimerIndex,
> > > >
> > > > + OUT UINT64 *TimerValue,
> > > >
> > > > + OUT UINT64 *TimerPeriod OPTIONAL
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + return EFI_UNSUPPORTED;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Implementation of SetMemoryAttributes() service of CPU
> > > > + Architecture
> > > > Protocol.
> > > >
> > > > +
> > > >
> > > > + This function modifies the attributes for the memory region
> > > > + specified by BaseAddress and
> > > >
> > > > + Length from their current attributes to the attributes specified
> > > > + by
> > > > Attributes.
> > > >
> > > > +
> > > >
> > > > + @param This The EFI_CPU_ARCH_PROTOCOL instance.
> > > >
> > > > + @param BaseAddress The physical address that is the start address
> > of a
> > > > memory region.
> > > >
> > > > + @param Length The size in bytes of the memory region.
> > > >
> > > > + @param Attributes The bit mask of attributes to set for the
> > memory
> > > > region.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS The attributes were set for the memory
> > region.
> > > >
> > > > + @retval EFI_ACCESS_DENIED The attributes for the memory
> > resource
> > > > range specified by
> > > >
> > > > + BaseAddress and Length cannot be modified.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER Length is zero.
> > > >
> > > > + Attributes specified an illegal
> > > > + combination of attributes that
> > > >
> > > > + cannot be set together.
> > > >
> > > > + @retval EFI_OUT_OF_RESOURCES There are not enough system
> > > > resources
> > > > + to modify the attributes of
> > > >
> > > > + the memory resource range.
> > > >
> > > > + @retval EFI_UNSUPPORTED The processor does not support one or
> > > > more bytes of the memory
> > > >
> > > > + resource range specified by BaseAddress and Length.
> > > >
> > > > + The bit mask of attributes is not
> > > > + support for the memory resource
> > > >
> > > > + range specified by BaseAddress and Length.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuSetMemoryAttributes (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> > > >
> > > > + IN UINT64 Length,
> > > >
> > > > + IN UINT64 Attributes
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported
> > > > + yet\n", __FUNCTION__));
> > > >
> > > > + return EFI_SUCCESS;
> > > >
> > > > +}
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Initialize the state information for the CPU Architectural Protocol.
> > > >
> > > > +
> > > >
> > > > + @param ImageHandle Image handle this driver.
> > > >
> > > > + @param SystemTable Pointer to the System Table.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS Thread can be successfully created
> > > >
> > > > + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data
> > > > + structure
> > > >
> > > > + @retval EFI_DEVICE_ERROR Cannot create the thread
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +InitializeCpu (
> > > >
> > > > + IN EFI_HANDLE ImageHandle,
> > > >
> > > > + IN EFI_SYSTEM_TABLE *SystemTable
> > > >
> > > > + )
> > > >
> > > > +{
> > > >
> > > > + EFI_STATUS Status;
> > > >
> > > > + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
> > > >
> > > > +
> > > >
> > > > + GetFirmwareContextPointer (&FirmwareContext);
> > > >
> > > > + ASSERT (FirmwareContext != NULL);
> > > >
> > > > + if (FirmwareContext == NULL) {
> > > >
> > > > + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of
> > > > + EFI_RISCV_FIRMWARE_CONTEXT\n"));
> > > >
> > > > + return EFI_NOT_FOUND;
> > > >
> > > > + }
> > > >
> > > > + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n",
> > > > + __FUNCTION__, FirmwareContext));
> > > >
> > > > +
> > > >
> > > > + mBootHartId = FirmwareContext->BootHartId;
> > > >
> > > > + DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n",
> > __FUNCTION__,
> > > > + mBootHartId));
> > > >
> > > > +
> > > >
> > > > +
> > > >
> > > > + InitializeCpuExceptionHandlers(NULL);
> > > >
> > > > +
> > > >
> > > > + //
> > > >
> > > > + // Make sure interrupts are disabled
> > > >
> > > > + //
> > > >
> > > > + DisableInterrupts ();
> > > >
> > > > +
> > > >
> > > > + Status = gBS->InstallProtocolInterface (&ImageHandle,
> > > >
> > > > +
> > > > + &gRiscVEfiBootProtocolGuid,
> > > >
> > > > + EFI_NATIVE_INTERFACE,
> > > >
> > > > + &gRiscvBootProtocol
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > + ASSERT_EFI_ERROR (Status);
> > > >
> > > > +
> > > >
> > > > + //
> > > >
> > > > + // Install CPU Architectural Protocol
> > > >
> > > > + //
> > > >
> > > > + Status = gBS->InstallMultipleProtocolInterfaces (
> > > >
> > > > + &mCpuHandle,
> > > >
> > > > + &gEfiCpuArchProtocolGuid,
> > > >
> > > > + &gCpu,
> > > >
> > > > + NULL
> > > >
> > > > + );
> > > >
> > > > + ASSERT_EFI_ERROR (Status);
> > > >
> > > > + return Status;
> > > >
> > > > +}
> > > >
> > > > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > > new file mode 100644
> > > > index 0000000000..f039759dbd
> > > > --- /dev/null
> > > > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > > @@ -0,0 +1,200 @@
> > > > +/** @file
> > > >
> > > > + RISC-V CPU DXE module header file.
> > > >
> > > > +
> > > >
> > > > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP.
> > > > + All rights reserved.<BR>
> > > >
> > > > + Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > > > + reserved.<BR>
> > > >
> > > > +
> > > >
> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +
> > > >
> > > > +#ifndef CPU_DXE_H_
> > > >
> > > > +#define CPU_DXE_H_
> > > >
> > > > +
> > > >
> > > > +#include <PiDxe.h>
> > > >
> > > > +
> > > >
> > > > +#include <Protocol/Cpu.h>
> > > >
> > > > +#include <Protocol/RiscVBootProtocol.h>
> > > >
> > > > +#include <Library/RiscVSbiLib.h>
> > > >
> > > > +#include <Library/BaseLib.h>
> > > >
> > > > +#include <Library/CpuExceptionHandlerLib.h>
> > > >
> > > > +#include <Library/DebugLib.h>
> > > >
> > > > +#include <Library/UefiBootServicesTableLib.h>
> > > >
> > > > +#include <Library/UefiDriverEntryPoint.h>
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Flush CPU data cache. If the instruction cache is fully coherent
> > > >
> > > > + with all DMA operations then function can just return EFI_SUCCESS.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param Start Physical address to start flushing from.
> > > >
> > > > + @param Length Number of bytes to flush. Round up to chipset
> > > >
> > > > + granularity.
> > > >
> > > > + @param FlushType Specifies the type of flush operation to
> > perform.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If cache was flushed
> > > >
> > > > + @retval EFI_UNSUPPORTED If flush type is not supported.
> > > >
> > > > + @retval EFI_DEVICE_ERROR If requested range could not be flushed.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuFlushCpuDataCache (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_PHYSICAL_ADDRESS Start,
> > > >
> > > > + IN UINT64 Length,
> > > >
> > > > + IN EFI_CPU_FLUSH_TYPE FlushType
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Enables CPU interrupts.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If interrupts were enabled in the CPU
> > > >
> > > > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the
> > CPU.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuEnableInterrupt (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Disables CPU interrupts.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > > >
> > > > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the
> > CPU.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuDisableInterrupt (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Return the state of interrupts.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param State Pointer to the CPU's current interrupt state
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER State is NULL.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuGetInterruptState (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + OUT BOOLEAN *State
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Generates an INIT to the CPU.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param InitType Type of CPU INIT to perform
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If CPU INIT occurred. This value should never
> > be
> > > >
> > > > + seen.
> > > >
> > > > + @retval EFI_DEVICE_ERROR If CPU INIT failed.
> > > >
> > > > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not
> > supported.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuInit (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_CPU_INIT_TYPE InitType
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Registers a function to be called from the CPU interrupt handler.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param InterruptType Defines which interrupt to hook. IA-32
> > > >
> > > > + valid range is 0x00 through 0xFF
> > > >
> > > > + @param InterruptHandler A pointer to a function of type
> > > >
> > > > + EFI_CPU_INTERRUPT_HANDLER that is
> > > > + called
> > > >
> > > > + when a processor interrupt occurs.
> > > > + A null
> > > >
> > > > + pointer is an error condition.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If handler installed or uninstalled.
> > > >
> > > > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a
> > > > handler
> > > >
> > > > + for InterruptType was previously installed.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a
> > > > + handler for
> > > >
> > > > + InterruptType was not previously installed.
> > > >
> > > > + @retval EFI_UNSUPPORTED The interrupt specified by
> > InterruptType
> > > >
> > > > + is not supported.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuRegisterInterruptHandler (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_EXCEPTION_TYPE InterruptType,
> > > >
> > > > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Returns a timer value from one of the CPU's internal timers.
> > > > + There is no
> > > >
> > > > + inherent time interval between ticks but is a function of the CPU
> > > > frequency.
> > > >
> > > > +
> > > >
> > > > + @param This - Protocol instance structure.
> > > >
> > > > + @param TimerIndex - Specifies which CPU timer is requested.
> > > >
> > > > + @param TimerValue - Pointer to the returned timer value.
> > > >
> > > > + @param TimerPeriod - A pointer to the amount of time that
> > passes
> > > >
> > > > + in femtoseconds (10-15) for each
> > > > + increment
> > > >
> > > > + of TimerValue. If TimerValue does
> > > > + not
> > > >
> > > > + increment at a predictable rate,
> > > > + then 0 is
> > > >
> > > > + returned. The amount of time that
> > > > + has
> > > >
> > > > + passed between two calls to
> > > > + GetTimerValue()
> > > >
> > > > + can be calculated with the formula
> > > >
> > > > + (TimerValue2 - TimerValue1) * TimerPeriod.
> > > >
> > > > + This parameter is optional and may be NULL.
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS - If the CPU timer count was returned.
> > > >
> > > > + @retval EFI_UNSUPPORTED - If the CPU does not have any readable
> > > > timers.
> > > >
> > > > + @retval EFI_DEVICE_ERROR - If an error occurred while reading the
> > > > timer.
> > > >
> > > > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or
> > > > + TimerValue
> > > > is NULL.
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuGetTimerValue (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN UINT32 TimerIndex,
> > > >
> > > > + OUT UINT64 *TimerValue,
> > > >
> > > > + OUT UINT64 *TimerPeriod OPTIONAL
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +/**
> > > >
> > > > + Set memory cacheability attributes for given range of memeory.
> > > >
> > > > +
> > > >
> > > > + @param This Protocol instance structure
> > > >
> > > > + @param BaseAddress Specifies the start address of the
> > > >
> > > > + memory range
> > > >
> > > > + @param Length Specifies the length of the memory range
> > > >
> > > > + @param Attributes The memory cacheability for the memory
> > range
> > > >
> > > > +
> > > >
> > > > + @retval EFI_SUCCESS If the cacheability of that memory range is
> > > >
> > > > + set successfully
> > > >
> > > > + @retval EFI_UNSUPPORTED If the desired operation cannot be
> > done
> > > >
> > > > + @retval EFI_INVALID_PARAMETER The input parameter is not
> > > > + correct,
> > > >
> > > > + such as Length = 0
> > > >
> > > > +
> > > >
> > > > +**/
> > > >
> > > > +EFI_STATUS
> > > >
> > > > +EFIAPI
> > > >
> > > > +CpuSetMemoryAttributes (
> > > >
> > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > >
> > > > + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> > > >
> > > > + IN UINT64 Length,
> > > >
> > > > + IN UINT64 Attributes
> > > >
> > > > + );
> > > >
> > > > +
> > > >
> > > > +#endif
> > > >
> > > > --
> > > > 2.25.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module
2022-09-08 10:53 ` Sunil V L
@ 2022-09-08 12:02 ` Chang, Abner
0 siblings, 0 replies; 24+ messages in thread
From: Chang, Abner @ 2022-09-08 12:02 UTC (permalink / raw)
To: Sunil V L
Cc: devel@edk2.groups.io, Jian J Wang, Liming Gao, Eric Dong, Ray Ni,
Rahul Kumar, Debkumar De, Catharine West, Daniel Schaefer,
Leif Lindholm, Ard Biesheuvel, Heinrich Schuchardt, Anup Patel
[AMD Official Use Only - General]
> -----Original Message-----
> From: Sunil V L <sunilvl@ventanamicro.com>
> Sent: Thursday, September 8, 2022 6:53 PM
> To: Chang, Abner <Abner.Chang@amd.com>
> Cc: devel@edk2.groups.io; Jian J Wang <jian.j.wang@intel.com>; Liming Gao
> <gaoliming@byosoft.com.cn>; Eric Dong <eric.dong@intel.com>; Ray Ni
> <ray.ni@intel.com>; Rahul Kumar <rahul1.kumar@intel.com>; Debkumar De
> <debkumar.de@intel.com>; Catharine West <catharine.west@intel.com>;
> Daniel Schaefer <git@danielschaefer.me>; Leif Lindholm
> <quic_llindhol@quicinc.com>; Ard Biesheuvel <ardb@kernel.org>; Heinrich
> Schuchardt <heinrich.schuchardt@canonical.com>; Anup Patel
> <apatel@ventanamicro.com>
> Subject: Re: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in
> CpuDxe module
>
> [CAUTION: External Email]
>
> On Wed, Sep 07, 2022 at 12:46:59PM +0000, Chang, Abner wrote:
> > [AMD Official Use Only - General]
> >
> >
> >
> > > -----Original Message-----
> > > From: Sunil V L <sunilvl@ventanamicro.com>
> > > Sent: Wednesday, September 7, 2022 7:22 PM
> > > To: Chang, Abner <Abner.Chang@amd.com>
> > > Cc: devel@edk2.groups.io; Jian J Wang <jian.j.wang@intel.com>;
> > > Liming Gao <gaoliming@byosoft.com.cn>; Eric Dong
> > > <eric.dong@intel.com>; Ray Ni <ray.ni@intel.com>; Rahul Kumar
> > > <rahul1.kumar@intel.com>; Debkumar De <debkumar.de@intel.com>;
> > > Catharine West <catharine.west@intel.com>; Daniel Schaefer
> > > <git@danielschaefer.me>; Leif Lindholm <quic_llindhol@quicinc.com>;
> > > Ard Biesheuvel <ardb@kernel.org>; Heinrich Schuchardt
> > > <heinrich.schuchardt@canonical.com>; Anup Patel
> > > <apatel@ventanamicro.com>
> > > Subject: Re: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support
> > > in CpuDxe module
> > >
> > > [CAUTION: External Email]
> > >
> > > On Wed, Sep 07, 2022 at 09:32:12AM +0000, Chang, Abner wrote:
> > > > [AMD Official Use Only - General]
> > > >
> > > > Hi Sunil and UefiCpuPkg maintainers, For CpuDxe case, I think we
> > > > should abstract CpuDxe to accommodate all
> > > processor architectures instead of having copy for each archs.
> > > CpuDxeCommon.c can have the generic protocol structure and the
> > > installation functions, and CpuDxeCommon.h has the general
> > > definitions. So does CpuMp related files. Move processor
> > > architecture dependent files to under arch folders. AMD may have
> > > some differences with Intel so we will have CpuDxeAmd.inf under
> > > CpuDxe\. AMD is revising SmmFeatureCpuLib base on the similar
> > > concept. I think this makes the module looks simple and
> > > architectural. Furthermore, the similar concept should apply to all
> > > modules (if
> > > necessary) under UefiCpuPkg.
> > > > I think we should revise CpuDxe before adding new arch such as
> > > > RISC-V
> > > and Loongson64 to this module.
> > > Thanks Abner!. I have sent V2 in the current form itself since I had
> > > to move DSC to OvmfPkg instead of edk2-platforms.
> > >
> > > I am not sure whether we really need this level of restructuring
> > > since I didn't find much to share between architectures. Thats why,
> > > I just made current sources as x86 speicifc and added RISC-V sources.
> > > Anyway, let me wait for maintainers feedback.
> > I was also struggled with UefiCpuPkg when I tried to move RISC-V stuff
> over here. Some modules are easy to be abstracted but some are not. Some
> as you mentioned have not much to share among processor archs. For these
> cases we can use folder or a separate module for the abstraction. Having X86
> source code on the module root and other processor archs in the folder look
> weird though.
> >
> > >Do you have a patch already
> > > for this restructuring? If so, I can rebase RISC-V changes on top of
> > >it if maintainers accept the approach.
> > No, I don't have that yet. But I am willing to help on restructuring this
> module and others if maintainers agree with this.
> That's great!. Could you please take care of refactoring
> DxeCpuExceptionHandlerLib also in UefiCpuPkg along with CpuDxe as soon
> as maintainers agree? That would be very helful.
Yes, I can do it together.
Abner
>
> Thanks
> Sunil
> > Thanks
> > Abner
> > >
> > > Thanks
> > > Sunil
> > > >
> > > > Here is a BZ for UefiCpuPkg rearchitecture,
> > > >
> > >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbu
> > > gz
> > > >
> > >
> illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D3860&data=05%7C01%7CA
> > > bner
> > >
> > .Chang%40amd.com%7Cc9bca42bd85c489c38ff08da90c33618%7C3dd8961fe
> > > 4884e60
> > > >
> > >
> 8e11a82d994e183d%7C0%7C0%7C637981465382450232%7CUnknown%7CTW
> > > FpbGZsb3d8
> > > >
> > >
> eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> > > D%7C3
> > > >
> > >
> 000%7C%7C%7C&sdata=iDjOPZCMAH6BSBhR2kx567ibVHza2ZfhjzLHC77
> > > cfI8%3D&
> > > > amp;reserved=0
> > > >
> > > > Abner
> > > >
> > > > Something looks like below,
> > > > CpuDxe\X86\Ia32\
> > > > \IA32\CpuAsm.asm
> > > > \IA32\PageAttribute.c
> > > > \X86\X64\
> > > > \X64\CpuAsm.asm
> > > > \X64\PageAttribute.c
> > > > \X86\CpuGdt.c
> > > > \CpuGdt.h
> > > > \CpuPageTable.C
> > > > \CpuPageTableh.h
> > > > \CpuDxe.c
> > > > \RISCV\RISCV64\
> > > > \RISCV64\CpuDxe.h
> > > > \CpuDxe.c
> > > > \ARM\ARM\
> > > > \AARCH64\
> > > > \CpuDxe.c
> > > > \CpuDxeCommon.c
> > > > \CpuMpCommon.c
> > > > \CpuDxeCommon.h
> > > > \CpuMpCommon.h
> > > > \CpuDxe.inf
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Sunil V L <sunilvl@ventanamicro.com>
> > > > > Sent: Wednesday, September 7, 2022 1:09 AM
> > > > > To: devel@edk2.groups.io
> > > > > Cc: Jian J Wang <jian.j.wang@intel.com>; Liming Gao
> > > > > <gaoliming@byosoft.com.cn>; Eric Dong <eric.dong@intel.com>; Ray
> > > > > Ni <ray.ni@intel.com>; Rahul Kumar <rahul1.kumar@intel.com>;
> > > > > Debkumar De <debkumar.de@intel.com>; Catharine West
> > > > > <catharine.west@intel.com>; Daniel Schaefer
> > > > > <git@danielschaefer.me>; Chang, Abner <Abner.Chang@amd.com>;
> > > > > Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
> > > > > <ardb@kernel.org>; Heinrich Schuchardt
> > > > > <heinrich.schuchardt@canonical.com>; Anup Patel
> > > > > <apatel@ventanamicro.com>; Sunil V L <sunilvl@ventanamicro.com>
> > > > > Subject: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support
> > > > > in CpuDxe module
> > > > >
> > > > > [CAUTION: External Email]
> > > > >
> > > > > This DXE module initializes the RISC-V CPU by installing the CPU
> > > > > specific ARCH protocol handlers. This also initializes the
> > > > > RISCV_EFI_BOOT_PROTOCOL which is required on RISC-V platforms.
> > > > >
> > > > > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > > > > ---
> > > > > UefiCpuPkg/CpuDxe/CpuDxe.inf | 16 +-
> > > > > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 337
> > > > > +++++++++++++++++++++++++++++
> > > > > UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 200 +++++++++++++++++
> > > > > 3 files changed, 552 insertions(+), 1 deletion(-) create mode
> > > > > 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > > > create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > > >
> > > > > diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > > > b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 4f2ea42f16..17cf2b1ecd
> > > > > 100644
> > > > > --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > > > +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
> > > > > @@ -1,8 +1,12 @@
> > > > > ## @file
> > > > >
> > > > > -# CPU driver installs CPU Architecture Protocol and CPU MP protocol.
> > > > >
> > > > > +# On X86, CPU driver installs CPU Architecture Protocol and
> > > > > +CPU MP
> > > > > protocol.
> > > > >
> > > > > +#
> > > > >
> > > > > +# On RISC-V, CPU driver installs CPU Architecture Protocol and
> > > > > +RISC-V boot
> > > > >
> > > > > +# protocol
> > > > >
> > > > > #
> > > > >
> > > > > # Copyright (c) 2008 - 2019, Intel Corporation. All rights
> > > > > reserved.<BR>
> > > > >
> > > > > # Copyright (c) 2017, AMD Incorporated. All rights
> > > > > reserved.<BR>
> > > > >
> > > > > +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > > > > +reserved.<BR>
> > > > >
> > > > > #
> > > > >
> > > > > # SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > >
> > > > > #
> > > > >
> > > > > @@ -44,6 +48,9 @@
> > > > > MtrrLib
> > > > >
> > > > > UefiCpuLib
> > > > >
> > > > >
> > > > >
> > > > > +[LibraryClasses.RISCV64]
> > > > >
> > > > > + RiscVSbiLib
> > > > >
> > > > > +
> > > > >
> > > > > [Sources.IA32, Sources.X64]
> > > > >
> > > > > CpuDxe.c
> > > > >
> > > > > CpuDxe.h
> > > > >
> > > > > @@ -62,11 +69,18 @@
> > > > > X64/CpuAsm.nasm
> > > > >
> > > > > X64/PagingAttribute.c
> > > > >
> > > > >
> > > > >
> > > > > +[Sources.RISCV64]
> > > > >
> > > > > + RiscV64/CpuDxe.c
> > > > >
> > > > > + RiscV64/CpuDxe.h
> > > > >
> > > > > +
> > > > >
> > > > > [Protocols]
> > > > >
> > > > > gEfiCpuArchProtocolGuid ## PRODUCES
> > > > >
> > > > > gEfiMpServiceProtocolGuid ## PRODUCES
> > > > >
> > > > > gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES
> > > > >
> > > > >
> > > > >
> > > > > +[Protocols.RISCV64]
> > > > >
> > > > > + gRiscVEfiBootProtocolGuid ## PRODUCES
> > > > >
> > > > > +
> > > > >
> > > > > [Guids]
> > > > >
> > > > > gIdleLoopEventGuid ## CONSUMES ## Event
> > > > >
> > > > > gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES
> ##
> > > > > SystemTable
> > > > >
> > > > > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > > > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > > > new file mode 100644
> > > > > index 0000000000..4112b6b8c6
> > > > > --- /dev/null
> > > > > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
> > > > > @@ -0,0 +1,337 @@
> > > > > +/** @file
> > > > >
> > > > > + RISC-V CPU DXE driver.
> > > > >
> > > > > +
> > > > >
> > > > > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development
> LP.
> > > > > + All rights reserved.<BR>
> > > > >
> > > > > + Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > > > > + reserved.<BR>
> > > > >
> > > > > +
> > > > >
> > > > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +
> > > > >
> > > > > +#include <Library/PcdLib.h>
> > > > >
> > > > > +#include <Register/RiscV64/RiscVAsm.h>
> > > > >
> > > > > +#include "CpuDxe.h"
> > > > >
> > > > > +
> > > > >
> > > > > +//
> > > > >
> > > > > +// Global Variables
> > > > >
> > > > > +//
> > > > >
> > > > > +STATIC BOOLEAN mInterruptState = FALSE;
> > > > >
> > > > > +STATIC EFI_HANDLE mCpuHandle = NULL;
> > > > >
> > > > > +STATIC UINTN mBootHartId;
> > > > >
> > > > > +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol;
> > > > >
> > > > > +
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +RiscvGetBootHartId (
> > > > >
> > > > > + IN RISCV_EFI_BOOT_PROTOCOL *This,
> > > > >
> > > > > + OUT UINTN *BootHartId
> > > > >
> > > > > + )
> > > > >
> > > > > +{
> > > > >
> > > > > + if((This != &gRiscvBootProtocol) || (BootHartId == NULL)) {
> > > > >
> > > > > + return EFI_INVALID_PARAMETER;
> > > > >
> > > > > + }
> > > > >
> > > > > +
> > > > >
> > > > > + *BootHartId = mBootHartId;
> > > > >
> > > > > + return EFI_SUCCESS;
> > > > >
> > > > > +}
> > > > >
> > > > > +
> > > > >
> > > > > +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol = {
> > > > >
> > > > > + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION,
> > > > >
> > > > > + RiscvGetBootHartId
> > > > >
> > > > > +};
> > > > >
> > > > > +
> > > > >
> > > > > +EFI_CPU_ARCH_PROTOCOL gCpu = {
> > > > >
> > > > > + CpuFlushCpuDataCache,
> > > > >
> > > > > + CpuEnableInterrupt,
> > > > >
> > > > > + CpuDisableInterrupt,
> > > > >
> > > > > + CpuGetInterruptState,
> > > > >
> > > > > + CpuInit,
> > > > >
> > > > > + CpuRegisterInterruptHandler,
> > > > >
> > > > > + CpuGetTimerValue,
> > > > >
> > > > > + CpuSetMemoryAttributes,
> > > > >
> > > > > + 1, // NumberOfTimers
> > > > >
> > > > > + 4 // DmaBufferAlignment
> > > > >
> > > > > +};
> > > > >
> > > > > +
> > > > >
> > > > > +//
> > > > >
> > > > > +// CPU Arch Protocol Functions
> > > > >
> > > > > +//
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Flush CPU data cache. If the instruction cache is fully
> > > > > + coherent
> > > > >
> > > > > + with all DMA operations then function can just return EFI_SUCCESS.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This Protocol instance structure
> > > > >
> > > > > + @param Start Physical address to start flushing from.
> > > > >
> > > > > + @param Length Number of bytes to flush. Round up to
> chipset
> > > > >
> > > > > + granularity.
> > > > >
> > > > > + @param FlushType Specifies the type of flush operation to
> > > perform.
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS If cache was flushed
> > > > >
> > > > > + @retval EFI_UNSUPPORTED If flush type is not supported.
> > > > >
> > > > > + @retval EFI_DEVICE_ERROR If requested range could not be
> flushed.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuFlushCpuDataCache (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > > >
> > > > > + IN EFI_PHYSICAL_ADDRESS Start,
> > > > >
> > > > > + IN UINT64 Length,
> > > > >
> > > > > + IN EFI_CPU_FLUSH_TYPE FlushType
> > > > >
> > > > > + )
> > > > >
> > > > > +{
> > > > >
> > > > > + return EFI_SUCCESS;
> > > > >
> > > > > +}
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Enables CPU interrupts.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This Protocol instance structure
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS If interrupts were enabled in the CPU
> > > > >
> > > > > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled
> > > > > + on the
> > > CPU.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuEnableInterrupt (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > > > >
> > > > > + )
> > > > >
> > > > > +{
> > > > >
> > > > > + EnableInterrupts ();
> > > > >
> > > > > + mInterruptState = TRUE;
> > > > >
> > > > > + return EFI_SUCCESS;
> > > > >
> > > > > +}
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Disables CPU interrupts.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This Protocol instance structure
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > > > >
> > > > > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled
> > > > > + on the
> > > CPU.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuDisableInterrupt (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > > > >
> > > > > + )
> > > > >
> > > > > +{
> > > > >
> > > > > + DisableInterrupts ();
> > > > >
> > > > > + mInterruptState = FALSE;
> > > > >
> > > > > + return EFI_SUCCESS;
> > > > >
> > > > > +}
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Return the state of interrupts.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This Protocol instance structure
> > > > >
> > > > > + @param State Pointer to the CPU's current interrupt state
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > > > >
> > > > > + @retval EFI_INVALID_PARAMETER State is NULL.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuGetInterruptState (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > > >
> > > > > + OUT BOOLEAN *State
> > > > >
> > > > > + )
> > > > >
> > > > > +{
> > > > >
> > > > > + if (State == NULL) {
> > > > >
> > > > > + return EFI_INVALID_PARAMETER;
> > > > >
> > > > > + }
> > > > >
> > > > > +
> > > > >
> > > > > + *State = mInterruptState;
> > > > >
> > > > > + return EFI_SUCCESS;
> > > > >
> > > > > +}
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Generates an INIT to the CPU.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This Protocol instance structure
> > > > >
> > > > > + @param InitType Type of CPU INIT to perform
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS If CPU INIT occurred. This value should
> never
> > > be
> > > > >
> > > > > + seen.
> > > > >
> > > > > + @retval EFI_DEVICE_ERROR If CPU INIT failed.
> > > > >
> > > > > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not
> > > supported.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuInit (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > > >
> > > > > + IN EFI_CPU_INIT_TYPE InitType
> > > > >
> > > > > + )
> > > > >
> > > > > +{
> > > > >
> > > > > + return EFI_UNSUPPORTED;
> > > > >
> > > > > +}
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Registers a function to be called from the CPU interrupt handler.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This Protocol instance structure
> > > > >
> > > > > + @param InterruptType Defines which interrupt to hook. IA-32
> > > > >
> > > > > + valid range is 0x00 through
> > > > > + 0xFF
> > > > >
> > > > > + @param InterruptHandler A pointer to a function of type
> > > > >
> > > > > + EFI_CPU_INTERRUPT_HANDLER that
> > > > > + is called
> > > > >
> > > > > + when a processor interrupt occurs.
> > > > > + A null
> > > > >
> > > > > + pointer is an error condition.
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS If handler installed or uninstalled.
> > > > >
> > > > > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and
> a
> > > > > handler
> > > > >
> > > > > + for InterruptType was previously installed.
> > > > >
> > > > > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and
> > > > > + a handler for
> > > > >
> > > > > + InterruptType was not previously installed.
> > > > >
> > > > > + @retval EFI_UNSUPPORTED The interrupt specified by
> > > InterruptType
> > > > >
> > > > > + is not supported.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuRegisterInterruptHandler (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > > >
> > > > > + IN EFI_EXCEPTION_TYPE InterruptType,
> > > > >
> > > > > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
> > > > >
> > > > > + )
> > > > >
> > > > > +{
> > > > >
> > > > > + return RegisterCpuInterruptHandler (InterruptType,
> > > > > + InterruptHandler);
> > > > >
> > > > > +}
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Returns a timer value from one of the CPU's internal timers.
> > > > > + There is no
> > > > >
> > > > > + inherent time interval between ticks but is a function of the
> > > > > + CPU
> > > > > frequency.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This - Protocol instance structure.
> > > > >
> > > > > + @param TimerIndex - Specifies which CPU timer is requested.
> > > > >
> > > > > + @param TimerValue - Pointer to the returned timer value.
> > > > >
> > > > > + @param TimerPeriod - A pointer to the amount of time that
> > > passes
> > > > >
> > > > > + in femtoseconds (10-15) for
> > > > > + each increment
> > > > >
> > > > > + of TimerValue. If TimerValue
> > > > > + does not
> > > > >
> > > > > + increment at a predictable
> > > > > + rate, then 0 is
> > > > >
> > > > > + returned. The amount of time
> > > > > + that has
> > > > >
> > > > > + passed between two calls to
> > > > > + GetTimerValue()
> > > > >
> > > > > + can be calculated with the
> > > > > + formula
> > > > >
> > > > > + (TimerValue2 - TimerValue1) * TimerPeriod.
> > > > >
> > > > > + This parameter is optional and may be NULL.
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS - If the CPU timer count was returned.
> > > > >
> > > > > + @retval EFI_UNSUPPORTED - If the CPU does not have any
> readable
> > > > > timers.
> > > > >
> > > > > + @retval EFI_DEVICE_ERROR - If an error occurred while reading
> the
> > > > > timer.
> > > > >
> > > > > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or
> > > > > + TimerValue
> > > > > is NULL.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuGetTimerValue (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > > >
> > > > > + IN UINT32 TimerIndex,
> > > > >
> > > > > + OUT UINT64 *TimerValue,
> > > > >
> > > > > + OUT UINT64 *TimerPeriod OPTIONAL
> > > > >
> > > > > + )
> > > > >
> > > > > +{
> > > > >
> > > > > + return EFI_UNSUPPORTED;
> > > > >
> > > > > +}
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Implementation of SetMemoryAttributes() service of CPU
> > > > > + Architecture
> > > > > Protocol.
> > > > >
> > > > > +
> > > > >
> > > > > + This function modifies the attributes for the memory region
> > > > > + specified by BaseAddress and
> > > > >
> > > > > + Length from their current attributes to the attributes
> > > > > + specified by
> > > > > Attributes.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This The EFI_CPU_ARCH_PROTOCOL instance.
> > > > >
> > > > > + @param BaseAddress The physical address that is the start
> address
> > > of a
> > > > > memory region.
> > > > >
> > > > > + @param Length The size in bytes of the memory region.
> > > > >
> > > > > + @param Attributes The bit mask of attributes to set for the
> > > memory
> > > > > region.
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS The attributes were set for the memory
> > > region.
> > > > >
> > > > > + @retval EFI_ACCESS_DENIED The attributes for the memory
> > > resource
> > > > > range specified by
> > > > >
> > > > > + BaseAddress and Length cannot be modified.
> > > > >
> > > > > + @retval EFI_INVALID_PARAMETER Length is zero.
> > > > >
> > > > > + Attributes specified an illegal
> > > > > + combination of attributes that
> > > > >
> > > > > + cannot be set together.
> > > > >
> > > > > + @retval EFI_OUT_OF_RESOURCES There are not enough system
> > > > > resources
> > > > > + to modify the attributes of
> > > > >
> > > > > + the memory resource range.
> > > > >
> > > > > + @retval EFI_UNSUPPORTED The processor does not support
> one or
> > > > > more bytes of the memory
> > > > >
> > > > > + resource range specified by BaseAddress and Length.
> > > > >
> > > > > + The bit mask of attributes is
> > > > > + not support for the memory resource
> > > > >
> > > > > + range specified by BaseAddress and Length.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuSetMemoryAttributes (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > > >
> > > > > + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> > > > >
> > > > > + IN UINT64 Length,
> > > > >
> > > > > + IN UINT64 Attributes
> > > > >
> > > > > + )
> > > > >
> > > > > +{
> > > > >
> > > > > + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported
> > > > > + yet\n", __FUNCTION__));
> > > > >
> > > > > + return EFI_SUCCESS;
> > > > >
> > > > > +}
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Initialize the state information for the CPU Architectural Protocol.
> > > > >
> > > > > +
> > > > >
> > > > > + @param ImageHandle Image handle this driver.
> > > > >
> > > > > + @param SystemTable Pointer to the System Table.
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS Thread can be successfully created
> > > > >
> > > > > + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data
> > > > > + structure
> > > > >
> > > > > + @retval EFI_DEVICE_ERROR Cannot create the thread
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +InitializeCpu (
> > > > >
> > > > > + IN EFI_HANDLE ImageHandle,
> > > > >
> > > > > + IN EFI_SYSTEM_TABLE *SystemTable
> > > > >
> > > > > + )
> > > > >
> > > > > +{
> > > > >
> > > > > + EFI_STATUS Status;
> > > > >
> > > > > + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
> > > > >
> > > > > +
> > > > >
> > > > > + GetFirmwareContextPointer (&FirmwareContext);
> > > > >
> > > > > + ASSERT (FirmwareContext != NULL);
> > > > >
> > > > > + if (FirmwareContext == NULL) {
> > > > >
> > > > > + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of
> > > > > + EFI_RISCV_FIRMWARE_CONTEXT\n"));
> > > > >
> > > > > + return EFI_NOT_FOUND;
> > > > >
> > > > > + }
> > > > >
> > > > > + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n",
> > > > > + __FUNCTION__, FirmwareContext));
> > > > >
> > > > > +
> > > > >
> > > > > + mBootHartId = FirmwareContext->BootHartId;
> > > > >
> > > > > + DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n",
> > > __FUNCTION__,
> > > > > + mBootHartId));
> > > > >
> > > > > +
> > > > >
> > > > > +
> > > > >
> > > > > + InitializeCpuExceptionHandlers(NULL);
> > > > >
> > > > > +
> > > > >
> > > > > + //
> > > > >
> > > > > + // Make sure interrupts are disabled
> > > > >
> > > > > + //
> > > > >
> > > > > + DisableInterrupts ();
> > > > >
> > > > > +
> > > > >
> > > > > + Status = gBS->InstallProtocolInterface (&ImageHandle,
> > > > >
> > > > > +
> > > > > + &gRiscVEfiBootProtocolGuid,
> > > > >
> > > > > + EFI_NATIVE_INTERFACE,
> > > > >
> > > > > + &gRiscvBootProtocol
> > > > >
> > > > > + );
> > > > >
> > > > > +
> > > > >
> > > > > + ASSERT_EFI_ERROR (Status);
> > > > >
> > > > > +
> > > > >
> > > > > + //
> > > > >
> > > > > + // Install CPU Architectural Protocol
> > > > >
> > > > > + //
> > > > >
> > > > > + Status = gBS->InstallMultipleProtocolInterfaces (
> > > > >
> > > > > + &mCpuHandle,
> > > > >
> > > > > + &gEfiCpuArchProtocolGuid,
> > > > >
> > > > > + &gCpu,
> > > > >
> > > > > + NULL
> > > > >
> > > > > + );
> > > > >
> > > > > + ASSERT_EFI_ERROR (Status);
> > > > >
> > > > > + return Status;
> > > > >
> > > > > +}
> > > > >
> > > > > diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > > > b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > > > new file mode 100644
> > > > > index 0000000000..f039759dbd
> > > > > --- /dev/null
> > > > > +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h
> > > > > @@ -0,0 +1,200 @@
> > > > > +/** @file
> > > > >
> > > > > + RISC-V CPU DXE module header file.
> > > > >
> > > > > +
> > > > >
> > > > > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development
> LP.
> > > > > + All rights reserved.<BR>
> > > > >
> > > > > + Copyright (c) 2022, Ventana Micro Systems Inc. All rights
> > > > > + reserved.<BR>
> > > > >
> > > > > +
> > > > >
> > > > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +
> > > > >
> > > > > +#ifndef CPU_DXE_H_
> > > > >
> > > > > +#define CPU_DXE_H_
> > > > >
> > > > > +
> > > > >
> > > > > +#include <PiDxe.h>
> > > > >
> > > > > +
> > > > >
> > > > > +#include <Protocol/Cpu.h>
> > > > >
> > > > > +#include <Protocol/RiscVBootProtocol.h>
> > > > >
> > > > > +#include <Library/RiscVSbiLib.h>
> > > > >
> > > > > +#include <Library/BaseLib.h>
> > > > >
> > > > > +#include <Library/CpuExceptionHandlerLib.h>
> > > > >
> > > > > +#include <Library/DebugLib.h>
> > > > >
> > > > > +#include <Library/UefiBootServicesTableLib.h>
> > > > >
> > > > > +#include <Library/UefiDriverEntryPoint.h>
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Flush CPU data cache. If the instruction cache is fully
> > > > > + coherent
> > > > >
> > > > > + with all DMA operations then function can just return EFI_SUCCESS.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This Protocol instance structure
> > > > >
> > > > > + @param Start Physical address to start flushing from.
> > > > >
> > > > > + @param Length Number of bytes to flush. Round up to
> chipset
> > > > >
> > > > > + granularity.
> > > > >
> > > > > + @param FlushType Specifies the type of flush operation to
> > > perform.
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS If cache was flushed
> > > > >
> > > > > + @retval EFI_UNSUPPORTED If flush type is not supported.
> > > > >
> > > > > + @retval EFI_DEVICE_ERROR If requested range could not be
> flushed.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuFlushCpuDataCache (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > > >
> > > > > + IN EFI_PHYSICAL_ADDRESS Start,
> > > > >
> > > > > + IN UINT64 Length,
> > > > >
> > > > > + IN EFI_CPU_FLUSH_TYPE FlushType
> > > > >
> > > > > + );
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Enables CPU interrupts.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This Protocol instance structure
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS If interrupts were enabled in the CPU
> > > > >
> > > > > + @retval EFI_DEVICE_ERROR If interrupts could not be enabled
> > > > > + on the
> > > CPU.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuEnableInterrupt (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > > > >
> > > > > + );
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Disables CPU interrupts.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This Protocol instance structure
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > > > >
> > > > > + @retval EFI_DEVICE_ERROR If interrupts could not be disabled
> > > > > + on the
> > > CPU.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuDisableInterrupt (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This
> > > > >
> > > > > + );
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Return the state of interrupts.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This Protocol instance structure
> > > > >
> > > > > + @param State Pointer to the CPU's current interrupt state
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS If interrupts were disabled in the CPU.
> > > > >
> > > > > + @retval EFI_INVALID_PARAMETER State is NULL.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuGetInterruptState (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > > >
> > > > > + OUT BOOLEAN *State
> > > > >
> > > > > + );
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Generates an INIT to the CPU.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This Protocol instance structure
> > > > >
> > > > > + @param InitType Type of CPU INIT to perform
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS If CPU INIT occurred. This value should
> never
> > > be
> > > > >
> > > > > + seen.
> > > > >
> > > > > + @retval EFI_DEVICE_ERROR If CPU INIT failed.
> > > > >
> > > > > + @retval EFI_UNSUPPORTED Requested type of CPU INIT not
> > > supported.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuInit (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > > >
> > > > > + IN EFI_CPU_INIT_TYPE InitType
> > > > >
> > > > > + );
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Registers a function to be called from the CPU interrupt handler.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This Protocol instance structure
> > > > >
> > > > > + @param InterruptType Defines which interrupt to hook. IA-32
> > > > >
> > > > > + valid range is 0x00 through
> > > > > + 0xFF
> > > > >
> > > > > + @param InterruptHandler A pointer to a function of type
> > > > >
> > > > > + EFI_CPU_INTERRUPT_HANDLER that
> > > > > + is called
> > > > >
> > > > > + when a processor interrupt occurs.
> > > > > + A null
> > > > >
> > > > > + pointer is an error condition.
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS If handler installed or uninstalled.
> > > > >
> > > > > + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and
> a
> > > > > handler
> > > > >
> > > > > + for InterruptType was previously installed.
> > > > >
> > > > > + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and
> > > > > + a handler for
> > > > >
> > > > > + InterruptType was not previously installed.
> > > > >
> > > > > + @retval EFI_UNSUPPORTED The interrupt specified by
> > > InterruptType
> > > > >
> > > > > + is not supported.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuRegisterInterruptHandler (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > > >
> > > > > + IN EFI_EXCEPTION_TYPE InterruptType,
> > > > >
> > > > > + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
> > > > >
> > > > > + );
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Returns a timer value from one of the CPU's internal timers.
> > > > > + There is no
> > > > >
> > > > > + inherent time interval between ticks but is a function of the
> > > > > + CPU
> > > > > frequency.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This - Protocol instance structure.
> > > > >
> > > > > + @param TimerIndex - Specifies which CPU timer is requested.
> > > > >
> > > > > + @param TimerValue - Pointer to the returned timer value.
> > > > >
> > > > > + @param TimerPeriod - A pointer to the amount of time that
> > > passes
> > > > >
> > > > > + in femtoseconds (10-15) for
> > > > > + each increment
> > > > >
> > > > > + of TimerValue. If TimerValue
> > > > > + does not
> > > > >
> > > > > + increment at a predictable
> > > > > + rate, then 0 is
> > > > >
> > > > > + returned. The amount of time
> > > > > + that has
> > > > >
> > > > > + passed between two calls to
> > > > > + GetTimerValue()
> > > > >
> > > > > + can be calculated with the
> > > > > + formula
> > > > >
> > > > > + (TimerValue2 - TimerValue1) * TimerPeriod.
> > > > >
> > > > > + This parameter is optional and may be NULL.
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS - If the CPU timer count was returned.
> > > > >
> > > > > + @retval EFI_UNSUPPORTED - If the CPU does not have any
> readable
> > > > > timers.
> > > > >
> > > > > + @retval EFI_DEVICE_ERROR - If an error occurred while reading
> the
> > > > > timer.
> > > > >
> > > > > + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or
> > > > > + TimerValue
> > > > > is NULL.
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuGetTimerValue (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > > >
> > > > > + IN UINT32 TimerIndex,
> > > > >
> > > > > + OUT UINT64 *TimerValue,
> > > > >
> > > > > + OUT UINT64 *TimerPeriod OPTIONAL
> > > > >
> > > > > + );
> > > > >
> > > > > +
> > > > >
> > > > > +/**
> > > > >
> > > > > + Set memory cacheability attributes for given range of memeory.
> > > > >
> > > > > +
> > > > >
> > > > > + @param This Protocol instance structure
> > > > >
> > > > > + @param BaseAddress Specifies the start address of the
> > > > >
> > > > > + memory range
> > > > >
> > > > > + @param Length Specifies the length of the memory range
> > > > >
> > > > > + @param Attributes The memory cacheability for the memory
> > > range
> > > > >
> > > > > +
> > > > >
> > > > > + @retval EFI_SUCCESS If the cacheability of that memory range
> is
> > > > >
> > > > > + set successfully
> > > > >
> > > > > + @retval EFI_UNSUPPORTED If the desired operation cannot be
> > > done
> > > > >
> > > > > + @retval EFI_INVALID_PARAMETER The input parameter is not
> > > > > + correct,
> > > > >
> > > > > + such as Length = 0
> > > > >
> > > > > +
> > > > >
> > > > > +**/
> > > > >
> > > > > +EFI_STATUS
> > > > >
> > > > > +EFIAPI
> > > > >
> > > > > +CpuSetMemoryAttributes (
> > > > >
> > > > > + IN EFI_CPU_ARCH_PROTOCOL *This,
> > > > >
> > > > > + IN EFI_PHYSICAL_ADDRESS BaseAddress,
> > > > >
> > > > > + IN UINT64 Length,
> > > > >
> > > > > + IN UINT64 Attributes
> > > > >
> > > > > + );
> > > > >
> > > > > +
> > > > >
> > > > > +#endif
> > > > >
> > > > > --
> > > > > 2.25.1
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2022-09-08 12:02 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
2022-09-06 17:08 ` [RFC PATCH 01/17] MdePkg/Register: Add register definition header files for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 02/17] MdePkg/MdePkg.dec: Add RISCV_EFI_BOOT_PROTOCOL GUID Sunil V L
2022-09-06 17:08 ` [RFC PATCH 03/17] MdePkg/Protocol: Add RiscVBootProtocol.h Sunil V L
2022-09-06 17:08 ` [RFC PATCH 04/17] MdeModulePkg/MdeModulePkg.dec: Add PCD variables for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 05/17] UefiCpuPkg.dec: Add PCD variable " Sunil V L
2022-09-06 17:08 ` [RFC PATCH 06/17] MdePkg/BaseLib: RISC-V: Add generic CPU related functions Sunil V L
2022-09-06 17:08 ` [RFC PATCH 07/17] MdePkg: Add ArchTimerLib library Sunil V L
2022-09-06 17:08 ` [RFC PATCH 08/17] MdePkg: Add RiscVSbiLib Library for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 09/17] UefiCpuPkg/DxeCpuExceptionHandlerLib: Refactor to add other architectures Sunil V L
2022-09-06 17:08 ` [RFC PATCH 10/17] UefiCpuPkg: Add RISC-V support in DxeCpuExceptionHandlerLib Sunil V L
2022-09-06 17:08 ` [RFC PATCH 11/17] MdePkg/Library: Add ResetSystemLib library Sunil V L
2022-09-06 17:08 ` [RFC PATCH 12/17] UefiCpuPkg/SecCore: Add SEC startup code for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 13/17] MdePkg: Add PlatformPeiLib library Sunil V L
2022-09-06 17:08 ` [RFC PATCH 14/17] MdeModulePkg/Universal: Add PlatformPei module for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 15/17] UefiCpuPkg/CpuDxe: Refactor to allow other CPU architectures Sunil V L
2022-09-06 17:08 ` [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module Sunil V L
2022-09-07 9:32 ` Chang, Abner
2022-09-07 11:22 ` Sunil V L
2022-09-07 12:46 ` Chang, Abner
2022-09-08 10:53 ` Sunil V L
2022-09-08 12:02 ` Chang, Abner
2022-09-06 17:08 ` [RFC PATCH 17/17] MdeModulePkg/Universal: Add TimerDxe module Sunil V L
2022-09-07 5:54 ` [edk2-devel] [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Gerd Hoffmann
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox