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charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only - General] Reviewed-by: Abner Chang > -----Original Message----- > From: Abdul Lateef Attar > Sent: Thursday, May 4, 2023 2:39 PM > To: devel@edk2.groups.io > Cc: Attar, AbdulLateef (Abdul Lateef) ; > Grimes, Paul ; Chang, Abner > ; Eric Dong ; Ray Ni > ; Rahul Kumar ; Attar, > AbdulLateef (Abdul Lateef) > Subject: [PATCH v10 5/9] UefiCpuPkg: Implements SmmCpuFeaturesLib for > AMD Family >=20 > From: Abdul Lateef Attar >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4182 >=20 > Implements interfaces to read and write save state registers of AMD's > processor family. > Initializes processor SMMADDR and MASK depends on PcdSmrrEnable flag. > Program or corrects the IP once control returns from SMM. >=20 > Cc: Paul Grimes > Cc: Abner Chang > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Signed-off-by: Abdul Lateef Attar > --- > UefiCpuPkg/UefiCpuPkg.dsc | 7 + > .../AmdSmmCpuFeaturesLib.inf | 38 ++ > .../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c | 445 > ++++++++++++++++++ > 3 files changed, 490 insertions(+) > create mode 100644 > UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > create mode 100644 > UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c >=20 > diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index > 8b0cb02a80e8..6e29850bed17 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dsc > +++ b/UefiCpuPkg/UefiCpuPkg.dsc > @@ -169,6 +169,12 @@ [Components.IA32, Components.X64] > >=20 > SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFea > turesLibStm.inf > } > + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { > + > + FILE_GUID =3D B7242C74-BD21-49EE-84B4-07162E8C080D > + > + > + > SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCp > uFeatur > + esLib.inf > + } > UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf > UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf > UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf > @@ -185,6 +191,7 @@ [Components.IA32, Components.X64] >=20 > UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultRep > ortLib/UnitTestResultReportLibConOut.inf > } > UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf > + UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf >=20 > [Components.X64] >=20 > UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHan > dlerLibUnitTest.inf > diff --git > a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > new file mode 100644 > index 000000000000..fcf6514443d1 > --- /dev/null > +++ > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > @@ -0,0 +1,38 @@ > +## @file > +# The CPU specific programming for PiSmmCpuDxeSmm module. > +# > +# Copyright (c) 2009 - 2016, Intel Corporation. All rights > +reserved.
# Copyright (C) 2023 Advanced Micro Devices, Inc. All > +rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # > +## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D SmmCpuFeaturesLib > + MODULE_UNI_FILE =3D SmmCpuFeaturesLib.uni > + FILE_GUID =3D 5849E964-78EC-428E-8CBD-848A7E35913= 4 > + MODULE_TYPE =3D DXE_SMM_DRIVER > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D SmmCpuFeaturesLib > + CONSTRUCTOR =3D SmmCpuFeaturesLibConstructor > + > +[Sources] > + SmmCpuFeaturesLib.c > + SmmCpuFeaturesLibCommon.c > + AmdSmmCpuFeaturesLib.c > + > +[Packages] > + MdePkg/MdePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + > +[LibraryClasses] > + BaseLib > + PcdLib > + MemoryAllocationLib > + DebugLib > + MmSaveStateLib > + > +[FeaturePcd] > + gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable ## CONSUMES > + gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable ## > CONSUMES > diff --git > a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c > new file mode 100644 > index 000000000000..1473f0a51fe2 > --- /dev/null > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c > @@ -0,0 +1,445 @@ > +/** @file > +Implementation specific to the SmmCpuFeatureLib library instance for > +AMD based platforms. > + > +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
> +Copyright (c) Microsoft Corporation.
Copyright (C) 2023 Advanced > +Micro Devices, Inc. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +// EFER register LMA bit > +#define LMA BIT10 > + > +// Machine Specific Registers (MSRs) > +#define SMMADDR_ADDRESS 0xC0010112ul > +#define SMMMASK_ADDRESS 0xC0010113ul > +#define EFER_ADDRESS 0XC0000080ul > + > +// The mode of the CPU at the time an SMI occurs STATIC UINT8 > +mSmmSaveStateRegisterLma; > + > +/** > + Read an SMM Save State register on the target processor. If this > +function > + returns EFI_UNSUPPORTED, then the caller is responsible for reading > +the > + SMM Save Sate register. > + > + @param[in] CpuIndex The index of the CPU to read the SMM Save State. > The > + value must be between 0 and the NumberOfCpus fie= ld in > + the System Management System Table (SMST). > + @param[in] Register The SMM Save State register to read. > + @param[in] Width The number of bytes to read from the CPU save > state. > + @param[out] Buffer Upon return, this holds the CPU register value r= ead > + from the save state. > + > + @retval EFI_SUCCESS The register was read from Save State. > + @retval EFI_INVALID_PARAMTER Buffer is NULL. > + @retval EFI_UNSUPPORTED This function does not support reading > Register. > + > +**/ > +EFI_STATUS > +EFIAPI > +SmmCpuFeaturesReadSaveStateRegister ( > + IN UINTN CpuIndex, > + IN EFI_SMM_SAVE_STATE_REGISTER Register, > + IN UINTN Width, > + OUT VOID *Buffer > + ) > +{ > + return MmSaveStateReadRegister (CpuIndex, Register, Width, Buffer); } > + > +/** > + Writes an SMM Save State register on the target processor. If this > +function > + returns EFI_UNSUPPORTED, then the caller is responsible for writing > +the > + SMM Save Sate register. > + > + @param[in] CpuIndex The index of the CPU to write the SMM Save State. > The > + value must be between 0 and the NumberOfCpus fiel= d in > + the System Management System Table (SMST). > + @param[in] Register The SMM Save State register to write. > + @param[in] Width The number of bytes to write to the CPU save stat= e. > + @param[in] Buffer Upon entry, this holds the new CPU register value= . > + > + @retval EFI_SUCCESS The register was written to Save State. > + @retval EFI_INVALID_PARAMTER Buffer is NULL. > + @retval EFI_UNSUPPORTED This function does not support writing > Register. > +**/ > +EFI_STATUS > +EFIAPI > +SmmCpuFeaturesWriteSaveStateRegister ( > + IN UINTN CpuIndex, > + IN EFI_SMM_SAVE_STATE_REGISTER Register, > + IN UINTN Width, > + IN CONST VOID *Buffer > + ) > +{ > + return MmSaveStateWriteRegister (CpuIndex, Register, Width, Buffer); > +} > + > +/** > + Performs library initialization. > + > + This initialization function contains common functionality shared > + betwen all library instance constructors. > + > +**/ > +VOID > +CpuFeaturesLibInitialization ( > + VOID > + ) > +{ > + UINT32 LMAValue; > + > + LMAValue =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA= ; > + mSmmSaveStateRegisterLma =3D > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; > + if (LMAValue) { > + mSmmSaveStateRegisterLma =3D > EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; > + } > +} > + > +/** > + Called during the very first SMI into System Management Mode to > +initialize > + CPU features, including SMBASE, for the currently executing CPU. > +Since this > + is the first SMI, the SMRAM Save State Map is at the default address > +of > + AMD_SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. > The currently > +executing > + CPU is specified by CpuIndex and CpuIndex can be used to access > +information > + about the currently executing CPU in the ProcessorInfo array and the > + HotPlugCpuData data structure. > + > + @param[in] CpuIndex The index of the CPU to initialize. The va= lue > + must be between 0 and the NumberOfCpus fiel= d in > + the System Management System Table (SMST). > + @param[in] IsMonarch TRUE if the CpuIndex is the index of the CP= U > that > + was elected as monarch during System Manage= ment > + Mode initialization. > + FALSE if the CpuIndex is not the index of t= he CPU > + that was elected as monarch during System > + Management Mode initialization. > + @param[in] ProcessorInfo Pointer to an array of > EFI_PROCESSOR_INFORMATION > + structures. ProcessorInfo[CpuIndex] contai= ns the > + information for the currently executing CPU= . > + @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA > structure that > + contains the ApidId and SmBase arrays. > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesInitializeProcessor ( > + IN UINTN CpuIndex, > + IN BOOLEAN IsMonarch, > + IN EFI_PROCESSOR_INFORMATION *ProcessorInfo, > + IN CPU_HOT_PLUG_DATA *CpuHotPlugData > + ) > +{ > + AMD_SMRAM_SAVE_STATE_MAP *CpuState; > + UINT32 LMAValue; > + > + // > + // Configure SMBASE. > + // > + CpuState =3D (AMD_SMRAM_SAVE_STATE_MAP > *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); > + CpuState->x64.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; > + > + // Re-initialize the value of mSmmSaveStateRegisterLma flag which > + might have been changed in PiCpuSmmDxeSmm Driver // Entry point, to > make sure correct value on AMD platform is assigned to be used by > SmmCpuFeaturesLib. > + LMAValue =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA= ; > + mSmmSaveStateRegisterLma =3D > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; > + if (LMAValue) { > + mSmmSaveStateRegisterLma =3D > EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; > + } > + > + // > + // If SMRR is supported, then program SMRR base/mask MSRs. > + // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first > normal SMI. > + // The code that initializes SMM environment is running in normal > +mode > + // from SMRAM region. If SMRR is enabled here, then the SMRAM region > + // is protected and the normal mode code execution will fail. > + // > + if (FeaturePcdGet (PcdSmrrEnable)) { > + // > + // SMRR size cannot be less than 4-KBytes > + // SMRR size must be of length 2^n > + // SMRR base alignment cannot be less than SMRR length > + // > + if ((CpuHotPlugData->SmrrSize < SIZE_4KB) || > + (CpuHotPlugData->SmrrSize !=3D GetPowerOfTwo32 (CpuHotPlugData- > >SmrrSize)) || > + ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != =3D > CpuHotPlugData->SmrrBase)) > + { > + // > + // Print message and halt if CPU is Monarch > + // > + if (IsMonarch) { > + DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet > alignment/size requirement!\n")); > + CpuDeadLoop (); > + } > + } else { > + AsmWriteMsr64 (SMMADDR_ADDRESS, CpuHotPlugData->SmrrBase); > + AsmWriteMsr64 (SMMMASK_ADDRESS, ((~(UINT64)(CpuHotPlugData- > >SmrrSize - 1)) | 0x6600)); > + } > + } > +} > + > +/** > + This function updates the SMRAM save state on the currently executing > +CPU > + to resume execution at a specific address after an RSM instruction. > +This > + function must evaluate the SMRAM save state to determine the > +execution mode > + the RSM instruction resumes and update the resume execution address > +with > + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT > +restart > + flag in the SMRAM save state must always be cleared. This function > +returns > + the value of the instruction pointer from the SMRAM save state that > +was > + replaced. If this function returns 0, then the SMRAM save state was > +not > + modified. > + > + This function is called during the very first SMI on each CPU after > + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution > + mode to signal that the SMBASE of each CPU has been updated before > + the default SMBASE address is used for the first SMI to the next CPU. > + > + @param[in] CpuIndex The index of the CPU to hook. The= value > + must be between 0 and the NumberOf= Cpus > + field in the System Management Sys= tem Table > + (SMST). > + @param[in] CpuState Pointer to SMRAM Save State Map fo= r the > + currently executing CPU. > + @param[in] NewInstructionPointer32 Instruction pointer to use if > resuming to > + 32-bit execution mode from 64-bit = SMM. > + @param[in] NewInstructionPointer Instruction pointer to use if resu= ming > to > + same execution mode as SMM. > + > + @retval 0 This function did modify the SMRAM save state. > + @retval > 0 The original instruction pointer value from the SMRAM sav= e > state > + before it was replaced. > +**/ > +UINT64 > +EFIAPI > +SmmCpuFeaturesHookReturnFromSmm ( > + IN UINTN CpuIndex, > + IN SMRAM_SAVE_STATE_MAP *CpuState, > + IN UINT64 NewInstructionPointer32, > + IN UINT64 NewInstructionPointer > + ) > +{ > + UINT64 OriginalInstructionPointer; > + AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState; > + > + AmdCpuState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; > + > + if (mSmmSaveStateRegisterLma =3D=3D > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { > + OriginalInstructionPointer =3D (UINT64)AmdCpuState->x86._EIP; > + AmdCpuState->x86._EIP =3D (UINT32)NewInstructionPointer; > + // > + // Clear the auto HALT restart flag so the RSM instruction returns > + // program control to the instruction following the HLT instruction. > + // > + if ((AmdCpuState->x86.AutoHALTRestart & BIT0) !=3D 0) { > + AmdCpuState->x86.AutoHALTRestart &=3D ~BIT0; > + } > + } else { > + OriginalInstructionPointer =3D AmdCpuState->x64._RIP; > + if ((AmdCpuState->x64.EFER & LMA) =3D=3D 0) { > + AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer32; > + } else { > + AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer; > + } > + > + // > + // Clear the auto HALT restart flag so the RSM instruction returns > + // program control to the instruction following the HLT instruction. > + // > + if ((AmdCpuState->x64.AutoHALTRestart & BIT0) !=3D 0) { > + AmdCpuState->x64.AutoHALTRestart &=3D ~BIT0; > + } > + } > + > + return OriginalInstructionPointer; > +} > + > +/** > + Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is > + returned, then a custom SMI handler is not provided by this library, > + and the default SMI handler must be used. > + > + @retval 0 Use the default SMI handler. > + @retval > 0 Use the SMI handler installed by > SmmCpuFeaturesInstallSmiHandler() > + The caller is required to allocate enough SMRAM for each = CPU to > + support the size of the custom SMI handler. > +**/ > +UINTN > +EFIAPI > +SmmCpuFeaturesGetSmiHandlerSize ( > + VOID > + ) > +{ > + return 0; > +} > + > +/** > + Install a custom SMI handler for the CPU specified by CpuIndex. This > +function > + is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is > +greater > + than zero and is called by the CPU that was elected as monarch during > +System > + Management Mode initialization. > + > + @param[in] CpuIndex The index of the CPU to install the custom SMI > handler. > + The value must be between 0 and the NumberOfCpus= field > + in the System Management System Table (SMST). > + @param[in] SmBase The SMBASE address for the CPU specified by > CpuIndex. > + @param[in] SmiStack The stack to use when an SMI is processed by the > + the CPU specified by CpuIndex. > + @param[in] StackSize The size, in bytes, if the stack used when an SM= I is > + processed by the CPU specified by CpuIndex. > + @param[in] GdtBase The base address of the GDT to use when an SMI i= s > + processed by the CPU specified by CpuIndex. > + @param[in] GdtSize The size, in bytes, of the GDT used when an SMI = is > + processed by the CPU specified by CpuIndex. > + @param[in] IdtBase The base address of the IDT to use when an SMI i= s > + processed by the CPU specified by CpuIndex. > + @param[in] IdtSize The size, in bytes, of the IDT used when an SMI = is > + processed by the CPU specified by CpuIndex. > + @param[in] Cr3 The base address of the page tables to use when = an > SMI > + is processed by the CPU specified by CpuIndex. > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesInstallSmiHandler ( > + IN UINTN CpuIndex, > + IN UINT32 SmBase, > + IN VOID *SmiStack, > + IN UINTN StackSize, > + IN UINTN GdtBase, > + IN UINTN GdtSize, > + IN UINTN IdtBase, > + IN UINTN IdtSize, > + IN UINT32 Cr3 > + ) > +{ > +} > + > +/** > + Determines if MTRR registers must be configured to set SMRAM > +cache-ability > + when executing in System Management Mode. > + > + @retval TRUE MTRR registers must be configured to set SMRAM cache- > ability. > + @retval FALSE MTRR registers do not need to be configured to set > SMRAM > + cache-ability. > +**/ > +BOOLEAN > +EFIAPI > +SmmCpuFeaturesNeedConfigureMtrrs ( > + VOID > + ) > +{ > + return FALSE; > +} > + > +/** > + Disable SMRR register if SMRR is supported and > +SmmCpuFeaturesNeedConfigureMtrrs() > + returns TRUE. > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesDisableSmrr ( > + VOID > + ) > +{ > +} > + > +/** > + Enable SMRR register if SMRR is supported and > +SmmCpuFeaturesNeedConfigureMtrrs() > + returns TRUE. > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesReenableSmrr ( > + VOID > + ) > +{ > +} > + > +/** > + Processor specific hook point each time a CPU enters System Management > Mode. > + > + @param[in] CpuIndex The index of the CPU that has entered SMM. The > value > + must be between 0 and the NumberOfCpus field in t= he > + System Management System Table (SMST). > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesRendezvousEntry ( > + IN UINTN CpuIndex > + ) > +{ > +} > + > +/** > + Returns the current value of the SMM register for the specified CPU. > + If the SMM register is not supported, then 0 is returned. > + > + @param[in] CpuIndex The index of the CPU to read the SMM register. > The > + value must be between 0 and the NumberOfCpus fiel= d in > + the System Management System Table (SMST). > + @param[in] RegName Identifies the SMM register to read. > + > + @return The value of the SMM register specified by RegName from the > CPU > + specified by CpuIndex. > +**/ > +UINT64 > +EFIAPI > +SmmCpuFeaturesGetSmmRegister ( > + IN UINTN CpuIndex, > + IN SMM_REG_NAME RegName > + ) > +{ > + return 0; > +} > + > +/** > + Sets the value of an SMM register on a specified CPU. > + If the SMM register is not supported, then no action is performed. > + > + @param[in] CpuIndex The index of the CPU to write the SMM register. > The > + value must be between 0 and the NumberOfCpus fiel= d in > + the System Management System Table (SMST). > + @param[in] RegName Identifies the SMM register to write. > + registers are read-only. > + @param[in] Value The value to write to the SMM register. > +**/ > +VOID > +EFIAPI > +SmmCpuFeaturesSetSmmRegister ( > + IN UINTN CpuIndex, > + IN SMM_REG_NAME RegName, > + IN UINT64 Value > + ) > +{ > +} > + > +/** > + Check to see if an SMM register is supported by a specified CPU. > + > + @param[in] CpuIndex The index of the CPU to check for SMM register > support. > + The value must be between 0 and the NumberOfCpus = field > + in the System Management System Table (SMST). > + @param[in] RegName Identifies the SMM register to check for support. > + > + @retval TRUE The SMM register specified by RegName is supported by > the CPU > + specified by CpuIndex. > + @retval FALSE The SMM register specified by RegName is not supported > by the > + CPU specified by CpuIndex. > +**/ > +BOOLEAN > +EFIAPI > +SmmCpuFeaturesIsSmmRegisterSupported ( > + IN UINTN CpuIndex, > + IN SMM_REG_NAME RegName > + ) > +{ > + return FALSE; > +} > -- > 2.25.1