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charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only - General] > -----Original Message----- > From: Attar, AbdulLateef (Abdul Lateef) > Sent: Monday, January 16, 2023 12:36 PM > To: Chang, Abner ; devel@edk2.groups.io > Cc: Grimes, Paul ; Kirkendall, Garrett > ; Eric Dong ; Ray Ni > ; Rahul Kumar ; Gerd > Hoffmann > Subject: RE: [edk2-devel] [PATCH v2 4/6] UefiCpuPkg: Implements > SmmSmramSaveStateLib library class >=20 > Hi Abner, >=20 > Please see inline for my reply under [Abdul]. >=20 > Thanks > AbduL > -----Original Message----- > From: Chang, Abner > Sent: 15 January 2023 10:15 > To: devel@edk2.groups.io; Attar, AbdulLateef (Abdul Lateef) > > Cc: Grimes, Paul ; Kirkendall, Garrett > ; Eric Dong ; Ray Ni > ; Rahul Kumar ; Gerd > Hoffmann > Subject: RE: [edk2-devel] [PATCH v2 4/6] UefiCpuPkg: Implements > SmmSmramSaveStateLib library class >=20 > [AMD Official Use Only - General] >=20 > According to the section 4.2.3 in edk2 c coding standard spec in below li= nk, > the processor vendor directory must be under the processor arch directory= . > We use vendor directory because the different implementations of the same > processor arch. > https://tianocore-docs.github.io/edk2- > CCodingStandardsSpecification/draft/edk2-CCodingStandardsSpecification- > draft.pdf > So for this case, we can just have AmdSmramSaveState.c under > SmramSaveStateLib\ according to the file naming defined in 4.3.5.4 becaus= e > this library is only for X86 platform. >=20 >=20 > [Abdul] SmramSaveState.c will be different for Intel's implementation, th= at's > the reason added Amd directory. Hi Abdul, If we were have Intel implementation later, it could be IntelSmramSaveState= .c and IntelSmramSaveStateLib.inf under \SmmSmramSaveStateLib. AMD can stil= l keep it as SmramSaveState.c under \SmmSmramSaveStateLib. Or we can rename= SmramSaveState to AmdSmramSaveState.c (this also conforms to file naming) = and have it under \SmmSmramSaveStateLib. Having SmramSaveState.c under SmmCpuFeatureLib/Amd is not conform to edk2 C= coding standard Directory naming. >=20 > After this patch set is reviewed and merged, we should have another patch > set to update PiSmmCpuDxeSmm to use this library for SMM register access, > remove the one in SmmCpuFeaturelib. Also update OVMF to use > SmmSmramSaveStateLib. Migration SmmSaveState.c under > PiSmmCpuDxeSmm to SmmSmramSaveStateLib for Intel implementation. >=20 > SmmSmramSaveStateLib implementation is AMD processor specific. > I haven't added Intel's implementation, hence cant use this library in > PiSmmCpuDxeSmm until Intel's implementation added. > Same applies to the OVMF. Yes, we can do above after this patch set is addressed. Thanks Abner >=20 > Other comments in below, >=20 > > -----Original Message----- > > From: devel@edk2.groups.io On Behalf Of Abdul > > Lateef Attar via groups.io > > Sent: Wednesday, January 11, 2023 2:16 PM > > To: devel@edk2.groups.io > > Cc: Attar, AbdulLateef (Abdul Lateef) ; > > Grimes, Paul ; Kirkendall, Garrett > > ; Chang, Abner ; > Eric > > Dong ; Ray Ni ; Rahul Kumar > > ; Gerd Hoffmann ; Attar, > > AbdulLateef (Abdul Lateef) > > Subject: [edk2-devel] [PATCH v2 4/6] UefiCpuPkg: Implements > > SmmSmramSaveStateLib library class > > > > Caution: This message originated from an External Source. Use proper > > caution when opening attachments, clicking links, or responding. > > > > > > From: Abdul Lateef Attar > > > > BZ: > > > https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fbugz > > > illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4182&data=3D05%7C01%7Cabner. > > > chang%40amd.com%7C21622ff06cd949cc7e1608daf39b82a2%7C3dd8961fe48 > > > 84e608e11a82d994e183d%7C0%7C0%7C638090146492954852%7CUnknown% > > > 7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW > > > wiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=3DQgHzNdcBkpCNbjGLPfx0L > > Em6ECHYowjuSryyNiWf0ww%3D&reserved=3D0 > > > > Implements SmmSmramSaveStateLib Library class for AMD cpu family. > > > > Cc: Paul Grimes > > Cc: Garrett Kirkendall > > Cc: Abner Chang > > Cc: Eric Dong > > Cc: Ray Ni > > Cc: Rahul Kumar > > Cc: Gerd Hoffmann > > > > Signed-off-by: Abdul Lateef Attar > > --- > > UefiCpuPkg/UefiCpuPkg.dsc | 3 + > > .../AmdSmmSmramSaveStateLib.inf | 28 ++ > > .../SmmSmramSaveStateLib/SmramSaveState.h | 102 ++++++ > > .../SmmSmramSaveStateLib/Amd/SmramSaveState.c | 318 > > ++++++++++++++++++ > > .../SmramSaveStateCommon.c | 124 +++++++ > > 5 files changed, 575 insertions(+) > > create mode 100644 > > > UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib. > > inf > > create mode 100644 > > UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveState.h > > create mode 100644 > > UefiCpuPkg/Library/SmmSmramSaveStateLib/Amd/SmramSaveState.c > > create mode 100644 > > UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveStateCommon.c > > > > diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc > > index f9a46089d2c7..99f7532ce00b 100644 > > --- a/UefiCpuPkg/UefiCpuPkg.dsc > > +++ b/UefiCpuPkg/UefiCpuPkg.dsc > > @@ -2,6 +2,7 @@ > > # UefiCpuPkg Package > > > > # > > > > # Copyright (c) 2007 - 2022, Intel Corporation. All rights > > reserved.
> > > > +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights > > +reserved.
> > > > # > > > > # SPDX-License-Identifier: BSD-2-Clause-Patent > > > > # > > > > @@ -104,6 +105,7 @@ [LibraryClasses.common.DXE_SMM_DRIVER] > > > > > MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMe > > moryAllocationLib.inf > > > > HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf > > > > > > > CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/Smm > > CpuExceptionHandlerLib.inf > > > > + > > + > > > SmmSmramSaveStateLib|UefiCpuPkg/Library/SmmSmramSaveStateLib/Am > > dSmmSmr > > + amSaveStateLib.inf > > > > > > > > [LibraryClasses.common.MM_STANDALONE] > > > > > > > MmServicesTableLib|MdePkg/Library/StandaloneMmServicesTableLib/Stan > > daloneMmServicesTableLib.inf > > > > @@ -191,6 +193,7 @@ [Components.IA32, Components.X64] > > > > > > > > > UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultRep > > ortLib/UnitTestResultReportLibConOut.inf > > > > } > > > > + > > > UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib. > > inf > > > > > > > > [Components.X64] > > > > > > > UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHan > > dlerLibUnitTest.inf > > > > diff --git > > > a/UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLi > > b.inf > > > b/UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLi > > b.inf > > new file mode 100644 > > index 000000000000..463e4c9331be > > --- /dev/null > > +++ > > > b/UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLi > > b.in > > +++ f > > @@ -0,0 +1,28 @@ > > +## @file > > > > +# SMM Smram save state service lib. > > > > +# > > > > +# This is SMM Smram save state service lib that provide service to > > +read and > > > > +# save savestate area registers. > > > > +# > > > > +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights > > +reserved.
> > > > +# > > > > +# SPDX-License-Identifier: BSD-2-Clause-Patent > > > > +# > > > > +## > > > > + > > > > +[Defines] > > > > + INF_VERSION =3D 1.29 > > > > + BASE_NAME =3D AmdSmmSmramSaveStateLib > > > > + FILE_GUID =3D FB7D0A60-E8D4-4EFA-90AA-B357BC569= 879 > > > > + MODULE_TYPE =3D DXE_SMM_DRIVER > > > > + VERSION_STRING =3D 1.0 > > > > + LIBRARY_CLASS =3D SmmSmramSaveStateLib > > > > + > > > > +[Sources] > > > > + SmramSaveState.h > > > > + SmramSaveStateCommon.c > > > > + Amd/SmramSaveState.c > > > > + > > > > +[Packages] > > > > + MdePkg/MdePkg.dec > > > > + UefiCpuPkg/UefiCpuPkg.dec > > > > diff --git > a/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveState.h > > b/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveState.h > > new file mode 100644 > > index 000000000000..c55ae004e016 > > --- /dev/null > > +++ b/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveState.h > > @@ -0,0 +1,102 @@ > > +/** @file > > > > + SMRAM Save State Map header file. > > > > + > > > > + Copyright (c) 2010 - 2019, Intel Corporation. All rights > > + reserved.
> > > > + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights > > + reserved.
> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > > > + > > > > +**/ > > > > + > > > > +#ifndef SMRAM_SAVESTATE_H_ > > > > +#define SMRAM_SAVESTATE_H_ > > > > + > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > + > > > > +// EFER register LMA bit > > > > +#define LMA BIT10 > > > > + > > > > +// Macro used to simplify the lookup table entries of type > > +CPU_SMM_SAVE_STATE_REGISTER_RANGE > > > > +#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 > > +} > > > > + > > > > +#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 2 > > > > + > > > > +// Structure used to describe a range of registers > > > > +typedef struct { > > > > + EFI_SMM_SAVE_STATE_REGISTER Start; > > > > + EFI_SMM_SAVE_STATE_REGISTER End; > > > > + UINTN Length; > > > > +} CPU_SMM_SAVE_STATE_REGISTER_RANGE; > > > > + > > > > +// Structure used to build a lookup table to retrieve the widths and > > +offsets > > > > +// associated with each supported EFI_SMM_SAVE_STATE_REGISTER > value > > > > + > > > > +typedef struct { > > > > + UINT8 Width32; > > > > + UINT8 Width64; > > > > + UINT16 Offset32; > > > > + UINT16 Offset64Lo; > > > > + UINT16 Offset64Hi; > > > > + BOOLEAN Writeable; > > > > +} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY; > > > > + > > > > +/** > > > > + Returns LMA value of the Processor. > > > > + > > > > + @param[in] VOID > > > > + > > > > + @retval UINT8 returns LMA bit value. > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +SmramSaveStateGetRegisterLma ( > > > > + VOID > > > > + ); > > > > + > > > > +/** > > > > + Read information from the CPU save state. > > > > + > > > > + @param Register Specifies the CPU register to read form the save s= tate. > > > > + > > > > + @retval 0 Register is not valid > > > > + @retval >0 Index into mSmmSmramCpuWidthOffset[] associated with > > + Register > > > > + > > > > +**/ > > > > +UINTN > > > > +EFIAPI > > > > +SmramSaveStateGetRegisterIndex ( > > > > + IN EFI_SMM_SAVE_STATE_REGISTER Register > > > > + ); > > > > + > > > > +/** > > > > + Read a CPU Save State register on the target processor. > > > > + > > > > + This function abstracts the differences that whether the CPU Save > > + State register is in the > > > > + IA32 CPU Save State Map or X64 CPU Save State Map. > > > > + > > > > + This function supports reading a CPU Save State register in SMBase > > relocation handler. > > > > + > > > > + @param[in] CpuIndex Specifies the zero-based index of the CPU > save > > state. > > > > + @param[in] RegisterIndex Index into mSmmSmramCpuWidthOffset[] > > look up table. > > > > + @param[in] Width The number of bytes to read from the CPU = save > > state. > > > > + @param[out] Buffer Upon return, this holds the CPU register = value > > read from the save state. > > > > + > > > > + @retval EFI_SUCCESS The register was read from Save State. > > > > + @retval EFI_NOT_FOUND The register is not defined for the Sa= ve > > State of Processor. > > > > + @retval EFI_INVALID_PARAMTER This or Buffer is NULL. > > > > + > > > > +**/ > > > > +EFI_STATUS > > > > +EFIAPI > > > > +SmramSaveStateReadRegisterByIndex ( > > > > + IN UINTN CpuIndex, > > > > + IN UINTN RegisterIndex, > > > > + IN UINTN Width, > > > > + OUT VOID *Buffer > > > > + ); > > > > + > > > > +#endif > > > > diff --git > > a/UefiCpuPkg/Library/SmmSmramSaveStateLib/Amd/SmramSaveState.c > > b/UefiCpuPkg/Library/SmmSmramSaveStateLib/Amd/SmramSaveState.c > > new file mode 100644 > > index 000000000000..af2eeedc71f5 > > --- /dev/null > > +++ > > b/UefiCpuPkg/Library/SmmSmramSaveStateLib/Amd/SmramSaveState.c > > @@ -0,0 +1,318 @@ > > +/** @file > > > > +Provides services to access SMRAM Save State Map > > > > + > > > > +Copyright (c) 2010 - 2019, Intel Corporation. All rights > > +reserved.
> > > > +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights > > +reserved.
> > > > +SPDX-License-Identifier: BSD-2-Clause-Patent > > > > + > > > > +**/ > > > > + > > > > +#include "SmramSaveState.h" > > > > +#include > > > > +#include > > > > + > > > > +#define EFER_ADDRESS 0XC0000080ul > > > > +#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1 > > > > + > > > > +// Macro used to simplify the lookup table entries of type > > +CPU_SMM_SAVE_STATE_LOOKUP_ENTRY > > > > +#define SMM_CPU_OFFSET(Field) OFFSET_OF > > (AMD_SMRAM_SAVE_STATE_MAP, > > +Field) > > > > + > > > > +// Table used by SmramSaveStateGetRegisterIndex() to convert an > > +EFI_SMM_SAVE_STATE_REGISTER > > > > +// value to an index into a table of type > > +CPU_SMM_SAVE_STATE_LOOKUP_ENTRY > > > > +CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE > > mSmmSmramCpuRegisterRanges[] =3D > > +{ > > > > + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, > > + EFI_SMM_SAVE_STATE_REGISTER_LDTINFO), > > > > + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, > > EFI_SMM_SAVE_STATE_REGISTER_RIP), > > > > + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, > > + EFI_SMM_SAVE_STATE_REGISTER_CR4), > > > > + { (EFI_SMM_SAVE_STATE_REGISTER)0, > > (EFI_SMM_SAVE_STATE_REGISTER)0, 0} > > > > +}; > > > > + > > > > +// Lookup table used to retrieve the widths and offsets associated > > +with each > > > > +// supported EFI_SMM_SAVE_STATE_REGISTER value > > > > +CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY > > mSmmSmramCpuWidthOffset[] =3D { > > > > + { 0, 0, 0, 0, = FALSE }, // > > Reserved > > > > + > > > > + // > > > > + // Internally defined CPU Save State Registers. Not defined in PI > > + SMM CPU > > Protocol. > > > > + // > > > > + { 4, 4, SMM_CPU_OFFSET (x86.SMMRevId), SMM_CPU_OFFSET > > (x64.SMMRevId), 0, FALSE}, = // > > SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX =3D 1 > > > > + > > > > + // > > > > + // CPU Save State registers defined in PI SMM CPU Protocol. > > > > + // > > > > + { 4, 8, SMM_CPU_OFFSET (x86.GDTBase), SMM_CPU_OFFSET > > (x64._GDTRBaseLoDword), SMM_CPU_OFFSET (x64._GDTRBaseHiDword), > > FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE =3D 4 > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._IDTRBase= LoDword), > > SMM_CPU_OFFSET (x64._IDTRBaseLoDword), FALSE}, // > > EFI_SMM_SAVE_STATE_REGISTER_IDTBASE =3D 5 > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._LDTRBase= LoDword), > > SMM_CPU_OFFSET (x64._LDTRBaseLoDword), FALSE}, // > > EFI_SMM_SAVE_STATE_REGISTER_LDTBASE =3D 6 > > > > + { 0, 2, 0, SMM_CPU_OFFSET (x64._GDTRLimi= t), 0, FALSE}, > > // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT =3D 7 > > > > + { 0, 2, 0, SMM_CPU_OFFSET (x64._IDTRLimi= t), 0, FALSE}, > > // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT =3D 8 > > > > + { 0, 4, 0, SMM_CPU_OFFSET (x64._LDTRLimi= t), 0, FALSE}, > > // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT =3D 9 > > > > + { 0, 0, 0, 0, = 0, FALSE}, > // > > EFI_SMM_SAVE_STATE_REGISTER_LDTINFO =3D 10 > > > > + { 4, 2, SMM_CPU_OFFSET (x86._ES), SMM_CPU_OFFSET (x64._ES), > > 0, FALSE}, // EFI_SMM_SAVE_STAT= E_REGISTER_ES =3D > > 20 > > > > + { 4, 2, SMM_CPU_OFFSET (x86._CS), SMM_CPU_OFFSET (x64._CS), > > 0, FALSE}, // EFI_SMM_SAVE_STAT= E_REGISTER_CS =3D > > 21 > > > > + { 4, 2, SMM_CPU_OFFSET (x86._SS), SMM_CPU_OFFSET (x64._SS), > > 0, FALSE}, // EFI_SMM_SAVE_STAT= E_REGISTER_SS =3D > > 22 > > > > + { 4, 2, SMM_CPU_OFFSET (x86._DS), SMM_CPU_OFFSET (x64._DS), > > 0, FALSE}, // EFI_SMM_SAVE_STAT= E_REGISTER_DS > =3D > > 23 > > > > + { 4, 2, SMM_CPU_OFFSET (x86._FS), SMM_CPU_OFFSET (x64._FS), > > 0, FALSE}, // EFI_SMM_SAVE_STAT= E_REGISTER_FS =3D > > 24 > > > > + { 4, 2, SMM_CPU_OFFSET (x86._GS), SMM_CPU_OFFSET (x64._GS), > > 0, FALSE}, // EFI_SMM_SAVE_STAT= E_REGISTER_GS > =3D > > 25 > > > > + { 0, 2, 0, SMM_CPU_OFFSET (x64._LDTR), = 0, FALSE}, > > // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL =3D 26 > > > > + { 0, 2, 0, SMM_CPU_OFFSET (x64._TR), = 0, FALSE}, > > // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL =3D 27 > > > > + { 4, 8, SMM_CPU_OFFSET (x86._DR7), SMM_CPU_OFFSET (x64._DR7), > > SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // > > EFI_SMM_SAVE_STATE_REGISTER_DR7 =3D 28 > > > > + { 4, 8, SMM_CPU_OFFSET (x86._DR6), SMM_CPU_OFFSET (x64._DR6), > > SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // > > EFI_SMM_SAVE_STATE_REGISTER_DR6 =3D 29 > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R8), > > SMM_CPU_OFFSET (x64._R8) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_R8 =3D 30 > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R9), > > SMM_CPU_OFFSET (x64._R9) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_R9 =3D 31 > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R10), > > SMM_CPU_OFFSET (x64._R10) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_R10 =3D 32 > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R11), > > SMM_CPU_OFFSET (x64._R11) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_R11 =3D 33 > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R12), > > SMM_CPU_OFFSET (x64._R12) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_R12 =3D 34 > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R13), > > SMM_CPU_OFFSET (x64._R13) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_R13 =3D 35 > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R14), > > SMM_CPU_OFFSET (x64._R14) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_R14 =3D 36 > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._R15), > > SMM_CPU_OFFSET (x64._R15) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_R15 =3D 37 > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EAX), SMM_CPU_OFFSET (x64._RAX), > > SMM_CPU_OFFSET (x64._RAX) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_RAX =3D 38 > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EBX), SMM_CPU_OFFSET (x64._RBX), > > SMM_CPU_OFFSET (x64._RBX) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_RBX =3D 39 > > > > + { 4, 8, SMM_CPU_OFFSET (x86._ECX), SMM_CPU_OFFSET (x64._RCX), > > SMM_CPU_OFFSET (x64._RCX) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_RBX =3D 39 > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EDX), SMM_CPU_OFFSET (x64._RDX), > > SMM_CPU_OFFSET (x64._RDX) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_RDX =3D 41 > > > > + { 4, 8, SMM_CPU_OFFSET (x86._ESP), SMM_CPU_OFFSET (x64._RSP), > > SMM_CPU_OFFSET (x64._RSP) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_RSP =3D 42 > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EBP), SMM_CPU_OFFSET (x64._RBP), > > SMM_CPU_OFFSET (x64._RBP) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_RBP =3D 43 > > > > + { 4, 8, SMM_CPU_OFFSET (x86._ESI), SMM_CPU_OFFSET (x64._RSI), > > SMM_CPU_OFFSET (x64._RSI) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_RSI =3D 44 > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EDI), SMM_CPU_OFFSET (x64._RDI), > > SMM_CPU_OFFSET (x64._RDI) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_RDI =3D 45 > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EIP), SMM_CPU_OFFSET (x64._RIP), > > SMM_CPU_OFFSET (x64._RIP) + 4, TRUE}, // > > EFI_SMM_SAVE_STATE_REGISTER_RIP =3D 46 > > > > + > > > > + { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS), SMM_CPU_OFFSET > > (x64._RFLAGS), SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE}, = // > > EFI_SMM_SAVE_STATE_REGISTER_RFLAGS =3D 51 > > > > + { 4, 8, SMM_CPU_OFFSET (x86._CR0), SMM_CPU_OFFSET (x64._CR0), > > SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // > > EFI_SMM_SAVE_STATE_REGISTER_CR0 =3D 52 > > > > + { 4, 8, SMM_CPU_OFFSET (x86._CR3), SMM_CPU_OFFSET (x64._CR3), > > SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // > > EFI_SMM_SAVE_STATE_REGISTER_CR3 =3D 53 > > > > + { 0, 8, 0, SMM_CPU_OFFSET (x64._CR4), > > SMM_CPU_OFFSET (x64._CR4) + 4, FALSE}, // > > EFI_SMM_SAVE_STATE_REGISTER_CR4 =3D 54 > > > > + { 0, 0, 0, 0, = 0 } > > > > +}; > > > > + > > > > +/** > > > > + Read an SMM Save State register on the target processor. If this > > + function > > > > + returns EFI_UNSUPPORTED, then the caller is responsible for reading > > + the > > > > + SMM Save Sate register. > > > > + > > > > + @param[in] CpuIndex The index of the CPU to read the SMM Save > > + State. The > > > > + value must be between 0 and the NumberOfCpus > > + field in > > > > + the System Management System Table (SMST). > > > > + @param[in] Register The SMM Save State register to read. > > > > + @param[in] Width The number of bytes to read from the CPU save > > state. > > > > + @param[out] Buffer Upon return, this holds the CPU register value > read > > > > + from the save state. > > > > + > > > > + @retval EFI_SUCCESS The register was read from Save State. > > > > + @retval EFI_INVALID_PARAMTER Buffer is NULL. > > > > + @retval EFI_UNSUPPORTED This function does not support reading > EFI_NOT_FOUND is missed. > [Abdul] will make the changes. > > Register. > > > > + > > > > +**/ > > > > +EFI_STATUS > > > > +EFIAPI > > > > +SmramSaveStateReadRegister ( > > > > + IN UINTN CpuIndex, > > > > + IN EFI_SMM_SAVE_STATE_REGISTER Register, > > > > + IN UINTN Width, > > > > + OUT VOID *Buffer > > > > + ) > > > > +{ > > > > + UINT32 SmmRevId; > > > > + EFI_SMM_SAVE_STATE_IO_INFO *IoInfo; > > > > + AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState; > > > > + UINT8 DataWidth; > > > > + > > > > + // Read CPU State > > > > + CpuSaveState =3D (AMD_SMRAM_SAVE_STATE_MAP > > + *)gSmst->CpuSaveState[CpuIndex]; > > > > + > > > > + // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA > > > > + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA) { > > > > + // Only byte access is supported for this register > > > > + if (Width !=3D 1) { > > > > + return EFI_INVALID_PARAMETER; > > > > + } > > > > + > > > > + *(UINT8 *)Buffer =3D SmramSaveStateGetRegisterLma (); > > > > + > > > > + return EFI_SUCCESS; > > > > + } > > > > + > > > > + // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO > > > > + > > > > + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_IO) { > > > > + // > > > > + // Get SMM Revision ID > > > > + // > > > > + SmramSaveStateReadRegisterByIndex (CpuIndex, > > + SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), > > &SmmRevId); > > > > + > > > > + // > > > > + // See if the CPU supports the IOMisc register in the save state > > > > + // > > > > + if (SmmRevId < AMD_SMM_MIN_REV_ID_X64) { > > > > + return EFI_NOT_FOUND; > > > > + } > > > > + > > > > + // Check if IO Restart Dword [IO Trap] is valid or not using bit 1= . > > > > + if (!(CpuSaveState->x64.IO_DWord & 0x02u)) { > > > > + return EFI_NOT_FOUND; > > > > + } > > > > + > > > > + // Zero the IoInfo structure that will be returned in Buffer > > > > + IoInfo =3D (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer; > > > > + ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO)); > > > > + > > > > + IoInfo->IoPort =3D (UINT16)(CpuSaveState->x64.IO_DWord >> 16u); > > > > + > > > > + if (CpuSaveState->x64.IO_DWord & 0x10u) { > > > > + IoInfo->IoWidth =3D EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8; > > > > + DataWidth =3D 0x01u; > > > > + } else if (CpuSaveState->x64.IO_DWord & 0x20u) { > > > > + IoInfo->IoWidth =3D EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16; > > > > + DataWidth =3D 0x02u; > > > > + } else { > > > > + IoInfo->IoWidth =3D EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32; > > > > + DataWidth =3D 0x04u; > > > > + } > > > > + > > > > + if (CpuSaveState->x64.IO_DWord & 0x01u) { > > > > + IoInfo->IoType =3D EFI_SMM_SAVE_STATE_IO_TYPE_INPUT; > > > > + } else { > > > > + IoInfo->IoType =3D EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT; > > > > + } > > > > + > > > > + if ((IoInfo->IoType =3D=3D EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) || > > + (IoInfo->IoType =3D=3D EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT)) { > > > > + SmramSaveStateReadRegister (CpuIndex, > > + EFI_SMM_SAVE_STATE_REGISTER_RAX, DataWidth, &IoInfo->IoData); > > > > + } > > > > + > > > > + return EFI_SUCCESS; > > > > + } > > > > + > > > > + // Convert Register to a register lookup table index > > > > + return SmramSaveStateReadRegisterByIndex (CpuIndex, > > + SmramSaveStateGetRegisterIndex (Register), Width, Buffer); > > > > +} > > > > + > > > > +/** > > > > + Writes an SMM Save State register on the target processor. If this > > + function > > > > + returns EFI_UNSUPPORTED, then the caller is responsible for writing > > + the > > > > + SMM Save Sate register. > > > > + > > > > + @param[in] CpuIndex The index of the CPU to write the SMM Save > > + State. The > > > > + value must be between 0 and the NumberOfCpus > > + field in > > > > + the System Management System Table (SMST). > > > > + @param[in] Register The SMM Save State register to write. > > > > + @param[in] Width The number of bytes to write to the CPU save st= ate. > > > > + @param[in] Buffer Upon entry, this holds the new CPU register val= ue. > > > > + > > > > + @retval EFI_SUCCESS The register was written to Save State= . > > > > + @retval EFI_INVALID_PARAMTER Buffer is NULL. > > > > + @retval EFI_UNSUPPORTED This function does not support writing >=20 > EFI_NOT_FOUND is missed. > Thanks > Abner > [Abdul] will make the changes. > > Register. > > > > +**/ > > > > +EFI_STATUS > > > > +EFIAPI > > > > +SmramSaveStateWriteRegister ( > > > > + IN UINTN CpuIndex, > > > > + IN EFI_SMM_SAVE_STATE_REGISTER Register, > > > > + IN UINTN Width, > > > > + IN CONST VOID *Buffer > > > > + ) > > > > +{ > > > > + UINTN RegisterIndex; > > > > + AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState; > > > > + > > > > + // > > > > + // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored > > > > + // > > > > + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA) { > > > > + return EFI_SUCCESS; > > > > + } > > > > + > > > > + // > > > > + // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported > > > > + // > > > > + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_IO) { > > > > + return EFI_NOT_FOUND; > > > > + } > > > > + > > > > + // > > > > + // Convert Register to a register lookup table index > > > > + // > > > > + RegisterIndex =3D SmramSaveStateGetRegisterIndex (Register); > > > > + if (RegisterIndex =3D=3D 0) { > > > > + return EFI_NOT_FOUND; > > > > + } > > > > + > > > > + CpuSaveState =3D gSmst->CpuSaveState[CpuIndex]; > > > > + > > > > + // > > > > + // Do not write non-writable SaveState, because it will cause except= ion. > > > > + // > > > > + if (!mSmmSmramCpuWidthOffset[RegisterIndex].Writeable) { > > > > + return EFI_UNSUPPORTED; > > > > + } > > > > + > > > > + // > > > > + // Check CPU mode > > > > + // > > > > + if (SmramSaveStateGetRegisterLma () =3D=3D > > + EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { > > > > + // > > > > + // If 32-bit mode width is zero, then the specified register can > > + not be accessed > > > > + // > > > > + if (mSmmSmramCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { > > > > + return EFI_NOT_FOUND; > > > > + } > > > > + > > > > + // > > > > + // If Width is bigger than the 32-bit mode width, then the > > + specified register can not be accessed > > > > + // > > > > + if (Width > mSmmSmramCpuWidthOffset[RegisterIndex].Width32) { > > > > + return EFI_INVALID_PARAMETER; > > > > + } > > > > + > > > > + // > > > > + // Write SMM State register > > > > + // > > > > + ASSERT (CpuSaveState !=3D NULL); > > > > + CopyMem ((UINT8 *)CpuSaveState + > > + mSmmSmramCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width); > > > > + } else { > > > > + // > > > > + // If 64-bit mode width is zero, then the specified register can > > + not be accessed > > > > + // > > > > + if (mSmmSmramCpuWidthOffset[RegisterIndex].Width64 =3D=3D 0) { > > > > + return EFI_NOT_FOUND; > > > > + } > > > > + > > > > + // > > > > + // If Width is bigger than the 64-bit mode width, then the > > + specified register can not be accessed > > > > + // > > > > + if (Width > mSmmSmramCpuWidthOffset[RegisterIndex].Width64) { > > > > + return EFI_INVALID_PARAMETER; > > > > + } > > > > + > > > > + // > > > > + // Write lower 32-bits of SMM State register > > > > + // > > > > + CopyMem ((UINT8 *)CpuSaveState + > > + mSmmSmramCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, > > + Width)); > > > > + if (Width >=3D 4) { > > > > + // > > > > + // Write upper 32-bits of SMM State register > > > > + // > > > > + CopyMem ((UINT8 *)CpuSaveState + > > + mSmmSmramCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 > *)Buffer > > + > > + 4, Width - 4); > > > > + } > > > > + } > > > > + > > > > + return EFI_SUCCESS; > > > > +} > > > > + > > > > +/** > > > > + Returns LMA value of the Processor. > > > > + > > > > + @param[in] VOID > > > > + > > > > + @retval UINT8 returns LMA bit value. > > > > +**/ > > > > +UINT8 > > > > +EFIAPI > > > > +SmramSaveStateGetRegisterLma ( > > > > + VOID > > > > + ) > > > > +{ > > > > + UINT32 LMAValue; > > > > + > > > > + LMAValue =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; > > > > + if (LMAValue) { > > > > + return EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; > > > > + } > > > > + > > > > + return EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; > > > > +} > > > > diff --git > > > a/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveStateCommon.c > > > b/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveStateCommon.c > > new file mode 100644 > > index 000000000000..98e89f9eec3f > > --- /dev/null > > +++ > > > b/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveStateCommon.c > > @@ -0,0 +1,124 @@ > > +/** @file > > > > + Provides common supporting function to access SMRAM Save State Map > > > > + > > > > + Copyright (c) 2010 - 2019, Intel Corporation. All rights > > + reserved.
> > > > + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights > > + reserved.
> > > > + > > > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > > > + > > > > +**/ > > > > + > > > > +#include "SmramSaveState.h" > > > > + > > > > +extern CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE > > +mSmmSmramCpuRegisterRanges[]; > > > > +extern CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY > > mSmmSmramCpuWidthOffset[]; > > > > + > > > > +/** > > > > + Read information from the CPU save state. > > > > + > > > > + @param Register Specifies the CPU register to read form the save s= tate. > > > > + > > > > + @retval 0 Register is not valid > > > > + @retval >0 Index into mSmmSmramCpuWidthOffset[] associated with > > + Register > > > > + > > > > +**/ > > > > +UINTN > > > > +EFIAPI > > > > +SmramSaveStateGetRegisterIndex ( > > > > + IN EFI_SMM_SAVE_STATE_REGISTER Register > > > > + ) > > > > +{ > > > > + UINTN Index; > > > > + UINTN Offset; > > > > + > > > > + for (Index =3D 0, Offset =3D SMM_SAVE_STATE_REGISTER_MAX_INDEX; > > + mSmmSmramCpuRegisterRanges[Index].Length !=3D 0; Index++) { > > > > + if ((Register >=3D mSmmSmramCpuRegisterRanges[Index].Start) && > > + (Register <=3D mSmmSmramCpuRegisterRanges[Index].End)) { > > > > + return Register - mSmmSmramCpuRegisterRanges[Index].Start + > > + Offset; > > > > + } > > > > + > > > > + Offset +=3D mSmmSmramCpuRegisterRanges[Index].Length; > > > > + } > > > > + > > > > + return 0; > > > > +} > > > > + > > > > +/** > > > > + Read a CPU Save State register on the target processor. > > > > + > > > > + This function abstracts the differences that whether the CPU Save > > + State register is in the > > > > + IA32 CPU Save State Map or X64 CPU Save State Map. > > > > + > > > > + This function supports reading a CPU Save State register in SMBase > > relocation handler. > > > > + > > > > + @param[in] CpuIndex Specifies the zero-based index of the CPU > save > > state. > > > > + @param[in] RegisterIndex Index into mSmmSmramCpuWidthOffset[] > > look up table. > > > > + @param[in] Width The number of bytes to read from the CPU = save > > state. > > > > + @param[out] Buffer Upon return, this holds the CPU register = value > > read from the save state. > > > > + > > > > + @retval EFI_SUCCESS The register was read from Save State. > > > > + @retval EFI_NOT_FOUND The register is not defined for the Sa= ve > > State of Processor. > > > > + @retval EFI_INVALID_PARAMTER This or Buffer is NULL. > > > > + > > > > +**/ > > > > +EFI_STATUS > > > > +EFIAPI > > > > +SmramSaveStateReadRegisterByIndex ( > > > > + IN UINTN CpuIndex, > > > > + IN UINTN RegisterIndex, > > > > + IN UINTN Width, > > > > + OUT VOID *Buffer > > > > + ) > > > > +{ > > > > + if (RegisterIndex =3D=3D 0) { > > > > + return EFI_NOT_FOUND; > > > > + } > > > > + > > > > + if (SmramSaveStateGetRegisterLma () =3D=3D > > + EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { > > > > + // > > > > + // If 32-bit mode width is zero, then the specified register can > > + not be accessed > > > > + // > > > > + if (mSmmSmramCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { > > > > + return EFI_NOT_FOUND; > > > > + } > > > > + > > > > + // > > > > + // If Width is bigger than the 32-bit mode width, then the > > + specified register can not be accessed > > > > + // > > > > + if (Width > mSmmSmramCpuWidthOffset[RegisterIndex].Width32) { > > > > + return EFI_INVALID_PARAMETER; > > > > + } > > > > + > > > > + // > > > > + // Write return buffer > > > > + // > > > > + ASSERT (gSmst->CpuSaveState[CpuIndex] !=3D NULL); > > > > + CopyMem (Buffer, (UINT8 *)gSmst->CpuSaveState[CpuIndex] + > > + mSmmSmramCpuWidthOffset[RegisterIndex].Offset32, Width); > > > > + } else { > > > > + // > > > > + // If 64-bit mode width is zero, then the specified register can > > + not be accessed > > > > + // > > > > + if (mSmmSmramCpuWidthOffset[RegisterIndex].Width64 =3D=3D 0) { > > > > + return EFI_NOT_FOUND; > > > > + } > > > > + > > > > + // > > > > + // If Width is bigger than the 64-bit mode width, then the > > + specified register can not be accessed > > > > + // > > > > + if (Width > mSmmSmramCpuWidthOffset[RegisterIndex].Width64) { > > > > + return EFI_INVALID_PARAMETER; > > > > + } > > > > + > > > > + // > > > > + // Write lower 32-bits of return buffer > > > > + // > > > > + CopyMem (Buffer, (UINT8 *)gSmst->CpuSaveState[CpuIndex] + > > + mSmmSmramCpuWidthOffset[RegisterIndex].Offset64Lo, MIN (4, > Width)); > > > > + if (Width >=3D 4) { > > > > + // > > > > + // Write upper 32-bits of return buffer > > > > + // > > > > + CopyMem ((UINT8 *)Buffer + 4, (UINT8 > > + *)gSmst->CpuSaveState[CpuIndex] + > > + mSmmSmramCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4); > > > > + } > > > > + } > > > > + > > > > + return EFI_SUCCESS; > > > > +} > > > > -- > > 2.25.1 > > > > > > > >=20 > >