Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V4 12/34] OvmfPkg/PlatformPei: Add support for RISC-V

["Chang, Abner" <abner.chang@amd.com>]

[AMD Official Use Only - General]

Acked-by: Abner Chang <abner.chang@amd.com>

However, this one has the dependency with 11/34.

> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Sunil V L
> via groups.io
> Sent: Saturday, October 15, 2022 12:48 AM
> To: devel@edk2.groups.io
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Jiewen Yao
> <jiewen.yao@intel.com>; Jordan Justen <jordan.l.justen@intel.com>; Gerd
> Hoffmann <kraxel@redhat.com>; Daniel Schaefer <git@danielschaefer.me>
> Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V4 12/34]
> OvmfPkg/PlatformPei: Add support for RISC-V
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> REF:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076&amp;data=05%7C01%7Ca
> bner.chang%40amd.com%7C662b4bb7c3d84c49a42608daae042cf8%7C3dd89
> 61fe4884e608e11a82d994e183d%7C0%7C0%7C638013630213202640%7CUnkn
> own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=iJgba94hHBMT4
> 8Z90bBpSh7wNuJtGQbtRgjk0mOyVlk%3D&amp;reserved=0
> 
> This is mostly copied from
> edk2-platforms/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei
> 
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Daniel Schaefer <git@danielschaefer.me>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  OvmfPkg/PlatformPei/PlatformPei.inf     |   9 +
>  OvmfPkg/PlatformPei/RiscV64/Platform.h  |  97 +++++
>  OvmfPkg/PlatformPei/RiscV64/Fv.c        |  81 +++++
>  OvmfPkg/PlatformPei/RiscV64/MemDetect.c | 212 +++++++++++
> OvmfPkg/PlatformPei/RiscV64/Platform.c  | 372 ++++++++++++++++++++
>  5 files changed, 771 insertions(+)
> 
> diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf
> b/OvmfPkg/PlatformPei/PlatformPei.inf
> index c637f621cb1f..5d873c34ca67 100644
> --- a/OvmfPkg/PlatformPei/PlatformPei.inf
> +++ b/OvmfPkg/PlatformPei/PlatformPei.inf
> @@ -33,6 +33,12 @@ [Sources.IA32, Sources.X64]
>    Ia32X64/Platform.h
>    Ia32X64/IntelTdx.c
> 
> +[Sources.RISCV64]
> +  RiscV64/Fv.c
> +  RiscV64/MemDetect.c
> +  RiscV64/Platform.c
> +  RiscV64/Platform.h
> +
>  [Packages]
>    EmbeddedPkg/EmbeddedPkg.dec
>    MdePkg/MdePkg.dec
> @@ -68,6 +74,9 @@ [LibraryClasses.IA32, LibraryClasses.X64]
>    QemuFwCfgSimpleParserLib
>    MemEncryptSevLib
> 
> +[LibraryClasses.RISCV64]
> +  RiscVSbiLib
> +
>  [Pcd]
>    gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase
>    gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize
> diff --git a/OvmfPkg/PlatformPei/RiscV64/Platform.h
> b/OvmfPkg/PlatformPei/RiscV64/Platform.h
> new file mode 100644
> index 000000000000..6c23c722a360
> --- /dev/null
> +++ b/OvmfPkg/PlatformPei/RiscV64/Platform.h
> @@ -0,0 +1,97 @@
> +/** @file
> +  Platform PEI module include file.
> +
> +  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> + rights reserved.<BR>  Copyright (c) 2006 - 2014, Intel Corporation.
> + All rights reserved.<BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef PLATFORM_PEI_H_INCLUDED_
> +#define PLATFORM_PEI_H_INCLUDED_
> +
> +VOID
> +AddIoMemoryBaseSizeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  UINT64                MemorySize
> +  );
> +
> +VOID
> +AddIoMemoryRangeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  EFI_PHYSICAL_ADDRESS  MemoryLimit
> +  );
> +
> +VOID
> +AddMemoryBaseSizeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  UINT64                MemorySize
> +  );
> +
> +VOID
> +AddMemoryRangeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  EFI_PHYSICAL_ADDRESS  MemoryLimit
> +  );
> +
> +VOID
> +AddUntestedMemoryBaseSizeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  UINT64                MemorySize
> +  );
> +
> +VOID
> +AddReservedMemoryBaseSizeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  UINT64                MemorySize
> +  );
> +
> +VOID
> +AddUntestedMemoryRangeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  EFI_PHYSICAL_ADDRESS  MemoryLimit
> +  );
> +
> +VOID
> +AddressWidthInitialization (
> +  VOID
> +  );
> +
> +EFI_STATUS
> +PublishPeiMemory (
> +  VOID
> +  );
> +
> +UINT32
> +GetSystemMemorySizeBelow4gb (
> +  VOID
> +  );
> +
> +VOID
> +InitializeRamRegions (
> +  VOID
> +  );
> +
> +EFI_STATUS
> +PeiFvInitialization (
> +  VOID
> +  );
> +
> +EFI_STATUS
> +InitializeXen (
> +  VOID
> +  );
> +
> +/**
> +  Build processor and platform information for the U5 platform
> +
> +  @return EFI_SUCCESS     Status.
> +
> +**/
> +EFI_STATUS
> +BuildRiscVSmbiosHobs (
> +  VOID
> +  );
> +
> +#endif // _PLATFORM_PEI_H_INCLUDED_
> diff --git a/OvmfPkg/PlatformPei/RiscV64/Fv.c
> b/OvmfPkg/PlatformPei/RiscV64/Fv.c
> new file mode 100644
> index 000000000000..ff99c1432935
> --- /dev/null
> +++ b/OvmfPkg/PlatformPei/RiscV64/Fv.c
> @@ -0,0 +1,81 @@
> +/** @file
> +  Build FV related hobs for platform.
> +
> +  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> + rights reserved.<BR>  Copyright (c) 2006 - 2013, Intel Corporation.
> + All rights reserved.<BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "PiPei.h"
> +#include "Platform.h"
> +#include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PeiServicesLib.h>
> +
> +/**
> +  Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
> +  and DXE know about them.
> +
> +  @retval EFI_SUCCESS   Platform PEI FVs were initialized successfully.
> +
> +**/
> +EFI_STATUS
> +PeiFvInitialization (
> +  VOID
> +  )
> +{
> +  DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume
> +Initialization\n"));
> +
> +  // Create a memory allocation HOB for the DXE FV.
> +  //
> +  // If "secure" S3 is needed, then SEC will decompress both PEI and
> + DXE  // firmware volumes at S3 resume too, hence we need to keep away
> + the OS from  // DXEFV as well. Otherwise we only need to keep away DXE
> + itself from the  // DXEFV area.
> +  //
> +  BuildMemoryAllocationHob (
> +    PcdGet32 (PcdOvmfPeiMemFvBase),
> +    PcdGet32 (PcdOvmfPeiMemFvSize),
> +    EfiBootServicesData
> +    );
> +
> +  //
> +  // Let DXE know about the DXE FV
> +  //
> +  BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32
> + (PcdOvmfDxeMemFvSize));  DEBUG ((
> +    DEBUG_INFO,
> +    "Platform builds DXE FV at %x, size %x.\n",
> +    PcdGet32 (PcdOvmfDxeMemFvBase),
> +    PcdGet32 (PcdOvmfDxeMemFvSize)
> +    ));
> +
> +  // Create a memory allocation HOB for the DXE FV.
> +  //
> +  // If "secure" S3 is needed, then SEC will decompress both PEI and
> + DXE  // firmware volumes at S3 resume too, hence we need to keep away
> + the OS from  // DXEFV as well. Otherwise we only need to keep away DXE
> + itself from the  // DXEFV area.
> +  //
> +  BuildMemoryAllocationHob (
> +    PcdGet32 (PcdOvmfDxeMemFvBase),
> +    PcdGet32 (PcdOvmfDxeMemFvSize),
> +    EfiBootServicesData
> +    );
> +
> +  //
> +  // Let PEI know about the DXE FV so it can find the DXE Core  //
> + PeiServicesInstallFvInfoPpi (
> +    NULL,
> +    (VOID *)(UINTN)PcdGet32 (PcdOvmfDxeMemFvBase),
> +    PcdGet32 (PcdOvmfDxeMemFvSize),
> +    NULL,
> +    NULL
> +    );
> +
> +  return EFI_SUCCESS;
> +}
> diff --git a/OvmfPkg/PlatformPei/RiscV64/MemDetect.c
> b/OvmfPkg/PlatformPei/RiscV64/MemDetect.c
> new file mode 100644
> index 000000000000..eb9d24581f8d
> --- /dev/null
> +++ b/OvmfPkg/PlatformPei/RiscV64/MemDetect.c
> @@ -0,0 +1,212 @@
> +/** @file
> +  Memory Detection for Virtual Machines.
> +
> +  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All
> + rights reserved.<BR>  Copyright (c) 2006 - 2014, Intel Corporation.
> + All rights reserved.<BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +Module Name:
> +
> +  MemDetect.c
> +
> +**/
> +
> +//
> +// The package level header files this module uses // #include
> +<PiPei.h>
> +
> +//
> +// The Library classes this module consumes // #include
> +<Library/BaseMemoryLib.h> #include <Library/DebugLib.h> #include
> +<Library/HobLib.h> #include <Library/IoLib.h> #include
> +<Library/PcdLib.h> #include <Library/PeimEntryPoint.h> #include
> +<Library/ResourcePublicationLib.h>
> +#include <Library/BaseRiscVSbiLib.h>
> +
> +#include <libfdt.h>
> +
> +#include <Guid/FdtHob.h>
> +
> +#include "Platform.h"
> +
> +STATIC EFI_PHYSICAL_ADDRESS  SystemMemoryBase;
> +STATIC UINT64                SystemMemorySize;
> +STATIC EFI_PHYSICAL_ADDRESS  MmodeResvBase;
> +STATIC UINT64                MmodeResvSize;
> +
> +/**
> +  Publish PEI core memory.
> +
> +  @return EFI_SUCCESS     The PEIM initialized successfully.
> +
> +**/
> +EFI_STATUS
> +PublishPeiMemory (
> +  VOID
> +  )
> +{
> +  EFI_RISCV_FIRMWARE_CONTEXT  *FirmwareContext;
> +  EFI_PHYSICAL_ADDRESS        MemoryBase;
> +  CONST UINT64                *RegProp;
> +  CONST CHAR8                 *Type;
> +  EFI_STATUS                  Status;
> +  UINT64                      CurBase, CurSize;
> +  UINT64                      NewBase = 0, NewSize = 0;
> +  UINT64                      MemorySize;
> +  INT32                       Node, Prev;
> +  INT32                       Len;
> +  VOID                        *FdtPointer;
> +
> +  FirmwareContext = NULL;
> +  GetFirmwareContextPointer (&FirmwareContext);
> +
> +  if (FirmwareContext == NULL) {
> +    DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n",
> __FUNCTION__));
> +    return EFI_UNSUPPORTED;
> +  }
> +
> +  FdtPointer = (VOID *)FirmwareContext->FlattenedDeviceTree;
> +  if (FdtPointer == NULL) {
> +    DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__));
> +    return EFI_UNSUPPORTED;
> +  }
> +
> +  // Look for the lowest memory node
> +  for (Prev = 0; ; Prev = Node) {
> +    Node = fdt_next_node (FdtPointer, Prev, NULL);
> +    if (Node < 0) {
> +      break;
> +    }
> +
> +    // Check for memory node
> +    Type = fdt_getprop (FdtPointer, Node, "device_type", &Len);
> +    if (Type && (AsciiStrnCmp (Type, "memory", Len) == 0)) {
> +      // Get the 'reg' property of this node. For now, we will assume
> +      // two 8 byte quantities for base and size, respectively.
> +      RegProp = fdt_getprop (FdtPointer, Node, "reg", &Len);
> +      if ((RegProp != 0) && (Len == (2 * sizeof (UINT64)))) {
> +        CurBase = fdt64_to_cpu (ReadUnaligned64 (RegProp));
> +        CurSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1));
> +
> +        DEBUG ((
> +          DEBUG_INFO,
> +          "%a: System RAM @ 0x%lx - 0x%lx\n",
> +          __FUNCTION__,
> +          CurBase,
> +          CurBase + CurSize - 1
> +          ));
> +
> +        if ((NewBase > CurBase) || (NewBase == 0)) {
> +          NewBase = CurBase;
> +          NewSize = CurSize;
> +        }
> +      } else {
> +        DEBUG ((
> +          DEBUG_ERROR,
> +          "%a: Failed to parse FDT memory node\n",
> +          __FUNCTION__
> +          ));
> +      }
> +    }
> +  }
> +
> +  SystemMemoryBase = NewBase;
> +  SystemMemorySize = NewSize;
> +
> +  /* try to locate the reserved memory opensbi node */  Node =
> + fdt_path_offset (FdtPointer, "/reserved-memory/mmode_resv0");  if
> + (Node >= 0) {
> +    RegProp = fdt_getprop (FdtPointer, Node, "reg", &Len);
> +    if ((RegProp != 0) && (Len == (2 * sizeof (UINT64)))) {
> +      NewBase = fdt64_to_cpu (ReadUnaligned64 (RegProp));
> +      NewSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1));
> +      DEBUG ((
> +        DEBUG_INFO,
> +        "%a: M-mode Base = 0x%lx, M-mode Size = 0x%lx\n",
> +        __FUNCTION__,
> +        NewBase,
> +        NewSize
> +        ));
> +      MmodeResvBase =  NewBase;
> +      MmodeResvSize = NewSize;
> +    }
> +  }
> +
> +  DEBUG ((
> +    DEBUG_INFO,
> +    "%a: SystemMemoryBase:0x%x SystemMemorySize:%x\n",
> +    __FUNCTION__,
> +    SystemMemoryBase,
> +    SystemMemorySize
> +    ));
> +
> +  //
> +  // Initial 16MB needs to be reserved
> +  //
> +  MemoryBase = SystemMemoryBase + SIZE_16MB;  MemorySize =
> + SystemMemorySize - SIZE_16MB;
> +
> +  //
> +  // Publish this memory to the PEI Core  //  Status =
> + PublishSystemMemory (MemoryBase, MemorySize);  ASSERT_EFI_ERROR
> + (Status);
> +
> +  return Status;
> +}
> +
> +/**
> +  Publish system RAM and reserve memory regions.
> +
> +**/
> +VOID
> +InitializeRamRegions (
> +  VOID
> +  )
> +{
> +  /*
> +   * M-mode FW can be loaded anywhere in memory but should not overlap
> +   * with the EDK2. This can happen if some other boot code loads the
> +   * M-mode firmware.
> +   *
> +   * The M-mode firmware memory should be marked as reserved memory
> +   * so that OS doesn't use it.
> +   */
> +  DEBUG ((
> +    DEBUG_INFO,
> +    "%a: M-mode FW Memory Start:0x%lx End:0x%lx\n",
> +    __FUNCTION__,
> +    MmodeResvBase,
> +    MmodeResvBase + MmodeResvSize
> +    ));
> +  AddReservedMemoryBaseSizeHob (MmodeResvBase, MmodeResvSize);
> +
> +  if (MmodeResvBase > SystemMemoryBase) {
> +    DEBUG ((
> +      DEBUG_INFO,
> +      "%a: Free Memory Start:0x%lx End:0x%lx\n",
> +      __FUNCTION__,
> +      SystemMemoryBase,
> +      MmodeResvBase
> +      ));
> +    AddMemoryRangeHob (SystemMemoryBase, MmodeResvBase);  }
> +
> +  DEBUG ((
> +    DEBUG_INFO,
> +    "%a: Free Memory Start:0x%lx End:0x%lx\n",
> +    __FUNCTION__,
> +    MmodeResvBase + MmodeResvSize,
> +    SystemMemoryBase + SystemMemorySize
> +    ));
> +  AddMemoryRangeHob (
> +    MmodeResvBase + MmodeResvSize,
> +    SystemMemoryBase + SystemMemorySize
> +    );
> +}
> diff --git a/OvmfPkg/PlatformPei/RiscV64/Platform.c
> b/OvmfPkg/PlatformPei/RiscV64/Platform.c
> new file mode 100644
> index 000000000000..45a2f44d9cca
> --- /dev/null
> +++ b/OvmfPkg/PlatformPei/RiscV64/Platform.c
> @@ -0,0 +1,372 @@
> +/** @file
> +  Platform PEI driver
> +
> +  Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP.
> + All rights reserved.<BR>  Copyright (c) 2006 - 2014, Intel
> + Corporation. All rights reserved.<BR>  Copyright (c) 2011, Andrei
> + Warkentin <andreiw@motorola.com>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +//
> +// The package level header files this module uses // #include
> +<PiPei.h>
> +
> +//
> +// The Library classes this module consumes // #include
> +<Library/DebugLib.h> #include <Library/HobLib.h> #include
> +<Library/IoLib.h> #include <Library/MemoryAllocationLib.h> #include
> +<Library/PcdLib.h> #include <Library/PciLib.h> #include
> +<Library/PeimEntryPoint.h> #include <Library/PeiServicesLib.h> #include
> +<Library/ResourcePublicationLib.h>
> +#include <Library/PlatformInitLib.h>
> +#include <Guid/MemoryTypeInformation.h> #include
> <Ppi/MasterBootMode.h>
> +#include <IndustryStandard/Pci22.h>
> +
> +#include "Platform.h"
> +
> +EFI_MEMORY_TYPE_INFORMATION  mDefaultMemoryTypeInformation[] =
> {
> +  { EfiACPIMemoryNVS,       0x004 },
> +  { EfiACPIReclaimMemory,   0x008 },
> +  { EfiReservedMemoryType,  0x004 },
> +  { EfiRuntimeServicesData, 0x024 },
> +  { EfiRuntimeServicesCode, 0x030 },
> +  { EfiBootServicesCode,    0x180 },
> +  { EfiBootServicesData,    0xF00 },
> +  { EfiMaxMemoryType,       0x000 }
> +};
> +
> +EFI_PEI_PPI_DESCRIPTOR  mPpiBootMode[] = {
> +  {
> +    EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
> +    &gEfiPeiMasterBootModePpiGuid,
> +    NULL
> +  }
> +};
> +
> +STATIC EFI_BOOT_MODE  mBootMode =
> BOOT_WITH_FULL_CONFIGURATION;
> +
> +/**
> +  Build memory map I/O range resource HOB using the
> +  base address and size.
> +
> +  @param  MemoryBase     Memory map I/O base.
> +  @param  MemorySize     Memory map I/O size.
> +
> +**/
> +VOID
> +AddIoMemoryBaseSizeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  UINT64                MemorySize
> +  )
> +{
> +  BuildResourceDescriptorHob (
> +    EFI_RESOURCE_MEMORY_MAPPED_IO,
> +    EFI_RESOURCE_ATTRIBUTE_PRESENT     |
> +    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> +    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> +    EFI_RESOURCE_ATTRIBUTE_TESTED,
> +    MemoryBase,
> +    MemorySize
> +    );
> +}
> +
> +/**
> +  Build reserved memory range resource HOB.
> +
> +  @param  MemoryBase     Reserved memory range base address.
> +  @param  MemorySize     Reserved memory range size.
> +
> +**/
> +VOID
> +AddReservedMemoryBaseSizeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  UINT64                MemorySize
> +  )
> +{
> +  BuildResourceDescriptorHob (
> +    EFI_RESOURCE_MEMORY_RESERVED,
> +    EFI_RESOURCE_ATTRIBUTE_PRESENT     |
> +    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> +    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> +    EFI_RESOURCE_ATTRIBUTE_TESTED,
> +    MemoryBase,
> +    MemorySize
> +    );
> +}
> +
> +/**
> +  Build memory map I/O resource using the base address
> +  and the top address of memory range.
> +
> +  @param  MemoryBase     Memory map I/O range base address.
> +  @param  MemoryLimit    The top address of memory map I/O range
> +
> +**/
> +VOID
> +AddIoMemoryRangeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  EFI_PHYSICAL_ADDRESS  MemoryLimit
> +  )
> +{
> +  AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit -
> +MemoryBase)); }
> +
> +/**
> +  Create memory range resource HOB using the memory base
> +  address and size.
> +
> +  @param  MemoryBase     Memory range base address.
> +  @param  MemorySize     Memory range size.
> +
> +**/
> +VOID
> +AddMemoryBaseSizeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  UINT64                MemorySize
> +  )
> +{
> +  BuildResourceDescriptorHob (
> +    EFI_RESOURCE_SYSTEM_MEMORY,
> +    EFI_RESOURCE_ATTRIBUTE_PRESENT |
> +    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> +    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> +    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> +    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> +    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
> +    EFI_RESOURCE_ATTRIBUTE_TESTED,
> +    MemoryBase,
> +    MemorySize
> +    );
> +}
> +
> +/**
> +  Create memory range resource HOB using memory base
> +  address and top address of the memory range.
> +
> +  @param  MemoryBase     Memory range base address.
> +  @param  MemoryLimit    Memory range size.
> +
> +**/
> +VOID
> +AddMemoryRangeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  EFI_PHYSICAL_ADDRESS  MemoryLimit
> +  )
> +{
> +  AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit -
> +MemoryBase)); }
> +
> +/**
> +  Create untested memory range resource HOB using memory base
> +  address and top address of the memory range.
> +
> +  @param  MemoryBase     Memory range base address.
> +  @param  MemorySize     Memory range size.
> +
> +**/
> +VOID
> +AddUntestedMemoryBaseSizeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  UINT64                MemorySize
> +  )
> +{
> +  BuildResourceDescriptorHob (
> +    EFI_RESOURCE_SYSTEM_MEMORY,
> +    EFI_RESOURCE_ATTRIBUTE_PRESENT |
> +    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> +    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> +    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> +    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> +    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
> +    MemoryBase,
> +    MemorySize
> +    );
> +}
> +
> +/**
> +  Create untested memory range resource HOB using memory base
> +  address and top address of the memory range.
> +
> +  @param  MemoryBase     Memory range base address.
> +  @param  MemoryLimit    Memory range size.
> +
> +**/
> +VOID
> +AddUntestedMemoryRangeHob (
> +  EFI_PHYSICAL_ADDRESS  MemoryBase,
> +  EFI_PHYSICAL_ADDRESS  MemoryLimit
> +  )
> +{
> +  AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit
> -
> +MemoryBase)); }
> +
> +/**
> +  Add PCI resource.
> +
> +**/
> +VOID
> +AddPciResource (
> +  VOID
> +  )
> +{
> +  //
> +  // Platform-specific
> +  //
> +}
> +
> +/**
> +  Platform memory map initialization.
> +
> +**/
> +VOID
> +MemMapInitialization (
> +  VOID
> +  )
> +{
> +  //
> +  // Create Memory Type Information HOB
> +  //
> +  BuildGuidDataHob (
> +    &gEfiMemoryTypeInformationGuid,
> +    mDefaultMemoryTypeInformation,
> +    sizeof (mDefaultMemoryTypeInformation)
> +    );
> +
> +  //
> +  // Add PCI IO Port space available for PCI resource allocations.
> +  //
> +  AddPciResource ();
> +}
> +
> +/**
> +  Platform misc initialization.
> +
> +**/
> +VOID
> +MiscInitialization (
> +  VOID
> +  )
> +{
> +  //
> +  // Build the CPU HOB with guest RAM size dependent address width and
> +16-bits
> +  // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed
> +during
> +  // S3 resume as well, so we build it unconditionally.)
> +  //
> +  // TODO: Determine this dynamically from the platform
> +  // setting or the HART configuration.
> +  //
> +  BuildCpuHob (56, 32);
> +}
> +
> +/**
> +  Check if system returns from S3.
> +
> +  @return BOOLEAN   TRUE, system returned from S3
> +                    FALSE, system is not returned from S3
> +
> +**/
> +BOOLEAN
> +CheckResumeFromS3 (
> +  VOID
> +  )
> +{
> +  //
> +  // Platform implementation-specific
> +  //
> +  return FALSE;
> +}
> +
> +/**
> +  Platform boot mode initialization.
> +
> +**/
> +VOID
> +BootModeInitialization (
> +  VOID
> +  )
> +{
> +  EFI_STATUS  Status;
> +
> +  if (CheckResumeFromS3 ()) {
> +    DEBUG ((DEBUG_INFO, "This is wake from S3\n"));  } else {
> +    DEBUG ((DEBUG_INFO, "This is normal boot\n"));  }
> +
> +  Status = PeiServicesSetBootMode (mBootMode);  ASSERT_EFI_ERROR
> + (Status);
> +
> +  Status = PeiServicesInstallPpi (mPpiBootMode);
> +  ASSERT_EFI_ERROR (Status);
> +}
> +
> +/**
> +  Build processor information for U54 Coreplex processor.
> +
> +  @return EFI_SUCCESS     Status.
> +
> +**/
> +EFI_STATUS
> +BuildCoreInformationHob (
> +  VOID
> +  )
> +{
> +  //  return BuildRiscVSmbiosHobs ();
> +  return EFI_SUCCESS;
> +}
> +
> +/**
> +  Perform Platform PEI initialization.
> +
> +  @param  FileHandle      Handle of the file being invoked.
> +  @param  PeiServices     Describes the list of possible PEI Services.
> +
> +  @return EFI_SUCCESS     The PEIM initialized successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializePlatform (
> +  IN       EFI_PEI_FILE_HANDLE  FileHandle,
> +  IN CONST EFI_PEI_SERVICES     **PeiServices
> +  )
> +{
> +  EFI_STATUS  Status;
> +
> +  DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));  Status =
> + PlatformPeim ();  if (EFI_ERROR (Status)) {
> +    DEBUG ((DEBUG_ERROR, "PlatformPeim failed\n"));
> +    ASSERT (FALSE);
> +  }
> +
> +  BootModeInitialization ();
> +  DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n"));
> + PublishPeiMemory ();  DEBUG ((DEBUG_INFO, "PEI memory
> published.\n"));
> + InitializeRamRegions ();  DEBUG ((DEBUG_INFO, "Platform RAM regions
> + initiated.\n"));
> +
> +  if (mBootMode != BOOT_ON_S3_RESUME) {
> +    PeiFvInitialization ();
> +    MemMapInitialization ();
> +  }
> +
> +  MiscInitialization ();
> +  Status = BuildCoreInformationHob ();
> +  if (EFI_ERROR (Status)) {
> +    DEBUG ((DEBUG_ERROR, "Fail to build processor information HOB.\n"));
> +    ASSERT (FALSE);
> +  }
> +
> +  return EFI_SUCCESS;
> +}
> --
> 2.38.0
> 
> 
> 
> 
>