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charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only - General] Please update AMD copyright in these two files to year 2023. Reviewed-by: Abner Chang > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Abdul > Lateef Attar via groups.io > Sent: Wednesday, January 11, 2023 2:16 PM > To: devel@edk2.groups.io > Cc: Attar, AbdulLateef (Abdul Lateef) ; > Grimes, Paul ; Kirkendall, Garrett > ; Chang, Abner ; > Michael D Kinney ; Liming Gao > ; Zhiguang Liu > Subject: [edk2-devel] [PATCH v2 2/6] MdePkg: Adds AMD SMRAM save state > map >=20 > Caution: This message originated from an External Source. Use proper > caution when opening attachments, clicking links, or responding. >=20 >=20 > BZ: > https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fbugz > illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4182&data=3D05%7C01%7Cabner. > chang%40amd.com%7C9f41cb0c402347d730f808daf39b74be%7C3dd8961fe48 > 84e608e11a82d994e183d%7C0%7C0%7C638090146263439328%7CUnknown% > 7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW > wiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=3Db1jrR3hCwT%2BJhB2j7xcX > fOHVsaVPhhSz0ZfCzey8lgc%3D&reserved=3D0 >=20 > Adds an SMM SMRAM save-state map for AMD processors. > SMRAM save state maps for the AMD processor family are now supported. >=20 > Save state map structure is added based on > AMD64 Architecture Programmer's Manual, Volume 2, Section 10.2. >=20 > The AMD legacy save state map for 32-bit architecture is defined. > The AMD64 save state map for 64-bit architecture is defined. >=20 > Also added Amd/SmramSaveStateMap.h to IgnoreFiles of EccCheck, because > structures defined in this file are derived from Intel/SmramSaveStateMap.= h. >=20 > Cc: Paul Grimes > Cc: Garrett Kirkendall > Cc: Abner Chang > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu >=20 > Signed-off-by: Abdul Lateef Attar > --- > .../Include/Register/Amd/SmramSaveStateMap.h | 194 > ++++++++++++++++++ > MdePkg/MdePkg.ci.yaml | 3 +- > 2 files changed, 196 insertions(+), 1 deletion(-) create mode 100644 > MdePkg/Include/Register/Amd/SmramSaveStateMap.h >=20 > diff --git a/MdePkg/Include/Register/Amd/SmramSaveStateMap.h > b/MdePkg/Include/Register/Amd/SmramSaveStateMap.h > new file mode 100644 > index 000000000000..6da1538608cf > --- /dev/null > +++ b/MdePkg/Include/Register/Amd/SmramSaveStateMap.h > @@ -0,0 +1,194 @@ > +/** @file >=20 > + AMD SMRAM Save State Map Definitions. >=20 > + >=20 > + SMRAM Save State Map definitions based on contents of the >=20 > + AMD64 Architecture Programmer Manual: >=20 > + Volume 2, System Programming, Section 10.2 SMM Resources >=20 > + >=20 > + Copyright (c) 2015 - 2019, Intel Corporation. All rights > + reserved.
>=20 > + Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved > + .
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#ifndef AMD_SMRAM_SAVE_STATE_MAP_H_ >=20 > +#define AMD_SMRAM_SAVE_STATE_MAP_H_ >=20 > + >=20 > +/// >=20 > +/// Default SMBASE address >=20 > +/// >=20 > +#define SMM_DEFAULT_SMBASE 0x30000 >=20 > + >=20 > +/// >=20 > +/// Offset of SMM handler from SMBASE >=20 > +/// >=20 > +#define SMM_HANDLER_OFFSET 0x8000 >=20 > + >=20 > +// SMM-Revision Identifier for AMD64 Architecture. >=20 > +#define AMD_SMM_MIN_REV_ID_X64 0x30064 >=20 > + >=20 > +#pragma pack (1) >=20 > + >=20 > +/// >=20 > +/// 32-bit SMRAM Save State Map >=20 > +/// >=20 > +typedef struct { >=20 > + // Padded an extra 0x200 bytes to match Intel/EDK2 >=20 > + UINT8 Reserved[0x200]; // fc00h >=20 > + // AMD Save State area starts @ 0xfe00 >=20 > + UINT8 Reserved1[0xf8]; // fe00h >=20 > + UINT32 SMBASE; // fef8h >=20 > + UINT32 SMMRevId; // fefch >=20 > + UINT16 IORestart; // ff00h >=20 > + UINT16 AutoHALTRestart; // ff02h >=20 > + UINT8 Reserved2[0x84]; // ff04h >=20 > + UINT32 GDTBase; // ff88h >=20 > + UINT64 Reserved3; // ff8ch >=20 > + UINT32 IDTBase; // ff94h >=20 > + UINT8 Reserved4[0x10]; // ff98h >=20 > + UINT32 _ES; // ffa8h >=20 > + UINT32 _CS; // ffach >=20 > + UINT32 _SS; // ffb0h >=20 > + UINT32 _DS; // ffb4h >=20 > + UINT32 _FS; // ffb8h >=20 > + UINT32 _GS; // ffbch >=20 > + UINT32 LDTBase; // ffc0h >=20 > + UINT32 _TR; // ffc4h >=20 > + UINT32 _DR7; // ffc8h >=20 > + UINT32 _DR6; // ffcch >=20 > + UINT32 _EAX; // ffd0h >=20 > + UINT32 _ECX; // ffd4h >=20 > + UINT32 _EDX; // ffd8h >=20 > + UINT32 _EBX; // ffdch >=20 > + UINT32 _ESP; // ffe0h >=20 > + UINT32 _EBP; // ffe4h >=20 > + UINT32 _ESI; // ffe8h >=20 > + UINT32 _EDI; // ffech >=20 > + UINT32 _EIP; // fff0h >=20 > + UINT32 _EFLAGS; // fff4h >=20 > + UINT32 _CR3; // fff8h >=20 > + UINT32 _CR0; // fffch >=20 > +} AMD_SMRAM_SAVE_STATE_MAP32; >=20 > + >=20 > +/// >=20 > +/// 64-bit SMRAM Save State Map >=20 > +/// >=20 > +typedef struct { >=20 > + // Padded an extra 0x200 bytes to match Intel/EDK2 >=20 > + UINT8 Reserved[0x200]; // fc00h >=20 > + // AMD Save State area starts @ 0xfe00 >=20 > + UINT16 _ES; // fe00h >=20 > + UINT16 _ESAttributes; // fe02h >=20 > + UINT32 _ESLimit; // fe04h >=20 > + UINT64 _ESBase; // fe08h >=20 > + >=20 > + UINT16 _CS; // fe10h >=20 > + UINT16 _CSAttributes; // fe12h >=20 > + UINT32 _CSLimit; // fe14h >=20 > + UINT64 _CSBase; // fe18h >=20 > + >=20 > + UINT16 _SS; // fe20h >=20 > + UINT16 _SSAttributes; // fe22h >=20 > + UINT32 _SSLimit; // fe24h >=20 > + UINT64 _SSBase; // fe28h >=20 > + >=20 > + UINT16 _DS; // fe30h >=20 > + UINT16 _DSAttributes; // fe32h >=20 > + UINT32 _DSLimit; // fe34h >=20 > + UINT64 _DSBase; // fe38h >=20 > + >=20 > + UINT16 _FS; // fe40h >=20 > + UINT16 _FSAttributes; // fe42h >=20 > + UINT32 _FSLimit; // fe44h >=20 > + UINT64 _FSBase; // fe48h >=20 > + >=20 > + UINT16 _GS; // fe50h >=20 > + UINT16 _GSAttributes; // fe52h >=20 > + UINT32 _GSLimit; // fe54h >=20 > + UINT64 _GSBase; // fe58h >=20 > + >=20 > + UINT32 _GDTRReserved1; // fe60h >=20 > + UINT16 _GDTRLimit; // fe64h >=20 > + UINT16 _GDTRReserved2; // fe66h >=20 > + // UINT64 _GDTRBase; // fe68h >=20 > + UINT32 _GDTRBaseLoDword; >=20 > + UINT32 _GDTRBaseHiDword; >=20 > + >=20 > + UINT16 _LDTR; // fe70h >=20 > + UINT16 _LDTRAttributes; // fe72h >=20 > + UINT32 _LDTRLimit; // fe74h >=20 > + // UINT64 _LDTRBase; // fe78h >=20 > + UINT32 _LDTRBaseLoDword; >=20 > + UINT32 _LDTRBaseHiDword; >=20 > + >=20 > + UINT32 _IDTRReserved1; // fe80h >=20 > + UINT16 _IDTRLimit; // fe84h >=20 > + UINT16 _IDTRReserved2; // fe86h >=20 > + // UINT64 _IDTRBase; // fe88h >=20 > + UINT32 _IDTRBaseLoDword; >=20 > + UINT32 _IDTRBaseHiDword; >=20 > + >=20 > + UINT16 _TR; // fe90h >=20 > + UINT16 _TRAttributes; // fe92h >=20 > + UINT32 _TRLimit; // fe94h >=20 > + UINT64 _TRBase; // fe98h >=20 > + >=20 > + UINT64 IO_RIP; // fea0h >=20 > + UINT64 IO_RCX; // fea8h >=20 > + UINT64 IO_RSI; // feb0h >=20 > + UINT64 IO_RDI; // feb8h >=20 > + UINT32 IO_DWord; // fec0h >=20 > + UINT8 Reserved1[0x04]; // fec4h >=20 > + UINT8 IORestart; // fec8h >=20 > + UINT8 AutoHALTRestart; // fec9h >=20 > + UINT8 Reserved2[0x06]; // fecah >=20 > + UINT64 EFER; // fed0h >=20 > + UINT64 SVM_Guest; // fed8h >=20 > + UINT64 SVM_GuestVMCB; // fee0h >=20 > + UINT64 SVM_GuestVIntr; // fee8h >=20 > + UINT8 Reserved3[0x0c]; // fef0h >=20 > + UINT32 SMMRevId; // fefch >=20 > + UINT32 SMBASE; // ff00h >=20 > + UINT8 Reserved4[0x14]; // ff04h >=20 > + UINT64 SSP; // ff18h >=20 > + UINT64 SVM_GuestPAT; // ff20h >=20 > + UINT64 SVM_HostEFER; // ff28h >=20 > + UINT64 SVM_HostCR4; // ff30h >=20 > + UINT64 SVM_HostCR3; // ff38h >=20 > + UINT64 SVM_HostCR0; // ff40h >=20 > + UINT64 _CR4; // ff48h >=20 > + UINT64 _CR3; // ff50h >=20 > + UINT64 _CR0; // ff58h >=20 > + UINT64 _DR7; // ff60h >=20 > + UINT64 _DR6; // ff68h >=20 > + UINT64 _RFLAGS; // ff70h >=20 > + UINT64 _RIP; // ff78h >=20 > + UINT64 _R15; // ff80h >=20 > + UINT64 _R14; // ff88h >=20 > + UINT64 _R13; // ff90h >=20 > + UINT64 _R12; // ff98h >=20 > + UINT64 _R11; // ffa0h >=20 > + UINT64 _R10; // ffa8h >=20 > + UINT64 _R9; // ffb0h >=20 > + UINT64 _R8; // ffb8h >=20 > + UINT64 _RDI; // ffc0h >=20 > + UINT64 _RSI; // ffc8h >=20 > + UINT64 _RBP; // ffd0h >=20 > + UINT64 _RSP; // ffd8h >=20 > + UINT64 _RBX; // ffe0h >=20 > + UINT64 _RDX; // ffe8h >=20 > + UINT64 _RCX; // fff0h >=20 > + UINT64 _RAX; // fff8h >=20 > +} AMD_SMRAM_SAVE_STATE_MAP64; >=20 > + >=20 > +/// >=20 > +/// Union of 32-bit and 64-bit SMRAM Save State Maps >=20 > +/// >=20 > +typedef union { >=20 > + AMD_SMRAM_SAVE_STATE_MAP32 x86; >=20 > + AMD_SMRAM_SAVE_STATE_MAP64 x64; >=20 > +} AMD_SMRAM_SAVE_STATE_MAP; >=20 > + >=20 > +#pragma pack () >=20 > + >=20 > +#endif >=20 > diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml index > 19bc0138cb76..86c9c502d799 100644 > --- a/MdePkg/MdePkg.ci.yaml > +++ b/MdePkg/MdePkg.ci.yaml > @@ -65,7 +65,8 @@ > "Include/Library/PcdLib.h", >=20 > "Include/Library/SafeIntLib.h", >=20 > "Include/Protocol/DebugSupport.h", >=20 > - "Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c" >=20 > + > + "Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c", >=20 > + "Include/Register/Amd/SmramSaveStateMap.h" >=20 > ] >=20 > }, >=20 > ## options defined ci/Plugin/CompilerPlugin >=20 > -- > 2.25.1 >=20 >=20 >=20 >=20 >=20