From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (NAM12-MW2-obe.outbound.protection.outlook.com [40.107.244.55]) by mx.groups.io with SMTP id smtpd.web10.134435.1673758362445653419 for ; Sat, 14 Jan 2023 20:52:42 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@amd.com header.s=selector1 header.b=iayv0R2O; spf=permerror, err=parse error for token &{10 18 %{i}._ip.%{h}._ehlo.%{d}._spf.vali.email}: invalid domain name (domain: amd.com, ip: 40.107.244.55, mailfrom: abner.chang@amd.com) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dT65kN9CxL1Hty7eFrl2cTSF6NJovddA2ROXGC5Z935Qz1b5Wb/Jl5YYSv0jvQr1rmUcMV9bWwmWSk0WysZdpSOp6G7QfgYYNise6snyz+rrRqaqLSAEC1JSLtCtD6dmJ92YV8PFc+qL2tDNwfxKz/ljiVa8pW2pTGmNKGYlBZCnM82PwdlDan8RQRF1M5av+4Bu3j7DNLXNBfNca5gzNJLD1UJ8wQtCIXVVqKSWWhu2UKMJAeDOOmV7d3wFmhcFUUUKH0j4wC0FI+lvD2mq28P/aqN9Ves85fI5KM+YR1yJ1el3gMQQ6SW3vX5kOzfEHDQjFU7nk34X5pTvgNAzAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JZIPskh0Ylb0ZbEyHxhymInjPK35kZdrIO3aeSTP0fg=; b=AJeY/G5vkJH7PXj6DcH6WCY8XKwbOT9hZMcDH/mgwpjGczMSNr8Nts57lffSF5ARDX5yW7kxgm6Pbd2Y0h4V/yFcT9SlZL+JDNGEbRd/1JtqVhFBI1u2C9QaEQCNBo+vh8bmweYCt4/1M2ybC8j05PeOn5Z5ptuVoK+4kyLD8XcB4nkWFwiwiY0RMy7cNXRKavTlhYB9B5IfP2lclYZq4+uvbd5NWe0RIAEd8sjCJUAWBlJ3VWXSWaPsoApJfNAk2VBr+wsN95EMWSfWao8O+WYfdf5p/NbGCKnr4qe/hDr0Dh4tP/7kLItGWDNE9rpERkbfQL0wNySULpU8EtFtPg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JZIPskh0Ylb0ZbEyHxhymInjPK35kZdrIO3aeSTP0fg=; b=iayv0R2OTel7YB27UC8fxgyTKPyPV7dZilRmT70X24DqxGm8X3XIdv/YFHfz8NptWOVcAuHjGS0ioYSY0qAQMcbKCP5m46Nt5wZ0hGjnjJTDjtSYG1fTF17+EGqFRa+ueMHPXoBqfS4FPHN10CzCizVXCJD/VTw/03vsVhzfJnc= Received: from MN2PR12MB3966.namprd12.prod.outlook.com (2603:10b6:208:165::18) by SN7PR12MB7252.namprd12.prod.outlook.com (2603:10b6:806:2ac::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5986.19; Sun, 15 Jan 2023 04:52:39 +0000 Received: from MN2PR12MB3966.namprd12.prod.outlook.com ([fe80::cddb:3de9:cd1d:26e4]) by MN2PR12MB3966.namprd12.prod.outlook.com ([fe80::cddb:3de9:cd1d:26e4%5]) with mapi id 15.20.5986.022; Sun, 15 Jan 2023 04:52:38 +0000 From: "Chang, Abner" To: "Attar, AbdulLateef (Abdul Lateef)" , "devel@edk2.groups.io" CC: "Attar, AbdulLateef (Abdul Lateef)" , "Grimes, Paul" , "Kirkendall, Garrett" , Eric Dong , Ray Ni , Rahul Kumar , "Attar, AbdulLateef (Abdul Lateef)" Subject: Re: [PATCH v2 6/6] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family Thread-Topic: [PATCH v2 6/6] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family Thread-Index: AQHZJYRyZlSsIR6bbE+ahKwiKflg1K6e71BQ Date: Sun, 15 Jan 2023 04:52:38 +0000 Message-ID: References: <27ef3133e6d416bfcdc81c27b6c2c04bf0932c96.1673417268.git.abdattar@amd.com> In-Reply-To: <27ef3133e6d416bfcdc81c27b6c2c04bf0932c96.1673417268.git.abdattar@amd.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_Enabled=true; MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_SetDate=2023-01-15T04:52:36Z; MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_Method=Standard; MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_Name=General; MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_SiteId=3dd8961f-e488-4e60-8e11-a82d994e183d; MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_ActionId=d684690c-a010-40bf-9832-9cfcc23ff566; MSIP_Label_4342314e-0df4-4b58-84bf-38bed6170a0f_ContentBits=1 authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MN2PR12MB3966:EE_|SN7PR12MB7252:EE_ x-ms-office365-filtering-correlation-id: ee6c766b-5a94-488e-5d7c-08daf6b45381 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: sJJAyX0W9VfJb1HFHyXFxKKlEHsYr5ksQw6ULn53DlOQwXsfT1m5jfwKrAOzOlYnTj5fVO92xneGAkcOTDp8lpON+i94vx5oBtJXK02qsXQDaNJqYskERrhbKuPymaXrG9JlJbEWBaA5LuAnBuHeAJJVv89rtu4RTnX7AfWx8Lsau9ObBpljp4wXhTwgjT9XFfz5CQaCwMxZZMMso7PFTt5CL7BLcLxbB8PRC1jfj/JMaIWwV2cvMyrGcBRT/uL46NDNgdNdraeVjSV6/IUQ8PYXV2L84CF//yoNiAztm0fCHOuHQKBN0PbhWe2Vi6LtljGpVCZdk9FXgfP7k6mZiCqzJf09uiwy7fKFl78mHbjoOQ4vNUN8+/ct/1+OXXqapxuJz5zMxRglteDHUpWGjCpuukEQKuYcfw9WiSYpdKhKQpxIJsnIw0juJuMDE5klkT1oWRtLtgBb8PvxmhLP42Sg9eWGbQeSfbzFmjaLwaF5CFJtSXOKVv9potTioCD44WsZd7p13vfjFmukAEnVpUfcF5rHRcUrOZWKXmz2WFWULGMcEYjMDk11+VhTG41SQRN/B+vpD29lrCGjVnoIcccoe6rdJ3goAZZ4YfvvHRFxZ1rMVX7ZI+WExxjuJJU2Y/TxQcn8DZGCd2nAhfpyzJg/YFKHm/4HsRb4hpqMnFHdMTsbTAkczkT/p6vAHKpsjADmf8xccz6Oqdn5FDOiliOR4arOBOcwPM2zGBQMHMQ= x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN2PR12MB3966.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(376002)(366004)(396003)(39860400002)(136003)(346002)(451199015)(41300700001)(9686003)(5660300002)(33656002)(52536014)(8936002)(53546011)(186003)(26005)(478600001)(6506007)(83380400001)(966005)(54906003)(110136005)(316002)(86362001)(66446008)(4326008)(64756008)(8676002)(38070700005)(66476007)(38100700002)(76116006)(55016003)(71200400001)(66946007)(66556008)(122000001)(7696005)(2906002);DIR:OUT;SFP:1101; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?RJa4Y60GW/zdO/t+kTpO8af6GwjwDrBPEFbiQuO2JbBWq4nCKo0zFT+G6lSl?= =?us-ascii?Q?y/zYeYi69GADQFXAPynsSI7G4Et13riczUWW0xT8cqdyE7JLOyxSbqSyen/5?= =?us-ascii?Q?Trsim97ilmjdyxn5gc7KQdY4USEC2uUL2D7RZwduelnuICf8qy4JJk19j2fe?= =?us-ascii?Q?8cEZU/ZkkVG0JDIPb7aMTrTUSj5lrNWBg/OuHe+dbsO9p1UGD8siXnoToUla?= =?us-ascii?Q?ifPlS8XpUoTTCpjB4Jtd4oeJ31x18cSI3Q/ylCtPYQ5WLiuibNgKEBiKpYfU?= =?us-ascii?Q?ojIlpLNNQOtbGNu6aeTOd89gHH25bdmQOge+/T/fSP4Op8sGy2NjEbLaRDx9?= =?us-ascii?Q?l1vkqCa/fnjzPU6gc+XEyDwme+RhE6JGnxYuQo4R7MsOQR5Xlh9LdJ8iZqyI?= =?us-ascii?Q?0dp1vtaYrXzcRVSSUVoiLczxZGFjJSThTts0GfA0YpqnoditLB0TZnOZEkQK?= =?us-ascii?Q?SRvYTUVZLK90WC39RPzYD6Af4xvOCQS2p0QCc3GvZch+M6JmJmLJJGN5ACH2?= =?us-ascii?Q?4ihj8PJ+sjfSa+LdO0T1hSfefdIyiJosKEWgp7AZxtK27E+QVYILEeIFvNZC?= =?us-ascii?Q?5jyuX8NTRwUj/oq93xAAuvLTwTeqtMl4W0m5tEZ7xLwC6oqP9LQazaqD5KcH?= =?us-ascii?Q?Ierk0mGnCyVHJ5cVizlphlMFio/2wtho5sB2TXfoXIW4zU8USemoFsph65zw?= =?us-ascii?Q?ELjHWqnIlqsXnS2+VyRf2wgN9o1wW2mdxUK3nkJcsksVYP/pJ5KNJBywWwfQ?= =?us-ascii?Q?mbtlQgfrlU9ftOAUoi5jikpJIQFM+IQuJWFnkpUO70lG6aIOQfCukqFskhJr?= =?us-ascii?Q?X4VWe1n3Qiy6iaC21huv1IlzMf9dWapP55V6zqEGHmN3c7LDWeTV//UHk8Fm?= =?us-ascii?Q?9a00nwkeP3Sgc6JxrzFG4td2PBFntAZKse0l4j/422KEpApwMIjeUNFRsBXp?= =?us-ascii?Q?r2DUCVrc9XIl2fH1Ajx3wiAnTVezAdF2h7I8sulvHX0npw860xvjbkyEV/1a?= =?us-ascii?Q?T4fg+38m7NdV+pKGJYELEuKLrahmyxvU1Rw3ElHZO6mmJFaBpikc9zvWe2hM?= =?us-ascii?Q?fxhOkvEKo3F6/VBcIw92MsAwdNrnD5H7wyNbKVMgZtEPyEXFWR631ozMsRuK?= =?us-ascii?Q?WBlPWfQSf5LhtDJFvuRA0JQgpRWQJHVbgccSyESOUpHnUGdCjAr6VHAFh365?= =?us-ascii?Q?66z7niiGowyD19RKqAd9OR7bmLIVF6iwJ3mIQ4xor3HvU6c5YCvLm6fp6eJv?= =?us-ascii?Q?DnSbWEmP5se7J8hOGeuf/wbYs2Oo8VYVtjuaS5TxSlQtOS1PAWzTCuG0XIJC?= =?us-ascii?Q?cQ2oRFnWFbAhu4vbI2Guzgj0aFFh/YZTkaVw1xSeUD0OoFzoovHi4EhRT6ap?= =?us-ascii?Q?euJ9W7CEPnCXWfWQeG/q3ouSS8BE8k7ydwb9L3ZnuywWgvKHHAovQXkv2ZnP?= =?us-ascii?Q?6WcZOSK/dtH1diIHku9JumiPdandSS8W05/T5lk1ic5voBsLtgUNlkJj/Oqc?= =?us-ascii?Q?9f6tSX9iDM4mDCJkn+yg7pqzQB0t1jSISSQaZIZI4ch58stQfKAK3bKUupVO?= =?us-ascii?Q?1Byr7gYwV/9Q9MBCI4qLaplBe7OY6+etUNIQXiIG?= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB3966.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ee6c766b-5a94-488e-5d7c-08daf6b45381 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Jan 2023 04:52:38.1723 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: +7jGkYdZLkS6xI3O3AHWw26gv0Qi9y5bW+NEw0Nm4HxEpIeZwhujJ5UHSRp/mE38vHvll0hm+SukQgzNDNWqsA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7252 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only - General] Reviewed-by: Abner Chang Thanks Abner > -----Original Message----- > From: Abdul Lateef Attar > Sent: Wednesday, January 11, 2023 2:16 PM > To: devel@edk2.groups.io > Cc: Attar, AbdulLateef (Abdul Lateef) ; > Grimes, Paul ; Kirkendall, Garrett > ; Chang, Abner ; > Eric Dong ; Ray Ni ; Rahul Kumar > ; Attar, AbdulLateef (Abdul Lateef) > > Subject: [PATCH v2 6/6] UefiCpuPkg: Implements SmmCpuFeaturesLib for > AMD Family >=20 > From: Abdul Lateef Attar >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4182 >=20 > Implements interfaces to read and write save state registers of AMD's > processor family. > Initializes processor SMMADDR and MASK depends on PcdSmrrEnable flag. > Program or corrects the IP once control returns from SMM. >=20 > Cc: Paul Grimes > Cc: Garrett Kirkendall > Cc: Abner Chang > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Signed-off-by: Abdul Lateef Attar > --- > .../AmdSmmCpuFeaturesLib.inf | 6 + > .../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 106 > +++++++++++++++++- > 2 files changed, 109 insertions(+), 3 deletions(-) >=20 > diff --git > a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > index 547b9cf15b84..236725d13ecf 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > +++ > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > @@ -31,3 +31,9 @@ [LibraryClasses] > PcdLib MemoryAllocationLib DebugLib+ > SmmSmramSaveStateLib++[FeaturePcd]+ > gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable ## CONSUMES+ > gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable ## > CONSUMES+diff --git > a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c > index c74e1a0c0c5b..af45be3e265a 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c > @@ -11,6 +11,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #include #include > +#include > +#include > +#include +#include > ++// EFER register LMA bit+#define > LMA BIT10++// Machine Specific Registers (MSRs)+#define > SMMADDR_ADDRESS 0xC0010112ul+#define SMMMASK_ADDRESS > 0xC0010113ul+#define EFER_ADDRESS 0XC0000080ul++// The mode of the > CPU at the time an SMI occurs+STATIC UINT8 mSmmSaveStateRegisterLma; > /** Read an SMM Save State register on the target processor. If this > function@@ -39,7 +54,7 @@ SmmCpuFeaturesReadSaveStateRegister ( > OUT VOID *Buffer ) {- return EFI_SUCCESS;+ = return > SmramSaveStateReadRegister (CpuIndex, Register, Width, Buffer); } /**@@ > -67,7 +82,7 @@ SmmCpuFeaturesWriteSaveStateRegister ( > IN CONST VOID *Buffer ) {- return EFI_SUCCESS;+ = return > SmramSaveStateWriteRegister (CpuIndex, Register, Width, Buffer); } > /**@@ -82,6 +97,13 @@ CpuFeaturesLibInitialization ( > VOID ) {+ UINT32 LMAValue;++ LMAValue =3D > (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;+ > mSmmSaveStateRegisterLma =3D > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;+ if (LMAValue) {+ > mSmmSaveStateRegisterLma =3D > EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;+ } } /**@@ -117,6 +139,52 > @@ SmmCpuFeaturesInitializeProcessor ( > IN CPU_HOT_PLUG_DATA *CpuHotPlugData ) {+ > AMD_SMRAM_SAVE_STATE_MAP *CpuState;+ UINT32 > LMAValue;++ //+ // Configure SMBASE.+ //+ CpuState =3D > (AMD_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + > SMRAM_SAVE_STATE_MAP_OFFSET);+ CpuState->x64.SMBASE =3D > (UINT32)CpuHotPlugData->SmBase[CpuIndex];++ // Re-initialize the value > of mSmmSaveStateRegisterLma flag which might have been changed in > PiCpuSmmDxeSmm Driver+ // Entry point, to make sure correct value on > AMD platform is assigned to be used by SmmCpuFeaturesLib.+ LMAValue > =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;+ > mSmmSaveStateRegisterLma =3D > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;+ if (LMAValue) {+ > mSmmSaveStateRegisterLma =3D > EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;+ }++ //+ // If SMRR is > supported, then program SMRR base/mask MSRs.+ // The > EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.+ > // The code that initializes SMM environment is running in normal mode+ = // > from SMRAM region. If SMRR is enabled here, then the SMRAM region+ // > is protected and the normal mode code execution will fail.+ //+ if > (FeaturePcdGet (PcdSmrrEnable)) {+ //+ // SMRR size cannot be less = than > 4-KBytes+ // SMRR size must be of length 2^n+ // SMRR base alignmen= t > cannot be less than SMRR length+ //+ if ((CpuHotPlugData->SmrrSize = < > SIZE_4KB) ||+ (CpuHotPlugData->SmrrSize !=3D GetPowerOfTwo32 > (CpuHotPlugData->SmrrSize)) ||+ ((CpuHotPlugData->SmrrBase & > ~(CpuHotPlugData->SmrrSize - 1)) !=3D CpuHotPlugData->SmrrBase))+ {+ > //+ // Print message and halt if CPU is Monarch+ //+ if (I= sMonarch) {+ > DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size > requirement!\n"));+ CpuDeadLoop ();+ }+ } else {+ Asm= WriteMsr64 > (SMMADDR_ADDRESS, CpuHotPlugData->SmrrBase);+ AsmWriteMsr64 > (SMMMASK_ADDRESS, ((~(UINT64)(CpuHotPlugData->SmrrSize - 1)) | > 0x6600));+ }+ } } /**@@ -159,7 +227,39 @@ > SmmCpuFeaturesHookReturnFromSmm ( > IN UINT64 NewInstructionPointer ) {- return 0;+ UIN= T64 > OriginalInstructionPointer;+ AMD_SMRAM_SAVE_STATE_MAP > *AmdCpuState;++ AmdCpuState =3D (AMD_SMRAM_SAVE_STATE_MAP > *)CpuState;++ if (mSmmSaveStateRegisterLma =3D=3D > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {+ > OriginalInstructionPointer =3D (UINT64)AmdCpuState->x86._EIP;+ > AmdCpuState->x86._EIP =3D (UINT32)NewInstructionPointer;+ //+ = // > Clear the auto HALT restart flag so the RSM instruction returns+ // pr= ogram > control to the instruction following the HLT instruction.+ //+ if > ((AmdCpuState->x86.AutoHALTRestart & BIT0) !=3D 0) {+ AmdCpuState- > >x86.AutoHALTRestart &=3D ~BIT0;+ }+ } else {+ OriginalInstruction= Pointer =3D > AmdCpuState->x64._RIP;+ if ((AmdCpuState->x64.EFER & LMA) =3D=3D 0) {+ > AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer32;+ } else {+ > AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer;+ }++ //+ = // > Clear the auto HALT restart flag so the RSM instruction returns+ // pr= ogram > control to the instruction following the HLT instruction.+ //+ if > ((AmdCpuState->x64.AutoHALTRestart & BIT0) !=3D 0) {+ AmdCpuState- > >x64.AutoHALTRestart &=3D ~BIT0;+ }+ }++ return > OriginalInstructionPointer; } /**-- > 2.25.1