From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qv1-f53.google.com (mail-qv1-f53.google.com [209.85.219.53]) by mx.groups.io with SMTP id smtpd.web11.52835.1681943845538227184 for ; Wed, 19 Apr 2023 15:37:25 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="signature has expired" header.i=@ventanamicro.com header.s=google header.b=RrhWs2WX; spf=pass (domain: ventanamicro.com, ip: 209.85.219.53, mailfrom: tphan@ventanamicro.com) Received: by mail-qv1-f53.google.com with SMTP id 6a1803df08f44-5f95cedb135so193006d6.1 for ; Wed, 19 Apr 2023 15:37:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681943844; x=1684535844; h=mime-version:content-language:accept-language:in-reply-to :references:message-id:date:thread-index:thread-topic:subject:cc:to :from:from:to:cc:subject:date:message-id:reply-to; bh=CcNeRQE1+JiH/M15OjrT35FxIBg3aX0feV/CBdUSa34=; b=RrhWs2WX9tBlaa2AWT0ndwjssVrOrRk04VioWlsq/vUx+AOjG8P/vfRgHCdGz9B5mU PjtYEBZuk5prBJcPkZK84N0taxDJdgKSWFXrAjIGfaeyUkcqxHb2TRCjy8RWRBT3M/ti bJxIf7wCGuAYZG1BQSXl89STMm7EDINDA5thrPeCcq52uFQIAAkaRQY7J8kB/GcC99gZ iqm179WL0vA8eaDeXr8TZsyTRuuaa5qrt79sAN/Ik4O93XRUcG/xOztK0C8cX5Fjkhe5 UC/W6Kb3atVFUZ5IOrH44eukY2FtjNUOGOGh3b9tjDk16Bcdc00qFI/wEDmw7aKhVk/X M5+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681943844; x=1684535844; h=mime-version:content-language:accept-language:in-reply-to :references:message-id:date:thread-index:thread-topic:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=CcNeRQE1+JiH/M15OjrT35FxIBg3aX0feV/CBdUSa34=; b=Vpd4PmrDrGWZf8r6hI3ldFcrUJzIkc4IySr91WB5DfTpBHIQ2wjq6rfzszAfndUDhT mBgtwscA0uWtWzY5WrWjU1wV2UuvVJbKUGd+ZyX5eoIil7f6zOGWTrmWsS26i+ubc4UY yK3cerbtXWJOHe6mmRiJMLQoG70P9FyoJXThap382ACcSRFSpkeeGeF85fDLj3ij8rVN PN3F5sZdsUt7qgRiXonLLlOaPHnTsLXtfIIYu0GAi3deKkKhCKiZsFK+vjWXsq94sbcZ 7YjUdj33JBVWhOLp5wnYyfGZkWCTl3Up9+IM7JfnXV7aHeX4bUtPCzYoeOSRZ3Uc1ZS2 IsUA== X-Gm-Message-State: AAQBX9dFg0pUfO2mBW4OX5ty53Em1c8C9rdkYc4p1F6EKfvg076rnrPm +DHdtHK2r7LkR8vIOKueA5o1Pb1Hikcs3y7G1e8= X-Google-Smtp-Source: AKy350ZI9an+SPZeZ+rmkde1ET+huCY+O7xB03VWZtilz8JS6ubWI8K8/gTlHoD0GaPy5wNa1VCcMg== X-Received: by 2002:a05:6214:da1:b0:56b:f28e:628a with SMTP id h1-20020a0562140da100b0056bf28e628amr383189qvh.6.1681943844153; Wed, 19 Apr 2023 15:37:24 -0700 (PDT) Return-Path: Received: from MN2PR13MB3022.namprd13.prod.outlook.com ([2603:1036:302:405e::5]) by smtp.gmail.com with ESMTPSA id f14-20020a0cf3ce000000b005eec576e4d2sm32627qvm.87.2023.04.19.15.37.23 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Apr 2023 15:37:23 -0700 (PDT) From: "Tuan Phan" To: "devel@edk2.groups.io" , "andrei.warkentin@intel.com" CC: "Kinney, Michael D" , "Gao, Liming" , "Liu, Zhiguang" , "sunilvl@ventanamicro.com" , "git@danielschaefer.me" Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support Thread-Topic: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support Thread-Index: AW4tOTgxUuPslz7sLnctKdjs1S/2ZNaJrDqAgAIAJ2o= X-MS-Exchange-MessageSentRepresentingType: 1 Date: Wed, 19 Apr 2023 22:37:23 +0000 Message-ID: References: <20230414185815.2994-1-tphan@ventanamicro.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-Exchange-Organization-SCL: -1 X-MS-TNEF-Correlator: X-MS-Exchange-Organization-RecordReviewCfmType: 0 MIME-Version: 1.0 Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN2PR13MB30222EA8A4CC9AA908B6BE38A7629MN2PR13MB3022namp_" --_000_MN2PR13MB30222EA8A4CC9AA908B6BE38A7629MN2PR13MB3022namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Andrei, Here you go: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu Will put the link in the cover letter next round. From: devel@edk2.groups.io on behalf of Andrei Warke= ntin Date: Tuesday, April 18, 2023 at 9:04 AM To: Tuan Phan , devel@edk2.groups.io Cc: Kinney, Michael D , Gao, Liming , Liu, Zhiguang , sunilvl@ventanamic= ro.com , git@danielschaefer.me Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support Hi Tuan, Do you mind sharing the GitHub branch as well? It would help with the revie= w immensely. A > -----Original Message----- > From: Tuan Phan > Sent: Friday, April 14, 2023 1:58 PM > To: devel@edk2.groups.io > Cc: Kinney, Michael D ; Gao, Liming > ; Liu, Zhiguang ; > sunilvl@ventanamicro.com; git@danielschaefer.me; Warkentin, Andrei > ; Tuan Phan > Subject: [PATCH v2 0/6] RISC-V MMU support > > RISC-V: Add MMU support > > This series adds MMU support for RISC-V. Only SV39/48/57 modes are > supported and tested. The MMU is required to support setting page > attribute which is the first basic step to support security booting on RI= SC-V. > > There are three parts: > 1. Add MMU base library. MMU will be enabled during CpuDxe initialization= . > 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to G= CD > if already done. > 3. Fix all resources should be populated in HOB or added to GCD by driver > before accessing when MMU enabled. > > Changes in v2: > - Move MMU core to a library. > - Setup SATP mode as highest possible that HW supports. > > Tuan Phan (6): > MdePkg/BaseLib: RISC-V: Support getting satp register value > MdePkg/Register: RISC-V: Add satp mode bits shift definition > UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode > OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size > OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists > OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform > devices > > MdePkg/Include/Library/BaseLib.h | 5 + > MdePkg/Include/Library/BaseRiscVMmuLib.h | 39 ++ > .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- > MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 > ++++++++++++++++++ > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 25 + > MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 + > .../VirtNorFlashStaticLib.c | 3 +- > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + > OvmfPkg/RiscVVirt/Sec/Memory.c | 18 +- > OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ > OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + > OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + > UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 + > 16 files changed, 776 insertions(+), 31 deletions(-) create mode 100644 > MdePkg/Include/Library/BaseRiscVMmuLib.h > create mode 100644 > MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > create mode 100644 > MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S > > -- > 2.25.1 --_000_MN2PR13MB30222EA8A4CC9AA908B6BE38A7629MN2PR13MB3022namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi Andrei,

Here you go: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu

Will put the link i= n the cover letter next round.

 

From: devel@edk2.groups.i= o <devel@edk2.groups.io> on behalf of Andrei Warkentin <andrei.war= kentin@intel.com>
Date: Tuesday, April 18, 2023 at 9:04 AM
To: Tuan Phan <tphan@ventanamicro.com>, devel@edk2.groups.io &= lt;devel@edk2.groups.io>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>, Gao, Limin= g <gaoliming@byosoft.com.cn>, Liu, Zhiguang <zhiguang.liu@intel.co= m>, sunilvl@ventanamicro.com <sunilvl@ventanamicro.com>, git@danie= lschaefer.me <git@danielschaefer.me>
Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support

Hi Tuan,

Do you mind sharing the GitHub branch as well? It would help with the revie= w immensely.

A

> -----Original Message-----
> From: Tuan Phan <tphan@ventanamicro.com>
> Sent: Friday, April 14, 2023 1:58 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming<= br> > <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel= .com>;
> sunilvl@ventanamicro.com; git@danielschaefer.me; Warkentin, Andrei
> <andrei.warkentin@intel.com>; Tuan Phan <tphan@ventanamicro.c= om>
> Subject: [PATCH v2 0/6] RISC-V MMU support
>
> RISC-V: Add MMU support
>
> This series adds MMU support for RISC-V. Only SV39/48/57 modes are
> supported and tested. The MMU is required to support setting page
> attribute which is the first basic step to support security booting on= RISC-V.
>
> There are three parts:
> 1. Add MMU base library. MMU will be enabled during CpuDxe initializat= ion.
> 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address t= o GCD
> if already done.
> 3. Fix all resources should be populated in HOB or added to GCD by dri= ver
> before accessing when MMU enabled.
>
> Changes in v2:
>   - Move MMU core to a library.
>   - Setup SATP mode as highest possible that HW supports. >
> Tuan Phan (6):
>   MdePkg/BaseLib: RISC-V: Support getting satp register valu= e
>   MdePkg/Register: RISC-V: Add satp mode bits shift definiti= on
>   UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
>   OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flas= h size
>   OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists=
>   OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for pla= tform
>     devices
>
>  MdePkg/Include/Library/BaseLib.h     &n= bsp;        |   5 +
>  MdePkg/Include/Library/BaseRiscVMmuLib.h    =   |  39 ++
>  .../Include/Register/RiscV64/RiscVEncoding.h  |  = 7 +-
>  MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S    = ; |   8 +
>  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569
> ++++++++++++++++++
>  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf    &= nbsp;  |  25 +
>  MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S |  31 +
>  .../VirtNorFlashStaticLib.c      &= nbsp;            |&n= bsp;  3 +-
>  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc     = ;      |   1 +
>  OvmfPkg/RiscVVirt/Sec/Memory.c     &nbs= p;          |  18 +-
>  OvmfPkg/RiscVVirt/Sec/Platform.c     &n= bsp;        |  62 ++
>  OvmfPkg/RiscVVirt/Sec/SecMain.inf     &= nbsp;       |   1 +
>  OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c    = ; |  25 +-
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c     &= nbsp;       |   9 +-
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h     &= nbsp;       |   2 +
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf    |&n= bsp;  2 +
>  16 files changed, 776 insertions(+), 31 deletions(-)  creat= e mode 100644
> MdePkg/Include/Library/BaseRiscVMmuLib.h
>  create mode 100644
> MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
>  create mode 100644
> MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
>  create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S=
>
> --
> 2.25.1





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