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Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.55; Mon, 13 May 2024 02:23:06 +0000 X-Received: from MN6PR11MB8244.namprd11.prod.outlook.com ([fe80::41a4:c775:32e6:76a8]) by MN6PR11MB8244.namprd11.prod.outlook.com ([fe80::41a4:c775:32e6:76a8%4]) with mapi id 15.20.7544.052; Mon, 13 May 2024 02:23:06 +0000 From: "Ni, Ray" To: "Tan, Dun" , "devel@edk2.groups.io" CC: Laszlo Ersek , "Kumar, Rahul R" , Gerd Hoffmann , "Wu, Jiaxin" Subject: Re: [edk2-devel] [PATCH 10/18] UefiCpuPkg:Relocate AP to new safe buffer in PeiMpLib Thread-Topic: [PATCH 10/18] UefiCpuPkg:Relocate AP to new safe buffer in PeiMpLib Thread-Index: AQHaosIk7d4/UW13JkuEGzuUOawdRbGUc1Ms Date: Mon, 13 May 2024 02:23:06 +0000 Message-ID: References: <20240510100827.1903-1-dun.tan@intel.com> <20240510100827.1903-11-dun.tan@intel.com> In-Reply-To: <20240510100827.1903-11-dun.tan@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: x-ms-publictraffictype: Email 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19:23:11 -0700 Resent-From: ray.ni@intel.com Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: iGCwVxqe70jvwfixJ0OIZNAbx7686176AA= Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN6PR11MB82440BC30FBB6ADCF7B27C198CE22MN6PR11MB8244namp_" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=wga25X1j; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none) --_000_MN6PR11MB82440BC30FBB6ADCF7B27C198CE22MN6PR11MB8244namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni Thanks, Ray ________________________________ From: Tan, Dun Sent: Friday, May 10, 2024 18:08 To: devel@edk2.groups.io Cc: Ni, Ray ; Laszlo Ersek ; Kumar, Ra= hul R ; Gerd Hoffmann ; Wu, Jia= xin Subject: [PATCH 10/18] UefiCpuPkg:Relocate AP to new safe buffer in PeiMpLi= b In this commit, change PeiMpLib to install callback of gEdkiiEndOfS3ResumeGuid to relocate AP to new safe buffer. The gEdkiiEndOfS3ResumeGuid is installed in S3Resume.c before jmping to OS waking vector. Previously, code in CpuS3.c of PiSmmCpuDxe driver will prepare the new safe buffer for AP and place AP in hlt loop state. With this code change, we can remove the Machine Instructions of mApHltLoopCode in PiSmmCpuDxe. Also we can reuse the related code in DxeMpLib for PeiMpLib. Signed-off-by: Dun Tan Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Jiaxin Wu --- UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 +++ UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 4 ++++ UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 152 ++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 11e0d2661f..3efd913395 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -68,6 +69,8 @@ // #define DEFAULT_MAX_MICROCODE_PATCH_NUM 8 +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull + // // Data structure for microcode patch information // diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index e31e34b6f9..8736690348 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -25,10 +25,12 @@ [Sources.IA32] Ia32/AmdSev.c Ia32/MpFuncs.nasm + Ia32/CreatePageTable.c [Sources.X64] X64/AmdSev.c X64/MpFuncs.nasm + X64/CreatePageTable.c [Sources.IA32, Sources.X64] AmdSev.c @@ -64,6 +66,7 @@ LocalApicLib MicrocodeLib MtrrLib + CpuPageTableLib [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONS= UMES @@ -87,6 +90,7 @@ gEdkiiS3SmmInitDoneGuid gEdkiiMicrocodePatchHobGuid gGhcbApicIdsGuid ## SOMETIMES_CONSUMES + gEdkiiEndOfS3ResumeGuid [Guids.LoongArch64] gProcessorResourceHobGuid ## SOMETIMES_CONSUMES ## HOB diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/M= pInitLib/PeiMpLib.c index 4d3acb491f..deb5fc3aac 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c @@ -9,6 +9,7 @@ #include "MpLib.h" #include #include +#include #include STATIC UINT64 mSevEsPeiWakeupBuffer =3D BASE_1MB; @@ -449,6 +450,47 @@ BuildMicrocodeCacheHob ( return; } +/** + S3 SMM Init Done notification function. + + @param PeiServices Indirect reference to the PEI Services Table. + @param NotifyDesc Address of the notification descriptor data str= ucture. + @param InvokePpi Address of the PPI that was invoked. + + @retval EFI_SUCCESS The function completes successfully. + +**/ +EFI_STATUS +EFIAPI +NotifyOnEndOfS3Resume ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, + IN VOID *InvokePpi + ) +{ + CPU_MP_DATA *CpuMpData; + + CpuMpData =3D GetCpuMpData (); + mNumberToFinish =3D CpuMpData->CpuCount - 1; + WakeUpAP (CpuMpData, TRUE, 0, RelocateApLoop, NULL, TRUE); + while (mNumberToFinish > 0) { + CpuPause (); + } + + DEBUG ((DEBUG_INFO, "%a() done!\n", __func__)); + + return EFI_SUCCESS; +} + +// +// Global function +// +EFI_PEI_NOTIFY_DESCRIPTOR mEndOfS3ResumeNotifyDesc =3D { + EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINAT= E_LIST, + &gEdkiiEndOfS3ResumeGuid, + NotifyOnEndOfS3Resume +}; + /** Initialize global data for MP support. @@ -463,12 +505,16 @@ InitMpGlobalData ( BuildMicrocodeCacheHob (CpuMpData); SaveCpuMpData (CpuMpData); + PrepareApLoopCode (CpuMpData); /// /// Install Notify /// Status =3D PeiServicesNotifyPpi (&mS3SmmInitDoneNotifyDesc); ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesNotifyPpi (&mEndOfS3ResumeNotifyDesc); + ASSERT_EFI_ERROR (Status); } /** @@ -815,3 +861,109 @@ PlatformShadowMicrocode ( return EFI_SUCCESS; } + +/** + Allocate buffer for ApLoopCode. + + @param[in] Pages Number of pages to allocate. + @param[in, out] Address Pointer to the allocated buffer. +**/ +VOID +AllocateApLoopCodeBuffer ( + IN UINTN Pages, + IN OUT EFI_PHYSICAL_ADDRESS *Address + ) +{ + EFI_STATUS Status; + + Status =3D PeiServicesAllocatePages (EfiACPIMemoryNVS, Pages, Address); + if (EFI_ERROR (Status)) { + *Address =3D 0; + } +} + +/** + Remove Nx protection for the range specific by BaseAddress and Length. + + The PEI implementation uses CpuPageTableLib to change the attribute. + The DXE implementation uses gDS to change the attribute. + + @param[in] BaseAddress BaseAddress of the range. + @param[in] Length Length of the range. +**/ +VOID +RemoveNxprotection ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINTN Length + ) +{ + EFI_STATUS Status; + UINTN PageTable; + EFI_PHYSICAL_ADDRESS Buffer; + UINTN BufferSize; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + PAGING_MODE PagingMode; + IA32_CR4 Cr4; + BOOLEAN Page5LevelSupport; + UINT32 RegEax; + BOOLEAN Page1GSupport; + CPUID_EXTENDED_CPU_SIG_EDX RegEdx; + + if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { + // + // Check Page5Level Support or not. + // + Cr4.UintN =3D AsmReadCr4 (); + Page5LevelSupport =3D (Cr4.Bits.LA57 ? TRUE : FALSE); + + // + // Check Page1G Support or not. + // + Page1GSupport =3D FALSE; + AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) { + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx.Uint32); + if (RegEdx.Bits.Page1GB !=3D 0) { + Page1GSupport =3D TRUE; + } + } + + // + // Decide Paging Mode according Page5LevelSupport & Page1GSupport. + // + if (Page5LevelSupport) { + PagingMode =3D Page1GSupport ? Paging5Level1GB : Paging5Level; + } else { + PagingMode =3D Page1GSupport ? Paging4Level1GB : Paging4Level; + } + } else { + PagingMode =3D PagingPae; + } + + MapAttribute.Uint64 =3D 0; + MapMask.Uint64 =3D 0; + MapMask.Bits.Nx =3D 1; + PageTable =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; + BufferSize =3D 0; + + // + // Get required buffer size for changing the pagetable. + // + Status =3D PageTableMap (&PageTable, PagingMode, 0, &BufferSize, BaseAdd= ress, Length, &MapAttribute, &MapMask, NULL); + if (Status =3D=3D EFI_BUFFER_TOO_SMALL) { + // + // Allocate required Buffer. + // + Status =3D PeiServicesAllocatePages ( + EfiBootServicesData, + EFI_SIZE_TO_PAGES (BufferSize), + &Buffer + ); + ASSERT_EFI_ERROR (Status); + Status =3D PageTableMap (&PageTable, PagingMode, (VOID *)(UINTN)Buffer= , &BufferSize, BaseAddress, Length, &MapAttribute, &MapMask, NULL); + } + + ASSERT_EFI_ERROR (Status); + AsmWriteCr3 (PageTable); +} -- 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Reviewed-by: Ray Ni <ray.ni@intel.com>

Thanks,
Ray
From: Tan, Dun <dun.tan@= intel.com>
Sent: Friday, May 10, 2024 18:08
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Ni, Ray <ray.ni@intel.com>; Laszlo Ersek <lersek@redhat= .com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; Gerd Hoffmann <= ;kraxel@redhat.com>; Wu, Jiaxin <jiaxin.wu@intel.com>
Subject: [PATCH 10/18] UefiCpuPkg:Relocate AP to new safe buffer in = PeiMpLib
 
In this commit, change PeiMpLib to install callbac= k
of gEdkiiEndOfS3ResumeGuid to relocate AP to new safe
buffer. The gEdkiiEndOfS3ResumeGuid is installed in
S3Resume.c before jmping to OS waking vector.

Previously, code in CpuS3.c of PiSmmCpuDxe driver will
prepare the new safe buffer for AP and place AP in hlt
loop state. With this code change, we can remove the
Machine Instructions of mApHltLoopCode in PiSmmCpuDxe.
Also we can reuse the related code in DxeMpLib for
PeiMpLib.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
---
 UefiCpuPkg/Library/MpInitLib/MpLib.h     &nb= sp;    |   3 +++
 UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf |   4 ++++  UefiCpuPkg/Library/MpInitLib/PeiMpLib.c     =   | 152 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++
 3 files changed, 159 insertions(+)

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h
index 11e0d2661f..3efd913395 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
@@ -33,6 +33,7 @@
 #include <Library/HobLib.h>
 #include <Library/PcdLib.h>
 #include <Library/MicrocodeLib.h>
+#include <Library/CpuPageTableLib.h>
 #include <ConfidentialComputingGuestAttr.h>
 
 #include <Register/Amd/Fam17Msr.h>
@@ -68,6 +69,8 @@
 //
 #define DEFAULT_MAX_MICROCODE_PATCH_NUM  8
 
+#define PAGING_4K_ADDRESS_MASK_64  0x000FFFFFFFFFF000ull
+
 //
 // Data structure for microcode patch information
 //
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf
index e31e34b6f9..8736690348 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
@@ -25,10 +25,12 @@
 [Sources.IA32]
   Ia32/AmdSev.c
   Ia32/MpFuncs.nasm
+  Ia32/CreatePageTable.c
 
 [Sources.X64]
   X64/AmdSev.c
   X64/MpFuncs.nasm
+  X64/CreatePageTable.c
 
 [Sources.IA32, Sources.X64]
   AmdSev.c
@@ -64,6 +66,7 @@
   LocalApicLib
   MicrocodeLib
   MtrrLib
+  CpuPageTableLib
 
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase   &n= bsp;            = ;       ## CONSUMES
@@ -87,6 +90,7 @@
   gEdkiiS3SmmInitDoneGuid
   gEdkiiMicrocodePatchHobGuid
   gGhcbApicIdsGuid       &nbs= p;            &= nbsp;  ## SOMETIMES_CONSUMES
+  gEdkiiEndOfS3ResumeGuid
 
 [Guids.LoongArch64]
   gProcessorResourceHobGuid      &= nbsp;       ## SOMETIMES_CONSUMES  ## HO= B
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/M= pInitLib/PeiMpLib.c
index 4d3acb491f..deb5fc3aac 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
@@ -9,6 +9,7 @@
 #include "MpLib.h"
 #include <Library/PeiServicesLib.h>
 #include <Guid/S3SmmInitDone.h>
+#include <Guid/EndOfS3Resume.h>
 #include <Ppi/ShadowMicrocode.h>
 
 STATIC UINT64  mSevEsPeiWakeupBuffer =3D BASE_1MB;
@@ -449,6 +450,47 @@ BuildMicrocodeCacheHob (
   return;
 }
 
+/**
+  S3 SMM Init Done notification function.
+
+  @param  PeiServices      Indirect ref= erence to the PEI Services Table.
+  @param  NotifyDesc       Address= of the notification descriptor data structure.
+  @param  InvokePpi        Ad= dress of the PPI that was invoked.
+
+  @retval EFI_SUCCESS      The function comp= letes successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NotifyOnEndOfS3Resume (
+  IN  EFI_PEI_SERVICES       =     **PeiServices,
+  IN  EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDesc,
+  IN  VOID         =             &nb= sp; *InvokePpi
+  )
+{
+  CPU_MP_DATA  *CpuMpData;
+
+  CpuMpData       =3D GetCpuMpData ();<= br> +  mNumberToFinish =3D CpuMpData->CpuCount - 1;
+  WakeUpAP (CpuMpData, TRUE, 0, RelocateApLoop, NULL, TRUE);
+  while (mNumberToFinish > 0) {
+    CpuPause ();
+  }
+
+  DEBUG ((DEBUG_INFO, "%a() done!\n", __func__));
+
+  return EFI_SUCCESS;
+}
+
+//
+// Global function
+//
+EFI_PEI_NOTIFY_DESCRIPTOR  mEndOfS3ResumeNotifyDesc =3D {
+  EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TER= MINATE_LIST,
+  &gEdkiiEndOfS3ResumeGuid,
+  NotifyOnEndOfS3Resume
+};
+
 /**
   Initialize global data for MP support.
 
@@ -463,12 +505,16 @@ InitMpGlobalData (
 
   BuildMicrocodeCacheHob (CpuMpData);
   SaveCpuMpData (CpuMpData);
+  PrepareApLoopCode (CpuMpData);
 
   ///
   /// Install Notify
   ///
   Status =3D PeiServicesNotifyPpi (&mS3SmmInitDoneNotifyDesc= );
   ASSERT_EFI_ERROR (Status);
+
+  Status =3D PeiServicesNotifyPpi (&mEndOfS3ResumeNotifyDesc); +  ASSERT_EFI_ERROR (Status);
 }
 
 /**
@@ -815,3 +861,109 @@ PlatformShadowMicrocode (
 
   return EFI_SUCCESS;
 }
+
+/**
+  Allocate buffer for ApLoopCode.
+
+  @param[in]      Pages    Nu= mber of pages to allocate.
+  @param[in, out] Address  Pointer to the allocated buffer.
+**/
+VOID
+AllocateApLoopCodeBuffer (
+  IN UINTN          = ;           Pages,
+  IN OUT EFI_PHYSICAL_ADDRESS  *Address
+  )
+{
+  EFI_STATUS  Status;
+
+  Status =3D PeiServicesAllocatePages (EfiACPIMemoryNVS, Pages, Addre= ss);
+  if (EFI_ERROR (Status)) {
+    *Address =3D 0;
+  }
+}
+
+/**
+  Remove Nx protection for the range specific by BaseAddress and Leng= th.
+
+  The PEI implementation uses CpuPageTableLib to change the attribute= .
+  The DXE implementation uses gDS to change the attribute.
+
+  @param[in] BaseAddress  BaseAddress of the range.
+  @param[in] Length       Length of the= range.
+**/
+VOID
+RemoveNxprotection (
+  IN EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN UINTN          = ;       Length
+  )
+{
+  EFI_STATUS         &nb= sp;        Status;
+  UINTN          &n= bsp;            Page= Table;
+  EFI_PHYSICAL_ADDRESS        Buff= er;
+  UINTN          &n= bsp;            Buff= erSize;
+  IA32_MAP_ATTRIBUTE        &= nbsp; MapAttribute;
+  IA32_MAP_ATTRIBUTE        &= nbsp; MapMask;
+  PAGING_MODE         &n= bsp;       PagingMode;
+  IA32_CR4          = ;          Cr4;
+  BOOLEAN          =            Page5LevelSupp= ort;
+  UINT32          &= nbsp;           RegEax; +  BOOLEAN          =            Page1GSupport;=
+  CPUID_EXTENDED_CPU_SIG_EDX  RegEdx;
+
+  if (sizeof (UINTN) =3D=3D sizeof (UINT64)) {
+    //
+    // Check Page5Level Support or not.
+    //
+    Cr4.UintN       &nbs= p; =3D AsmReadCr4 ();
+    Page5LevelSupport =3D (Cr4.Bits.LA57 ? TRUE : FALSE); +
+    //
+    // Check Page1G Support or not.
+    //
+    Page1GSupport =3D FALSE;
+    AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, N= ULL, NULL);
+    if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) {
+      AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NUL= L, NULL, &RegEdx.Uint32);
+      if (RegEdx.Bits.Page1GB !=3D 0) {
+        Page1GSupport =3D TRUE;
+      }
+    }
+
+    //
+    // Decide Paging Mode according Page5LevelSupport &= Page1GSupport.
+    //
+    if (Page5LevelSupport) {
+      PagingMode =3D Page1GSupport ? Paging5Level= 1GB : Paging5Level;
+    } else {
+      PagingMode =3D Page1GSupport ? Paging4Level= 1GB : Paging4Level;
+    }
+  } else {
+    PagingMode =3D PagingPae;
+  }
+
+  MapAttribute.Uint64 =3D 0;
+  MapMask.Uint64      =3D 0;
+  MapMask.Bits.Nx     =3D 1;
+  PageTable         &nbs= p; =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
+  BufferSize          = =3D 0;
+
+  //
+  // Get required buffer size for changing the pagetable.
+  //
+  Status =3D PageTableMap (&PageTable, PagingMode, 0, &Buffer= Size, BaseAddress, Length, &MapAttribute, &MapMask, NULL);
+  if (Status =3D=3D EFI_BUFFER_TOO_SMALL) {
+    //
+    // Allocate required Buffer.
+    //
+    Status =3D PeiServicesAllocatePages (
+            &n= bsp;  EfiBootServicesData,
+            &n= bsp;  EFI_SIZE_TO_PAGES (BufferSize),
+            &n= bsp;  &Buffer
+            &n= bsp;  );
+    ASSERT_EFI_ERROR (Status);
+    Status =3D PageTableMap (&PageTable, PagingMode, (V= OID *)(UINTN)Buffer, &BufferSize, BaseAddress, Length, &MapAttribut= e, &MapMask, NULL);
+  }
+
+  ASSERT_EFI_ERROR (Status);
+  AsmWriteCr3 (PageTable);
+}
--
2.31.1.windows.1

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