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charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: Jeff Brasen > Sent: Friday, June 30, 2023 11:21 AM > To: Ni, Ray ; devel@edk2.groups.io > Cc: Wang, Jian J ; Gao, Liming > ; Wu, Hao A > Subject: RE: [PATCH] MdeModulePkg/PciHostBridge: Add support for driver > binding >=20 > Not sure why the patch failed to apply I'll see if there is something wro= ng with my > gitconfig tomorrow. The path you suggested below is exactly what our curr= ent > implementation does. However, I am trying to make our pcie controller dri= ver do > async initialization so that using a depex is less ideal as we may have t= o postpone > driver load to after end of dxe instead of just the connection. It seemed= that a > driver binding type approach was a good approach for this. I am curious how the pcie root (root complex) initialization is done in asy= nc way? Does it use a timer callback to poll the initialization status every certai= n interval? On the other hand, even you make PciHostBridge as a UEFI driver-model drive= r, you still require some code to initiate the "ConnectController()". How is that done? Comparing the two paths (today's =3D my proposal, new way =3D your patch), = both require some code to explicitly call "ConnectController()". >=20 > On a less important implementation if the pieces that live under the libr= ary are > driver binding we have to reject any stop requests as there is no driver = linkage > between the two layers. In x86, root complex (pcie root) is almost the root of all peripherals. I c= annot see a value to Stop () the pcie root. If you check the PciBus implementation, it supports Stop() but the Stop() o= nly succeeds when all upper layer drivers succeed to Stop(). (usually it's not the case.) And even PciBus.Stop() succeeds, the resource(MMIO/IO/BUS) allocation is no= t un-done. It's only the PciIo handles that are destroyed in software level. Thanks, Ray >=20 > -Jeff >=20 >=20 > -----Original Message----- > From: Ni, Ray > Sent: Thursday, June 29, 2023 8:29 PM > To: Jeff Brasen ; devel@edk2.groups.io > Cc: Wang, Jian J ; Gao, Liming > ; Wu, Hao A > Subject: RE: [PATCH] MdeModulePkg/PciHostBridge: Add support for driver > binding >=20 > External email: Use caution opening links or attachments >=20 >=20 > I failed to apply the patch in my local tree. >=20 > It seems you invented a new EdkiiRootBridgeIo protocol and a certain prop= rietary > driver would produce this protocol instance. > Then the open source PciHostBridge driver starts on that. >=20 > Then, why not implement your own PciHostBridgeLib and let it depends on s= ome > "AllRootBridgeIoInformationIsReady" protocol. > So that the PciHostBridge driver could still call PciHostBridgeLib and al= l your > implementation in this patch can be in that lib. >=20 > Thanks, > Ray >=20 > > -----Original Message----- > > From: Jeff Brasen > > Sent: Friday, June 30, 2023 4:54 AM > > To: devel@edk2.groups.io > > Cc: Wang, Jian J ; Gao, Liming > > ; Wu, Hao A ; Ni, Ray > > ; Jeff Brasen > > Subject: [PATCH] MdeModulePkg/PciHostBridge: Add support for driver > > binding > > > > If the platform does not support any PCIe devices using the library > > > > method allow devices to connect to host bridge via driver binding. > > > > > > > > Signed-off-by: Jeff Brasen > > > > --- > > > > .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 649 > > ++++++++++++++---- > > > > .../Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf | 1 + > > > > .../Bus/Pci/PciHostBridgeDxe/PciRootBridge.h | 13 + > > > > .../Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 24 + > > > > MdeModulePkg/MdeModulePkg.dec | 4 + > > > > 5 files changed, 562 insertions(+), 129 deletions(-) > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c > > b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c > > > > index d573e532ba..506c6660ae 100644 > > > > --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c > > > > +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c > > > > @@ -422,167 +422,320 @@ IoMmuProtocolCallback ( > > > > } > > > > > > > > /** > > > > + PCI Root Bridge Memory setup. > > > > > > > > - Entry point of this driver. > > > > + @param RootBridge Root Bridge instance. > > > > > > > > - @param ImageHandle Image handle of this driver. > > > > - @param SystemTable Pointer to standard EFI system table. > > > > - > > > > - @retval EFI_SUCCESS Succeed. > > > > - @retval EFI_DEVICE_ERROR Fail to install PCI_ROOT_BRIDGE_IO protoco= l. > > > > + @retval EFI_SUCCESS Memory was setup correctly > > > > + @retval others Error in setup > > > > > > > > **/ > > > > EFI_STATUS > > > > EFIAPI > > > > -InitializePciHostBridge ( > > > > - IN EFI_HANDLE ImageHandle, > > > > - IN EFI_SYSTEM_TABLE *SystemTable > > > > +PciRootBridgeMemorySetup ( > > > > + IN PCI_ROOT_BRIDGE *RootBridge > > > > ) > > > > { > > > > EFI_STATUS Status; > > > > - PCI_HOST_BRIDGE_INSTANCE *HostBridge; > > > > - PCI_ROOT_BRIDGE_INSTANCE *RootBridge; > > > > - PCI_ROOT_BRIDGE *RootBridges; > > > > - UINTN RootBridgeCount; > > > > - UINTN Index; > > > > + UINT64 HostAddress; > > > > PCI_ROOT_BRIDGE_APERTURE *MemApertures[4]; > > > > UINTN MemApertureIndex; > > > > - BOOLEAN ResourceAssigned; > > > > - LIST_ENTRY *Link; > > > > - UINT64 HostAddress; > > > > > > > > - RootBridges =3D PciHostBridgeGetRootBridges (&RootBridgeCount); > > > > - if ((RootBridges =3D=3D NULL) || (RootBridgeCount =3D=3D 0)) { > > > > - return EFI_UNSUPPORTED; > > > > - } > > > > - > > > > - Status =3D gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID > > **)&mCpuIo); > > > > - ASSERT_EFI_ERROR (Status); > > > > - > > > > - // > > > > - // Most systems in the world including complex servers have only > > one Host Bridge. > > > > - // > > > > - HostBridge =3D AllocateZeroPool (sizeof (PCI_HOST_BRIDGE_INSTANCE)); > > > > - ASSERT (HostBridge !=3D NULL); > > > > - > > > > - HostBridge->Signature =3D PCI_HOST_BRIDGE_SIGNATURE; > > > > - HostBridge->CanRestarted =3D TRUE; > > > > - InitializeListHead (&HostBridge->RootBridges); > > > > - ResourceAssigned =3D FALSE; > > > > - > > > > - // > > > > - // Create Root Bridge Device Handle in this Host Bridge > > > > - // > > > > - for (Index =3D 0; Index < RootBridgeCount; Index++) { > > > > + if (RootBridge->Io.Base <=3D RootBridge->Io.Limit) { > > > > // > > > > - // Create Root Bridge Handle Instance > > > > + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. > > > > + // For GCD resource manipulation, we need to use host address. > > > > // > > > > - RootBridge =3D CreateRootBridge (&RootBridges[Index]); > > > > - ASSERT (RootBridge !=3D NULL); > > > > - if (RootBridge =3D=3D NULL) { > > > > - continue; > > > > + HostAddress =3D TO_HOST_ADDRESS ( > > > > + RootBridge->Io.Base, > > > > + RootBridge->Io.Translation > > > > + ); > > > > + > > > > + Status =3D AddIoSpace ( > > > > + HostAddress, > > > > + RootBridge->Io.Limit - RootBridge->Io.Base + 1 > > > > + ); > > > > + ASSERT_EFI_ERROR (Status); > > > > + if (EFI_ERROR (Status)) { > > > > + return Status; > > > > } > > > > > > > > - // > > > > - // Make sure all root bridges share the same ResourceAssigned valu= e. > > > > - // > > > > - if (Index =3D=3D 0) { > > > > - ResourceAssigned =3D RootBridges[Index].ResourceAssigned; > > > > - } else { > > > > - ASSERT (ResourceAssigned =3D=3D RootBridges[Index].ResourceAssig= ned); > > > > + if (RootBridge->ResourceAssigned) { > > > > + Status =3D gDS->AllocateIoSpace ( > > > > + EfiGcdAllocateAddress, > > > > + EfiGcdIoTypeIo, > > > > + 0, > > > > + RootBridge->Io.Limit - RootBridge->Io.Base + 1, > > > > + &HostAddress, > > > > + gImageHandle, > > > > + NULL > > > > + ); > > > > + ASSERT_EFI_ERROR (Status); > > > > + if (EFI_ERROR (Status)) { > > > > + return Status; > > > > + } > > > > } > > > > + } > > > > + > > > > + // > > > > + // Add all the Mem/PMem aperture to GCD > > > > + // Mem/PMem shouldn't overlap with each other > > > > + // Root bridge which needs to combine MEM and PMEM should only > > + report > > > > + // the MEM aperture in Mem > > > > + // > > > > + MemApertures[0] =3D &RootBridge->Mem; > > > > + MemApertures[1] =3D &RootBridge->MemAbove4G; > > > > + MemApertures[2] =3D &RootBridge->PMem; > > > > + MemApertures[3] =3D &RootBridge->PMemAbove4G; > > > > > > > > - if (RootBridges[Index].Io.Base <=3D RootBridges[Index].Io.Limit) { > > > > + for (MemApertureIndex =3D 0; MemApertureIndex < ARRAY_SIZE > > (MemApertures); MemApertureIndex++) { > > > > + if (MemApertures[MemApertureIndex]->Base <=3D > > MemApertures[MemApertureIndex]->Limit) { > > > > // > > > > // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address= . > > > > // For GCD resource manipulation, we need to use host address. > > > > // > > > > HostAddress =3D TO_HOST_ADDRESS ( > > > > - RootBridges[Index].Io.Base, > > > > - RootBridges[Index].Io.Translation > > > > + MemApertures[MemApertureIndex]->Base, > > > > + MemApertures[MemApertureIndex]->Translation > > > > ); > > > > - > > > > - Status =3D AddIoSpace ( > > > > + Status =3D AddMemoryMappedIoSpace ( > > > > HostAddress, > > > > - RootBridges[Index].Io.Limit - RootBridges[Index].Io.B= ase + 1 > > > > + MemApertures[MemApertureIndex]->Limit - > > MemApertures[MemApertureIndex]->Base + 1, > > > > + EFI_MEMORY_UC > > > > ); > > > > ASSERT_EFI_ERROR (Status); > > > > - if (ResourceAssigned) { > > > > - Status =3D gDS->AllocateIoSpace ( > > > > + if (EFI_ERROR (Status)) { > > > > + return Status; > > > > + } > > > > + > > > > + Status =3D gDS->SetMemorySpaceAttributes ( > > > > + HostAddress, > > > > + MemApertures[MemApertureIndex]->Limit - > > MemApertures[MemApertureIndex]->Base + 1, > > > > + EFI_MEMORY_UC > > > > + ); > > > > + if (EFI_ERROR (Status)) { > > > > + DEBUG ((DEBUG_WARN, "PciHostBridge driver failed to set > > EFI_MEMORY_UC to MMIO aperture - %r.\n", Status)); > > > > + } > > > > + > > > > + if (RootBridge->ResourceAssigned) { > > > > + Status =3D gDS->AllocateMemorySpace ( > > > > EfiGcdAllocateAddress, > > > > - EfiGcdIoTypeIo, > > > > + EfiGcdMemoryTypeMemoryMappedIo, > > > > 0, > > > > - RootBridges[Index].Io.Limit - RootBridges[Inde= x].Io.Base + 1, > > > > + MemApertures[MemApertureIndex]->Limit - > > MemApertures[MemApertureIndex]->Base + 1, > > > > &HostAddress, > > > > gImageHandle, > > > > NULL > > > > ); > > > > ASSERT_EFI_ERROR (Status); > > > > + if (EFI_ERROR (Status)) { > > > > + return Status; > > > > + } > > > > } > > > > } > > > > + } > > > > + > > > > + return EFI_SUCCESS; > > > > +} > > > > > > > > +/** > > > > + PCI Root Bridge Memory free. > > > > + > > > > + @param RootBridge Root Bridge instance. > > > > + > > > > + @retval EFI_SUCCESS Memory was setup correctly > > > > + @retval others Error in setup > > > > + > > > > +**/ > > > > +EFI_STATUS > > > > +EFIAPI > > > > +PciRootBridgeMemoryFree ( > > > > + IN PCI_ROOT_BRIDGE *RootBridge > > > > + ) > > > > +{ > > > > + EFI_STATUS Status; > > > > + UINT64 HostAddress; > > > > + PCI_ROOT_BRIDGE_APERTURE *MemApertures[4]; > > > > + UINTN MemApertureIndex; > > > > + > > > > + if (RootBridge->Io.Base <=3D RootBridge->Io.Limit) { > > > > // > > > > - // Add all the Mem/PMem aperture to GCD > > > > - // Mem/PMem shouldn't overlap with each other > > > > - // Root bridge which needs to combine MEM and PMEM should only rep= ort > > > > - // the MEM aperture in Mem > > > > + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. > > > > + // For GCD resource manipulation, we need to use host address. > > > > // > > > > - MemApertures[0] =3D &RootBridges[Index].Mem; > > > > - MemApertures[1] =3D &RootBridges[Index].MemAbove4G; > > > > - MemApertures[2] =3D &RootBridges[Index].PMem; > > > > - MemApertures[3] =3D &RootBridges[Index].PMemAbove4G; > > > > - > > > > - for (MemApertureIndex =3D 0; MemApertureIndex < ARRAY_SIZE > > (MemApertures); MemApertureIndex++) { > > > > - if (MemApertures[MemApertureIndex]->Base <=3D > > MemApertures[MemApertureIndex]->Limit) { > > > > - // > > > > - // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device addre= ss. > > > > - // For GCD resource manipulation, we need to use host address. > > > > - // > > > > - HostAddress =3D TO_HOST_ADDRESS ( > > > > - MemApertures[MemApertureIndex]->Base, > > > > - MemApertures[MemApertureIndex]->Translation > > > > - ); > > > > - Status =3D AddMemoryMappedIoSpace ( > > > > - HostAddress, > > > > - MemApertures[MemApertureIndex]->Limit - > > MemApertures[MemApertureIndex]->Base + 1, > > > > - EFI_MEMORY_UC > > > > - ); > > > > + HostAddress =3D TO_HOST_ADDRESS ( > > > > + RootBridge->Io.Base, > > > > + RootBridge->Io.Translation > > > > + ); > > > > + > > > > + if (RootBridge->ResourceAssigned) { > > > > + Status =3D gDS->FreeIoSpace (HostAddress, RootBridge->Io.Limit - > > + RootBridge- > > >Io.Base + 1); > > > > + ASSERT_EFI_ERROR (Status); > > > > + if (EFI_ERROR (Status)) { > > > > + return Status; > > > > + } > > > > + } > > > > + } > > > > + > > > > + // > > > > + // Add all the Mem/PMem aperture to GCD > > > > + // Mem/PMem shouldn't overlap with each other > > > > + // Root bridge which needs to combine MEM and PMEM should only > > + report > > > > + // the MEM aperture in Mem > > > > + // > > > > + MemApertures[0] =3D &RootBridge->Mem; > > > > + MemApertures[1] =3D &RootBridge->MemAbove4G; > > > > + MemApertures[2] =3D &RootBridge->PMem; > > > > + MemApertures[3] =3D &RootBridge->PMemAbove4G; > > > > + > > > > + for (MemApertureIndex =3D 0; MemApertureIndex < ARRAY_SIZE > > (MemApertures); MemApertureIndex++) { > > > > + if (MemApertures[MemApertureIndex]->Base <=3D > > MemApertures[MemApertureIndex]->Limit) { > > > > + // > > > > + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address= . > > > > + // For GCD resource manipulation, we need to use host address. > > > > + // > > > > + HostAddress =3D TO_HOST_ADDRESS ( > > > > + MemApertures[MemApertureIndex]->Base, > > > > + MemApertures[MemApertureIndex]->Translation > > > > + ); > > > > + if (RootBridge->ResourceAssigned) { > > > > + Status =3D gDS->FreeMemorySpace (HostAddress, > > + RootBridge->Io.Limit - > > RootBridge->Io.Base + 1); > > > > ASSERT_EFI_ERROR (Status); > > > > - Status =3D gDS->SetMemorySpaceAttributes ( > > > > - HostAddress, > > > > - MemApertures[MemApertureIndex]->Limit - > > MemApertures[MemApertureIndex]->Base + 1, > > > > - EFI_MEMORY_UC > > > > - ); > > > > if (EFI_ERROR (Status)) { > > > > - DEBUG ((DEBUG_WARN, "PciHostBridge driver failed to set > > EFI_MEMORY_UC to MMIO aperture - %r.\n", Status)); > > > > - } > > > > - > > > > - if (ResourceAssigned) { > > > > - Status =3D gDS->AllocateMemorySpace ( > > > > - EfiGcdAllocateAddress, > > > > - EfiGcdMemoryTypeMemoryMappedIo, > > > > - 0, > > > > - MemApertures[MemApertureIndex]->Limit - > > MemApertures[MemApertureIndex]->Base + 1, > > > > - &HostAddress, > > > > - gImageHandle, > > > > - NULL > > > > - ); > > > > - ASSERT_EFI_ERROR (Status); > > > > + return Status; > > > > } > > > > } > > > > } > > > > + } > > > > > > > > - // > > > > - // Insert Root Bridge Handle Instance > > > > - // > > > > - InsertTailList (&HostBridge->RootBridges, &RootBridge->Link); > > > > + return EFI_SUCCESS; > > > > +} > > > > + > > > > +/** > > > > + Test to see if this driver supports ControllerHandle. Any > > + ControllerHandle > > > > + than contains a gEdkiiPciHostBridgeProtocolGuid protocol can be supp= orted. > > > > + > > > > + @param This Protocol instance pointer. > > > > + @param Controller Handle of device to test. > > > > + @param RemainingDevicePath Optional parameter use to pick a > > + specific child > > > > + device to start. > > > > + > > > > + @retval EFI_SUCCESS This driver supports this device. > > > > + @retval EFI_ALREADY_STARTED This driver is already running on this d= evice. > > > > + @retval other This driver does not support this device= . > > > > + > > > > +**/ > > > > +EFI_STATUS > > > > +EFIAPI > > > > +PciHostBrigeDriverBindingSupported ( > > > > + IN EFI_DRIVER_BINDING_PROTOCOL *This, > > > > + IN EFI_HANDLE Controller, > > > > + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath > > > > + ) > > > > +{ > > > > + EFI_STATUS Status; > > > > + PCI_ROOT_BRIDGE *PciRootBridge; > > > > + > > > > + // > > > > + // Check if Pci Host Bridge protocol is installed by platform > > > > + // > > > > + Status =3D gBS->OpenProtocol ( > > > > + Controller, > > > > + &gEdkiiPciHostBridgeProtocolGuid, > > > > + (VOID **)&PciRootBridge, > > > > + This->DriverBindingHandle, > > > > + Controller, > > > > + EFI_OPEN_PROTOCOL_BY_DRIVER > > > > + ); > > > > + if (EFI_ERROR (Status)) { > > > > + return Status; > > > > } > > > > > > > > // > > > > - // When resources were assigned, it's not needed to expose > > > > - // PciHostBridgeResourceAllocation protocol. > > > > + // Close the protocol used to perform the supported test > > > > + // > > > > + gBS->CloseProtocol ( > > > > + Controller, > > > > + &gEdkiiPciHostBridgeProtocolGuid, > > > > + This->DriverBindingHandle, > > > > + Controller > > > > + ); > > > > + > > > > + return EFI_SUCCESS; > > > > +} > > > > + > > > > +/** > > > > + Start this driver on ControllerHandle and enumerate Pci bus and > > + start > > > > + all device under PCI bus. > > > > + > > > > + @param This Protocol instance pointer. > > > > + @param Controller Handle of device to bind driver to. > > > > + @param RemainingDevicePath Optional parameter use to pick a > > + specific child > > > > + device to start. > > > > + > > > > + @retval EFI_SUCCESS This driver is added to ControllerHandl= e. > > > > + @retval EFI_ALREADY_STARTED This driver is already running on > > ControllerHandle. > > > > + @retval other This driver does not support this devic= e. > > > > + > > > > +**/ > > > > +EFI_STATUS > > > > +EFIAPI > > > > +PciHostBrigeDriverBindingStart ( > > > > + IN EFI_DRIVER_BINDING_PROTOCOL *This, > > > > + IN EFI_HANDLE Controller, > > > > + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath > > > > + ) > > > > +{ > > > > + EFI_STATUS Status; > > > > + PCI_ROOT_BRIDGE *PciRootBridge; > > > > + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; > > > > + PCI_HOST_BRIDGE_INSTANCE *HostBridge; > > > > + BOOLEAN MemorySetupDone; > > > > + > > > > + MemorySetupDone =3D FALSE; > > > > + // > > > > + // Check if Pci Host Bridge protocol is installed by platform > > > > // > > > > - if (!ResourceAssigned) { > > > > + Status =3D gBS->OpenProtocol ( > > > > + Controller, > > > > + &gEdkiiPciHostBridgeProtocolGuid, > > > > + (VOID **)&PciRootBridge, > > > > + This->DriverBindingHandle, > > > > + Controller, > > > > + EFI_OPEN_PROTOCOL_BY_DRIVER > > > > + ); > > > > + if (EFI_ERROR (Status)) { > > > > + return Status; > > > > + } > > > > + > > > > + RootBridge =3D CreateRootBridge (PciRootBridge); > > > > + ASSERT (RootBridge !=3D NULL); > > > > + if (RootBridge =3D=3D NULL) { > > > > + Status =3D EFI_DEVICE_ERROR; > > > > + goto ErrorExit; > > > > + } > > > > + > > > > + Status =3D PciRootBridgeMemorySetup (PciRootBridge); > > > > + if (EFI_ERROR (Status)) { > > > > + goto ErrorExit; > > > > + } > > > > + > > > > + MemorySetupDone =3D TRUE; > > > > + > > > > + if (!PciRootBridge->ResourceAssigned) { > > > > + // Create host bridge > > > > + HostBridge =3D AllocateZeroPool (sizeof > > + (PCI_HOST_BRIDGE_INSTANCE)); > > > > + ASSERT (HostBridge !=3D NULL); > > > > + if (HostBridge =3D=3D NULL) { > > > > + Status =3D EFI_OUT_OF_RESOURCES; > > > > + goto ErrorExit; > > > > + } > > > > + > > > > + HostBridge->Handle =3D 0; > > > > + HostBridge->Signature =3D PCI_HOST_BRIDGE_SIGNATURE; > > > > + HostBridge->CanRestarted =3D TRUE; > > > > + InitializeListHead (&HostBridge->RootBridges); > > > > + > > > > HostBridge->ResAlloc.NotifyPhase =3D NotifyPhase; > > > > HostBridge->ResAlloc.GetNextRootBridge =3D GetNextRootBridge; > > > > HostBridge->ResAlloc.GetAllocAttributes =3D GetAttributes; > > > > @@ -599,28 +752,266 @@ InitializePciHostBridge ( > > > > NULL > > > > ); > > > > ASSERT_EFI_ERROR (Status); > > > > - } > > > > + if (EFI_ERROR (Status)) { > > > > + goto ErrorExit; > > > > + } > > > > > > > > - for (Link =3D GetFirstNode (&HostBridge->RootBridges) > > > > - ; !IsNull (&HostBridge->RootBridges, Link) > > > > - ; Link =3D GetNextNode (&HostBridge->RootBridges, Link) > > > > - ) > > > > - { > > > > - RootBridge =3D ROOT_BRIDGE_FROM_LINK (L= ink); > > > > + // > > > > + // Insert Root Bridge Handle Instance > > > > + // > > > > + InsertTailList (&HostBridge->RootBridges, &RootBridge->Link); > > > > RootBridge->RootBridgeIo.ParentHandle =3D HostBridge->Handle; > > > > + } else { > > > > + RootBridge->RootBridgeIo.ParentHandle =3D 0; > > > > + } > > > > > > > > - Status =3D gBS->InstallMultipleProtocolInterfaces ( > > > > - &RootBridge->Handle, > > > > - &gEfiDevicePathProtocolGuid, > > > > - RootBridge->DevicePath, > > > > - &gEfiPciRootBridgeIoProtocolGuid, > > > > - &RootBridge->RootBridgeIo, > > > > - NULL > > > > - ); > > > > - ASSERT_EFI_ERROR (Status); > > > > + RootBridge->Handle =3D Controller; > > > > + Status =3D gBS->InstallMultipleProtocolInterfaces ( > > > > + &RootBridge->Handle, > > > > + &gEfiPciRootBridgeIoProtocolGuid, > > > > + &RootBridge->RootBridgeIo, > > > > + NULL > > > > + ); > > > > + > > > > +ErrorExit: > > > > + if (EFI_ERROR (Status)) { > > > > + if (MemorySetupDone) { > > > > + PciRootBridgeMemoryFree (PciRootBridge); > > > > + } > > > > + > > > > + if (RootBridge !=3D NULL) { > > > > + if (!IsListEmpty (&RootBridge->Link)) { > > > > + RemoveEntryList (&RootBridge->Link); > > > > + } > > > > + > > > > + FreeRootBridge (RootBridge); > > > > + } > > > > + > > > > + gBS->CloseProtocol ( > > > > + Controller, > > > > + &gEdkiiPciHostBridgeProtocolGuid, > > > > + This->DriverBindingHandle, > > > > + Controller > > > > + ); > > > > } > > > > > > > > - PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount); > > > > + return Status; > > > > +} > > > > + > > > > +/** > > > > + Stop this driver on ControllerHandle. Support stopping any child > > + handles > > > > + created by this driver. > > > > + > > > > + @param This Protocol instance pointer. > > > > + @param Controller Handle of device to stop driver on. > > > > + @param NumberOfChildren Number of Handles in ChildHandleBuffer. > > + If > > number of > > > > + children is zero stop the entire bus drive= r. > > > > + @param ChildHandleBuffer List of Child Handles to Stop. > > > > + > > > > + @retval EFI_SUCCESS This driver is removed ControllerHandle. > > > > + @retval other This driver was not removed from this devi= ce. > > > > + > > > > +**/ > > > > +EFI_STATUS > > > > +EFIAPI > > > > +PciHostBrigeDriverBindingStop ( > > > > + IN EFI_DRIVER_BINDING_PROTOCOL *This, > > > > + IN EFI_HANDLE Controller, > > > > + IN UINTN NumberOfChildren, > > > > + IN EFI_HANDLE *ChildHandleBuffer > > > > + ) > > > > +{ > > > > + EFI_STATUS Status; > > > > + PCI_ROOT_BRIDGE *PciRootBridge; > > > > + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; > > > > + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo; > > > > + > > > > + Status =3D gBS->HandleProtocol ( > > > > + Controller, > > > > + &gEfiPciRootBridgeIoProtocolGuid, > > > > + (VOID **)&RootBridgeIo > > > > + ); > > > > + if (EFI_ERROR (Status)) { > > > > + return Status; > > > > + } > > > > + > > > > + RootBridge =3D ROOT_BRIDGE_FROM_THIS (RootBridgeIo); > > > > + > > > > + Status =3D gBS->HandleProtocol ( > > > > + Controller, > > > > + &gEdkiiPciHostBridgeProtocolGuid, > > > > + (VOID **)&PciRootBridge > > > > + ); > > > > + if (EFI_ERROR (Status)) { > > > > + return Status; > > > > + } > > > > + > > > > + Status =3D gBS->UninstallMultipleProtocolInterfaces ( > > > > + Controller, > > > > + &gEfiPciRootBridgeIoProtocolGuid, > > > > + (VOID **)&PciRootBridge > > > > + ); > > > > + if (EFI_ERROR (Status)) { > > > > + return Status; > > > > + } > > > > + > > > > + if (!IsListEmpty (&RootBridge->Link)) { > > > > + RemoveEntryList (&RootBridge->Link); > > > > + } > > > > + > > > > + PciRootBridgeMemoryFree (PciRootBridge); > > > > + > > > > + FreeRootBridge (RootBridge); > > > > + gBS->CloseProtocol ( > > > > + Controller, > > > > + &gEdkiiPciHostBridgeProtocolGuid, > > > > + This->DriverBindingHandle, > > > > + Controller > > > > + ); > > > > + return EFI_SUCCESS; > > > > +} > > > > + > > > > +// > > > > +// PCI Bus Driver Global Variables > > > > +// > > > > +EFI_DRIVER_BINDING_PROTOCOL gPciHostBrigeDriverBinding =3D { > > > > + PciHostBrigeDriverBindingSupported, > > > > + PciHostBrigeDriverBindingStart, > > > > + PciHostBrigeDriverBindingStop, > > > > + 0xa, > > > > + NULL, > > > > + NULL > > > > +}; > > > > + > > > > +/** > > > > + > > > > + Entry point of this driver. > > > > + > > > > + @param ImageHandle Image handle of this driver. > > > > + @param SystemTable Pointer to standard EFI system table. > > > > + > > > > + @retval EFI_SUCCESS Succeed. > > > > + @retval EFI_DEVICE_ERROR Fail to install PCI_ROOT_BRIDGE_IO protoco= l. > > > > + > > > > +**/ > > > > +EFI_STATUS > > > > +EFIAPI > > > > +InitializePciHostBridge ( > > > > + IN EFI_HANDLE ImageHandle, > > > > + IN EFI_SYSTEM_TABLE *SystemTable > > > > + ) > > > > +{ > > > > + EFI_STATUS Status; > > > > + PCI_HOST_BRIDGE_INSTANCE *HostBridge; > > > > + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; > > > > + PCI_ROOT_BRIDGE *RootBridges; > > > > + UINTN RootBridgeCount; > > > > + UINTN Index; > > > > + BOOLEAN ResourceAssigned; > > > > + LIST_ENTRY *Link; > > > > + > > > > + Status =3D gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID > > **)&mCpuIo); > > > > + ASSERT_EFI_ERROR (Status); > > > > + > > > > + RootBridges =3D PciHostBridgeGetRootBridges (&RootBridgeCount); > > > > + if ((RootBridges =3D=3D NULL) || (RootBridgeCount =3D=3D 0)) { > > > > + // Register for binding protocol if library enumeration is not > > + used > > > > + Status =3D EfiLibInstallDriverBinding ( > > > > + ImageHandle, > > > > + SystemTable, > > > > + &gPciHostBrigeDriverBinding, > > > > + ImageHandle > > > > + ); > > > > + ASSERT_EFI_ERROR (Status); > > > > + } else { > > > > + // > > > > + // Most systems in the world including complex servers have only > > + one Host > > Bridge. > > > > + // > > > > + HostBridge =3D AllocateZeroPool (sizeof > > + (PCI_HOST_BRIDGE_INSTANCE)); > > > > + ASSERT (HostBridge !=3D NULL); > > > > + > > > > + HostBridge->Signature =3D PCI_HOST_BRIDGE_SIGNATURE; > > > > + HostBridge->CanRestarted =3D TRUE; > > > > + InitializeListHead (&HostBridge->RootBridges); > > > > + ResourceAssigned =3D FALSE; > > > > + > > > > + // > > > > + // Create Root Bridge Device Handle in this Host Bridge > > > > + // > > > > + for (Index =3D 0; Index < RootBridgeCount; Index++) { > > > > + // > > > > + // Create Root Bridge Handle Instance > > > > + // > > > > + RootBridge =3D CreateRootBridge (&RootBridges[Index]); > > > > + ASSERT (RootBridge !=3D NULL); > > > > + if (RootBridge =3D=3D NULL) { > > > > + continue; > > > > + } > > > > + > > > > + // > > > > + // Make sure all root bridges share the same ResourceAssigned va= lue. > > > > + // > > > > + if (Index =3D=3D 0) { > > > > + ResourceAssigned =3D RootBridges[Index].ResourceAssigned; > > > > + } else { > > > > + ASSERT (ResourceAssigned =3D=3D > > + RootBridges[Index].ResourceAssigned); > > > > + } > > > > + > > > > + Status =3D PciRootBridgeMemorySetup (&RootBridges[Index]); > > > > + if (EFI_ERROR (Status)) { > > > > + continue; > > > > + } > > > > + > > > > + // > > > > + // Insert Root Bridge Handle Instance > > > > + // > > > > + InsertTailList (&HostBridge->RootBridges, &RootBridge->Link); > > > > + } > > > > + > > > > + // > > > > + // When resources were assigned, it's not needed to expose > > > > + // PciHostBridgeResourceAllocation protocol. > > > > + // > > > > + if (!ResourceAssigned) { > > > > + HostBridge->ResAlloc.NotifyPhase =3D NotifyPhase; > > > > + HostBridge->ResAlloc.GetNextRootBridge =3D GetNextRootBridge; > > > > + HostBridge->ResAlloc.GetAllocAttributes =3D GetAttributes; > > > > + HostBridge->ResAlloc.StartBusEnumeration =3D > > + StartBusEnumeration; > > > > + HostBridge->ResAlloc.SetBusNumbers =3D SetBusNumbers; > > > > + HostBridge->ResAlloc.SubmitResources =3D SubmitResources; > > > > + HostBridge->ResAlloc.GetProposedResources =3D > > + GetProposedResources; > > > > + HostBridge->ResAlloc.PreprocessController =3D > > + PreprocessController; > > > > + > > > > + Status =3D gBS->InstallMultipleProtocolInterfaces ( > > > > + &HostBridge->Handle, > > > > + > > + &gEfiPciHostBridgeResourceAllocationProtocolGuid, > > > > + &HostBridge->ResAlloc, > > > > + NULL > > > > + ); > > > > + ASSERT_EFI_ERROR (Status); > > > > + } > > > > + > > > > + for (Link =3D GetFirstNode (&HostBridge->RootBridges) > > > > + ; !IsNull (&HostBridge->RootBridges, Link) > > > > + ; Link =3D GetNextNode (&HostBridge->RootBridges, Link) > > > > + ) > > > > + { > > > > + RootBridge =3D ROOT_BRIDGE_FROM_LINK = (Link); > > > > + RootBridge->RootBridgeIo.ParentHandle =3D HostBridge->Handle; > > > > + > > > > + Status =3D gBS->InstallMultipleProtocolInterfaces ( > > > > + &RootBridge->Handle, > > > > + &gEfiDevicePathProtocolGuid, > > > > + RootBridge->DevicePath, > > > > + &gEfiPciRootBridgeIoProtocolGuid, > > > > + &RootBridge->RootBridgeIo, > > > > + NULL > > > > + ); > > > > + ASSERT_EFI_ERROR (Status); > > > > + } > > > > + > > > > + PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount); > > > > + } > > > > > > > > if (!EFI_ERROR (Status)) { > > > > mIoMmuEvent =3D EfiCreateProtocolNotifyEvent ( > > > > diff --git > > a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > > b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > > > > index 9c24cacc30..ee4740b14f 100644 > > > > --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > > > > +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > > > > @@ -46,6 +46,7 @@ > > > > gEfiPciRootBridgeIoProtocolGuid ## BY_START > > > > gEfiPciHostBridgeResourceAllocationProtocolGuid ## BY_START > > > > gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUME= S > > > > + gEdkiiPciHostBridgeProtocolGuid ## SOMETIMES_CONSUME= S > > > > > > > > [Depex] > > > > gEfiCpuIo2ProtocolGuid AND > > > > diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h > > b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h > > > > index 10a6200719..7923c4677b 100644 > > > > --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h > > > > +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h > > > > @@ -93,6 +93,19 @@ CreateRootBridge ( > > > > IN PCI_ROOT_BRIDGE *Bridge > > > > ); > > > > > > > > +/** > > > > + Free the Pci Root Bridge instance. > > > > + > > > > + @param Bridge The root bridge instance. > > > > + > > > > + @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created > > > > + or NULL if creation fails. > > > > +**/ > > > > +VOID > > > > +FreeRootBridge ( > > > > + IN PCI_ROOT_BRIDGE_INSTANCE *Bridge > > > > + ); > > > > + > > > > // > > > > // Protocol Member Function Prototypes > > > > // > > > > diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c > > b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c > > > > index 157a0ada80..f0eb465a9d 100644 > > > > --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c > > > > +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c > > > > @@ -286,6 +286,30 @@ CreateRootBridge ( > > > > return RootBridge; > > > > } > > > > > > > > +/** > > > > + Free the Pci Root Bridge instance. > > > > + > > > > + @param Bridge The root bridge instance. > > > > + > > > > + @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created > > > > + or NULL if creation fails. > > > > +**/ > > > > +VOID > > > > +FreeRootBridge ( > > > > + IN PCI_ROOT_BRIDGE_INSTANCE *Bridge > > > > + ) > > > > +{ > > > > + if (Bridge->ConfigBuffer !=3D NULL) { > > > > + FreePool (Bridge->ConfigBuffer); > > > > + } > > > > + > > > > + if (Bridge->DevicePath !=3D NULL) { > > > > + FreePool (Bridge->DevicePath); > > > > + } > > > > + > > > > + FreePool (Bridge); > > > > +} > > > > + > > > > /** > > > > Check parameters for IO,MMIO,PCI read/write services of PCI Root Bri= dge IO. > > > > > > > > diff --git a/MdeModulePkg/MdeModulePkg.dec > > b/MdeModulePkg/MdeModulePkg.dec > > > > index d65dae18aa..24700fa797 100644 > > > > --- a/MdeModulePkg/MdeModulePkg.dec > > > > +++ b/MdeModulePkg/MdeModulePkg.dec > > > > @@ -692,6 +692,10 @@ > > > > ## Include/Protocol/VariablePolicy.h > > > > gEdkiiVariablePolicyProtocolGuid =3D { 0x81D1675C, 0x86F6, 0x48DF, { > > 0xBD, 0x95, 0x9A, 0x6E, 0x4F, 0x09, 0x25, 0xC3 } } > > > > > > > > + ## Include/Library/PciHostBridgeLib.h > > > > + # Exposes a PCI_HOST_BRIDGE structure for driver binding usage > > > > + gEdkiiPciHostBridgeProtocolGuid =3D { 0xaff2b72d, 0x202e, 0x40e3, { > > + 0x82, 0xd5, > > 0x9f, 0x6f, 0x61, 0xaf, 0x2a, 0x0b } } > > > > + > > > > [PcdsFeatureFlag] > > > > ## Indicates if the platform can support update capsule across a > > system reset.

> > > > # TRUE - Supports update capsule across a system reset.
> > > > -- > > > > 2.25.1 > > > >