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charset="us-ascii" Content-Transfer-Encoding: quoted-printable // // SMM Stack Guard Enabled // Append Shadow Stack after normal stack // 2 more pages is allocated for each processor, one is guard page = and the other is known good shadow stack. // // |=3D Stacks // +--------------------------------------------------+--------------= -------------------------------------------------+ // | Known Good Stack | Guard Page | SMM Stack | Known Good Sh= adow Stack | Guard Page | SMM Shadow Stack | // +--------------------------------------------------+--------------= -------------------------------------------------+ // | 4K | 4K |PcdCpuSmmStackSize| 4K= | 4K |PcdCpuSmmShadowStackSize| // |<---------------- mSmmStackSize ----------------->|<-------------= -------- mSmmShadowStackSize ------------------->| // | = | // |<-------------------------------------------- Processor N -------= ------------------------------------------------>| // GenSmmPageTable() only sets the "Guard page" in "mSmmStackSize range" as no= t-present. But the "Guard page" in "mSmmShadowStackSize range" is not marked as not-pr= esent. Why? Thanks, Ray > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of duntan > Sent: Tuesday, May 16, 2023 5:59 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Kumar, = Rahul > R ; Gerd Hoffmann > Subject: [edk2-devel] [Patch V4 10/15] UefiCpuPkg: Add GenSmmPageTable() = to > create smm page table >=20 > This commit is code refinement to current smm pagetable generation > code. Add a new GenSmmPageTable() API to create smm page table > based on the PageTableMap() API in CpuPageTableLib. Caller only > needs to specify the paging mode and the PhysicalAddressBits to map. > This function can be used to create both IA32 pae paging and X64 > 5level, 4level paging. >=20 > Signed-off-by: Dun Tan > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Cc: Gerd Hoffmann > --- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 2 +- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 15 > +++++++++++++++ > UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 65 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 220 > ++++++++++++++++++++++++++-----------------------------------------------= ------------ > -------------------------------------------------------------------------= ------------------------- > ------------------------------------- > 4 files changed, 107 insertions(+), 195 deletions(-) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > index 9c8107080a..b11264ce4a 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > @@ -63,7 +63,7 @@ SmmInitPageTable ( > InitializeIDTSmmStackGuard (); > } >=20 > - return Gen4GPageTable (TRUE); > + return GenSmmPageTable (PagingPae, mPhysicalAddressBits); > } >=20 > /** > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > index a7da9673a5..5399659bc0 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > @@ -553,6 +553,21 @@ Gen4GPageTable ( > IN BOOLEAN Is32BitPageTable > ); >=20 > +/** > + Create page table based on input PagingMode and PhysicalAddressBits in= smm. > + > + @param[in] PagingMode The paging mode. > + @param[in] PhysicalAddressBits The bits of physical address to m= ap. > + > + @retval PageTable Address > + > +**/ > +UINTN > +GenSmmPageTable ( > + IN PAGING_MODE PagingMode, > + IN UINT8 PhysicalAddressBits > + ); > + > /** > Initialize global data for MP synchronization. >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > index ef0ba9a355..138ff43c9d 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > @@ -1642,6 +1642,71 @@ EdkiiSmmClearMemoryAttributes ( > return SmmClearMemoryAttributes (BaseAddress, Length, Attributes); > } >=20 > +/** > + Create page table based on input PagingMode and PhysicalAddressBits in= smm. > + > + @param[in] PagingMode The paging mode. > + @param[in] PhysicalAddressBits The bits of physical address to m= ap. > + > + @retval PageTable Address > + > +**/ > +UINTN > +GenSmmPageTable ( > + IN PAGING_MODE PagingMode, > + IN UINT8 PhysicalAddressBits > + ) > +{ > + UINTN PageTableBufferSize; > + UINTN PageTable; > + VOID *PageTableBuffer; > + IA32_MAP_ATTRIBUTE MapAttribute; > + IA32_MAP_ATTRIBUTE MapMask; > + RETURN_STATUS Status; > + UINTN GuardPage; > + UINTN Index; > + UINT64 Length; > + > + Length =3D LShiftU64 (1, PhysicalAddressBits= ); > + PageTable =3D 0; > + PageTableBufferSize =3D 0; > + MapMask.Uint64 =3D MAX_UINT64; > + MapAttribute.Uint64 =3D mAddressEncMask; > + MapAttribute.Bits.Present =3D 1; > + MapAttribute.Bits.ReadWrite =3D 1; > + MapAttribute.Bits.UserSupervisor =3D 1; > + MapAttribute.Bits.Accessed =3D 1; > + MapAttribute.Bits.Dirty =3D 1; > + > + Status =3D PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, 0, Length, &MapAttribute, &MapMask, NULL); > + ASSERT (Status =3D=3D RETURN_BUFFER_TOO_SMALL); > + DEBUG ((DEBUG_INFO, "GenSMMPageTable: 0x%x bytes needed for initial > SMM page table\n", PageTableBufferSize)); > + PageTableBuffer =3D AllocatePageTableMemory (EFI_SIZE_TO_PAGES > (PageTableBufferSize)); > + ASSERT (PageTableBuffer !=3D NULL); > + Status =3D PageTableMap (&PageTable, PagingMode, PageTableBuffer, > &PageTableBufferSize, 0, Length, &MapAttribute, &MapMask, NULL); > + ASSERT (Status =3D=3D RETURN_SUCCESS); > + ASSERT (PageTableBufferSize =3D=3D 0); > + > + if (FeaturePcdGet (PcdCpuSmmStackGuard)) { > + // > + // Mark the 4KB guard page between known good stack and smm stack as > non-present > + // > + for (Index =3D 0; Index < gSmmCpuPrivate- > >SmmCoreEntryContext.NumberOfCpus; Index++) { > + GuardPage =3D mSmmStackArrayBase + EFI_PAGE_SIZE + Index * > (mSmmStackSize + mSmmShadowStackSize); > + Status =3D ConvertMemoryPageAttributes (PageTable, PagingMode, > GuardPage, SIZE_4KB, EFI_MEMORY_RP, TRUE, NULL); > + } > + } > + > + if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) !=3D 0) { > + // > + // Mark [0, 4k] as non-present > + // > + Status =3D ConvertMemoryPageAttributes (PageTable, PagingMode, 0, SI= ZE_4KB, > EFI_MEMORY_RP, TRUE, NULL); > + } > + > + return (UINTN)PageTable; > +} > + > /** > This function retrieves the attributes of the memory region specified = by > BaseAddress and Length. If different attributes are got from different= part > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > index 25ced50955..060e6dc147 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > @@ -167,160 +167,6 @@ CalculateMaximumSupportAddress ( > return PhysicalAddressBits; > } >=20 > -/** > - Set static page table. > - > - @param[in] PageTable Address of page table. > - @param[in] PhysicalAddressBits The maximum physical address bits > supported. > -**/ > -VOID > -SetStaticPageTable ( > - IN UINTN PageTable, > - IN UINT8 PhysicalAddressBits > - ) > -{ > - UINT64 PageAddress; > - UINTN NumberOfPml5EntriesNeeded; > - UINTN NumberOfPml4EntriesNeeded; > - UINTN NumberOfPdpEntriesNeeded; > - UINTN IndexOfPml5Entries; > - UINTN IndexOfPml4Entries; > - UINTN IndexOfPdpEntries; > - UINTN IndexOfPageDirectoryEntries; > - UINT64 *PageMapLevel5Entry; > - UINT64 *PageMapLevel4Entry; > - UINT64 *PageMap; > - UINT64 *PageDirectoryPointerEntry; > - UINT64 *PageDirectory1GEntry; > - UINT64 *PageDirectoryEntry; > - > - // > - // IA-32e paging translates 48-bit linear addresses to 52-bit physical= addresses > - // when 5-Level Paging is disabled. > - // > - ASSERT (PhysicalAddressBits <=3D 52); > - if (!m5LevelPagingNeeded && (PhysicalAddressBits > 48)) { > - PhysicalAddressBits =3D 48; > - } > - > - NumberOfPml5EntriesNeeded =3D 1; > - if (PhysicalAddressBits > 48) { > - NumberOfPml5EntriesNeeded =3D (UINTN)LShiftU64 (1, PhysicalAddressBi= ts - > 48); > - PhysicalAddressBits =3D 48; > - } > - > - NumberOfPml4EntriesNeeded =3D 1; > - if (PhysicalAddressBits > 39) { > - NumberOfPml4EntriesNeeded =3D (UINTN)LShiftU64 (1, PhysicalAddressBi= ts - > 39); > - PhysicalAddressBits =3D 39; > - } > - > - NumberOfPdpEntriesNeeded =3D 1; > - ASSERT (PhysicalAddressBits > 30); > - NumberOfPdpEntriesNeeded =3D (UINTN)LShiftU64 (1, PhysicalAddressBits = - 30); > - > - // > - // By architecture only one PageMapLevel4 exists - so lets allocate st= orage for > it. > - // > - PageMap =3D (VOID *)PageTable; > - > - PageMapLevel4Entry =3D PageMap; > - PageMapLevel5Entry =3D NULL; > - if (m5LevelPagingNeeded) { > - // > - // By architecture only one PageMapLevel5 exists - so lets allocate = storage for > it. > - // > - PageMapLevel5Entry =3D PageMap; > - } > - > - PageAddress =3D 0; > - > - for ( IndexOfPml5Entries =3D 0 > - ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded > - ; IndexOfPml5Entries++, PageMapLevel5Entry++) > - { > - // > - // Each PML5 entry points to a page of PML4 entires. > - // So lets allocate space for them and fill them in in the IndexOfPm= l4Entries > loop. > - // When 5-Level Paging is disabled, below allocation happens only on= ce. > - // > - if (m5LevelPagingNeeded) { > - PageMapLevel4Entry =3D (UINT64 *)((*PageMapLevel5Entry) & > ~mAddressEncMask & gPhyMask); > - if (PageMapLevel4Entry =3D=3D NULL) { > - PageMapLevel4Entry =3D AllocatePageTableMemory (1); > - ASSERT (PageMapLevel4Entry !=3D NULL); > - ZeroMem (PageMapLevel4Entry, EFI_PAGES_TO_SIZE (1)); > - > - *PageMapLevel5Entry =3D (UINT64)(UINTN)PageMapLevel4Entry | > mAddressEncMask | PAGE_ATTRIBUTE_BITS; > - } > - } > - > - for (IndexOfPml4Entries =3D 0; IndexOfPml4Entries < > (NumberOfPml5EntriesNeeded =3D=3D 1 ? NumberOfPml4EntriesNeeded : 512); > IndexOfPml4Entries++, PageMapLevel4Entry++) { > - // > - // Each PML4 entry points to a page of Page Directory Pointer entr= ies. > - // > - PageDirectoryPointerEntry =3D (UINT64 *)((*PageMapLevel4Entry) & > ~mAddressEncMask & gPhyMask); > - if (PageDirectoryPointerEntry =3D=3D NULL) { > - PageDirectoryPointerEntry =3D AllocatePageTableMemory (1); > - ASSERT (PageDirectoryPointerEntry !=3D NULL); > - ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE (1)); > - > - *PageMapLevel4Entry =3D (UINT64)(UINTN)PageDirectoryPointerEntry= | > mAddressEncMask | PAGE_ATTRIBUTE_BITS; > - } > - > - if (m1GPageTableSupport) { > - PageDirectory1GEntry =3D PageDirectoryPointerEntry; > - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntr= ies < 512; > IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress +=3D > SIZE_1GB) { > - if ((IndexOfPml4Entries =3D=3D 0) && (IndexOfPageDirectoryEntr= ies < 4)) { > - // > - // Skip the < 4G entries > - // > - continue; > - } > - > - // > - // Fill in the Page Directory entries > - // > - *PageDirectory1GEntry =3D PageAddress | mAddressEncMask | IA32= _PG_PS > | PAGE_ATTRIBUTE_BITS; > - } > - } else { > - PageAddress =3D BASE_4GB; > - for (IndexOfPdpEntries =3D 0; IndexOfPdpEntries < > (NumberOfPml4EntriesNeeded =3D=3D 1 ? NumberOfPdpEntriesNeeded : 512); > IndexOfPdpEntries++, PageDirectoryPointerEntry++) { > - if ((IndexOfPml4Entries =3D=3D 0) && (IndexOfPdpEntries < 4)) = { > - // > - // Skip the < 4G entries > - // > - continue; > - } > - > - // > - // Each Directory Pointer entries points to a page of Page Dir= ectory entires. > - // So allocate space for them and fill them in in the > IndexOfPageDirectoryEntries loop. > - // > - PageDirectoryEntry =3D (UINT64 *)((*PageDirectoryPointerEntry)= & > ~mAddressEncMask & gPhyMask); > - if (PageDirectoryEntry =3D=3D NULL) { > - PageDirectoryEntry =3D AllocatePageTableMemory (1); > - ASSERT (PageDirectoryEntry !=3D NULL); > - ZeroMem (PageDirectoryEntry, EFI_PAGES_TO_SIZE (1)); > - > - // > - // Fill in a Page Directory Pointer Entries > - // > - *PageDirectoryPointerEntry =3D (UINT64)(UINTN)PageDirectoryE= ntry | > mAddressEncMask | PAGE_ATTRIBUTE_BITS; > - } > - > - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEn= tries < 512; > IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress +=3D > SIZE_2MB) { > - // > - // Fill in the Page Directory entries > - // > - *PageDirectoryEntry =3D PageAddress | mAddressEncMask | IA32= _PG_PS | > PAGE_ATTRIBUTE_BITS; > - } > - } > - } > - } > - } > -} > - > /** > Create PageTable for SMM use. >=20 > @@ -332,15 +178,16 @@ SmmInitPageTable ( > VOID > ) > { > - EFI_PHYSICAL_ADDRESS Pages; > - UINT64 *PTEntry; > + UINTN PageTable; > LIST_ENTRY *FreePage; > UINTN Index; > UINTN PageFaultHandlerHookAddress; > IA32_IDT_GATE_DESCRIPTOR *IdtEntry; > EFI_STATUS Status; > + UINT64 *PdptEntry; > UINT64 *Pml4Entry; > UINT64 *Pml5Entry; > + UINT8 PhysicalAddressBits; >=20 > // > // Initialize spin lock > @@ -357,59 +204,44 @@ SmmInitPageTable ( > } else { > mPagingMode =3D m1GPageTableSupport ? Paging4Level1GB : Paging4Level= ; > } > + > DEBUG ((DEBUG_INFO, "5LevelPaging Needed - %d\n", > m5LevelPagingNeeded)); > DEBUG ((DEBUG_INFO, "1GPageTable Support - %d\n", > m1GPageTableSupport)); > DEBUG ((DEBUG_INFO, "PcdCpuSmmRestrictedMemoryAccess - %d\n", > mCpuSmmRestrictedMemoryAccess)); > DEBUG ((DEBUG_INFO, "PhysicalAddressBits - %d\n", > mPhysicalAddressBits)); > - // > - // Generate PAE page table for the first 4GB memory space > - // > - Pages =3D Gen4GPageTable (FALSE); >=20 > // > - // Set IA32_PG_PMNT bit to mask this entry > + // Generate initial SMM page table. > + // Only map [0, 4G] when PcdCpuSmmRestrictedMemoryAccess is FALSE. > // > - PTEntry =3D (UINT64 *)(UINTN)Pages; > - for (Index =3D 0; Index < 4; Index++) { > - PTEntry[Index] |=3D IA32_PG_PMNT; > - } > - > - // > - // Fill Page-Table-Level4 (PML4) entry > - // > - Pml4Entry =3D (UINT64 *)AllocatePageTableMemory (1); > - ASSERT (Pml4Entry !=3D NULL); > - *Pml4Entry =3D Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; > - ZeroMem (Pml4Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml4Entry)); > - > - // > - // Set sub-entries number > - // > - SetSubEntriesNum (Pml4Entry, 3); > - PTEntry =3D Pml4Entry; > + PhysicalAddressBits =3D mCpuSmmRestrictedMemoryAccess ? > mPhysicalAddressBits : 32; > + PageTable =3D GenSmmPageTable (mPagingMode, PhysicalAddressB= its); >=20 > if (m5LevelPagingNeeded) { > + Pml5Entry =3D (UINT64 *)PageTable; > // > - // Fill PML5 entry > - // > - Pml5Entry =3D (UINT64 *)AllocatePageTableMemory (1); > - ASSERT (Pml5Entry !=3D NULL); > - *Pml5Entry =3D (UINTN)Pml4Entry | mAddressEncMask | > PAGE_ATTRIBUTE_BITS; > - ZeroMem (Pml5Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml5Entry)); > - // > - // Set sub-entries number > + // Set Pml5Entry sub-entries number for smm PF handler usage. > // > SetSubEntriesNum (Pml5Entry, 1); > - PTEntry =3D Pml5Entry; > + Pml4Entry =3D (UINT64 *)((*Pml5Entry) & ~mAddressEncMask & gPhyMask)= ; > + } else { > + Pml4Entry =3D (UINT64 *)PageTable; > + } > + > + // > + // Set IA32_PG_PMNT bit to mask first 4 PdptEntry. > + // > + PdptEntry =3D (UINT64 *)((*Pml4Entry) & ~mAddressEncMask & gPhyMask); > + for (Index =3D 0; Index < 4; Index++) { > + PdptEntry[Index] |=3D IA32_PG_PMNT; > } >=20 > - if (mCpuSmmRestrictedMemoryAccess) { > + if (!mCpuSmmRestrictedMemoryAccess) { > // > - // When access to non-SMRAM memory is restricted, create page table > - // that covers all memory space. > + // Set Pml4Entry sub-entries number for smm PF handler usage. > // > - SetStaticPageTable ((UINTN)PTEntry, mPhysicalAddressBits); > - } else { > + SetSubEntriesNum (Pml4Entry, 3); > + > // > // Add pages to page pool > // > @@ -466,7 +298,7 @@ SmmInitPageTable ( > // > // Return the address of PML4/PML5 (to set CR3) > // > - return (UINT32)(UINTN)PTEntry; > + return (UINT32)PageTable; > } >=20 > /** > -- > 2.31.1.windows.1 >=20 >=20 >=20 >=20 >=20