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X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: P4xlCpJ7fyVUDncD400bFzHKwwohL1m3VIlwTiVzUb1ypR6HTSIF/tfhjLnUcd7Mf6N1ah9BVfg5Syf6GoDLGQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB4724 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Fri, 24 May 2024 18:34:53 -0700 Resent-From: ray.ni@intel.com Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Nk0lsjMaQEWJ588Lk1itWL0px7686176AA= Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN6PR11MB82441022813E0A1E4BCF9AA08CF62MN6PR11MB8244namp_" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=OQSkPZET; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io --_000_MN6PR11MB82441022813E0A1E4BCF9AA08CF62MN6PR11MB8244namp_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable I created PR for merge: UefiCpuPkg/MpLib:Do not assume BSP is #0. by niruiy= u =B7 Pull Request #5683 =B7 tianocore/edk2 (github.com) But, I cannot set "push" label. @Gao, Liming? Thanks, Ray ________________________________ From: devel@edk2.groups.io on behalf of Ni, Ray Sent: Saturday, May 25, 2024 9:32 To: Feng, Ning ; devel@edk2.groups.io Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg/MpLib:Do not assume BSP is #0. Reviewed-by: Ray Ni Thanks, Ray ________________________________ From: Feng, Ning Sent: Saturday, May 25, 2024 15:42 To: devel@edk2.groups.io Cc: Feng, Ning ; Ni, Ray Subject: [PATCH] UefiCpuPkg/MpLib:Do not assume BSP is #0. REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D4778 MPInitlib have wrong expectation that BSP index should always be 0 in MpInitLibInitialize(), SwitchBsp(),ApWakeupFunction(). That will cause the data mismatch, if the initial BSP is not 0. Cc: Ray Ni Signed-off-by: Ning Feng --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 47 ++++++++++++++++++---------- 1 file changed, 30 insertions(+), 17 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index d724456502..ba497cbfd9 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -114,6 +114,10 @@ FutureBSPProc ( SaveVolatileRegisters (&DataInHob->APInfo.VolatileRegisters); AsmExchangeRole (&DataInHob->APInfo, &DataInHob->BSPInfo); RestoreVolatileRegisters (&DataInHob->APInfo.VolatileRegisters, FALSE); + // + // Restore VolatileReg saved in CpuMpData->CpuData + // + CopyMem (&DataInHob->CpuData[DataInHob->BspNumber].VolatileRegisters, &D= ataInHob->APInfo.VolatileRegisters, sizeof (CPU_VOLATILE_REGISTERS)); } /** @@ -761,11 +765,11 @@ ApWakeupFunction ( BistData =3D (UINT32)ApStackData->Bist; // - // CpuMpData->CpuData[0].VolatileRegisters is initialized based on B= SP environment, + // CpuMpData->CpuData[BspNumber].VolatileRegisters is initialized ba= sed on BSP environment, // to initialize AP in InitConfig path. - // NOTE: IDTR.BASE stored in CpuMpData->CpuData[0].VolatileRegisters= points to a different IDT shared by all APs. + // NOTE: IDTR.BASE stored in CpuMpData->CpuData[BspNumber].VolatileR= egisters points to a different IDT shared by all APs. // - RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, = FALSE); + RestoreVolatileRegisters (&CpuMpData->CpuData[CpuMpData->BspNumber].= VolatileRegisters, FALSE); InitializeApData (CpuMpData, ProcessorNumber, BistData, ApTopOfStack= ); ApStartupSignalBuffer =3D CpuMpData->CpuData[ProcessorNumber].Startu= pApSignal; } else { @@ -798,10 +802,10 @@ ApWakeupFunction ( // 1. AP is re-enabled after it's disabled, in either PEI or DXE p= hase. // 2. AP is initialized in DXE phase. // In either case, use the volatile registers value derived from B= SP. - // NOTE: IDTR.BASE stored in CpuMpData->CpuData[0].VolatileRegiste= rs points to a + // NOTE: IDTR.BASE stored in CpuMpData->CpuData[BspNumber].Volatil= eRegisters points to a // different IDT shared by all APs. // - RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters= , FALSE); + RestoreVolatileRegisters (&CpuMpData->CpuData[CpuMpData->BspNumber= ].VolatileRegisters, FALSE); } else { if (CpuMpData->ApLoopMode =3D=3D ApInHltLoop) { // @@ -927,7 +931,7 @@ DxeApEntryPoint ( AsmWriteMsr64 (MSR_IA32_EFER, EferMsr.Uint64); } - RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALS= E); + RestoreVolatileRegisters (&CpuMpData->CpuData[CpuMpData->BspNumber].Vola= tileRegisters, FALSE); InterlockedIncrement ((UINT32 *)&CpuMpData->FinishedCount); PlaceAPInMwaitLoopOrRunLoop ( CpuMpData->ApLoopMode, @@ -2151,11 +2155,16 @@ MpInitLibInitialize ( CpuMpData->BackupBufferSize =3D ApResetVectorSizeBelow1Mb; CpuMpData->WakeupBuffer =3D (UINTN)-1; CpuMpData->CpuCount =3D 1; - CpuMpData->BspNumber =3D 0; - CpuMpData->WaitEvent =3D NULL; - CpuMpData->SwitchBspFlag =3D FALSE; - CpuMpData->CpuData =3D (CPU_AP_DATA *)(CpuMpData + 1); - CpuMpData->CpuInfoInHob =3D (UINT64)(UINTN)(CpuMpData->CpuData + Max= LogicalProcessorNumber); + if (FirstMpHandOff =3D=3D NULL) { + CpuMpData->BspNumber =3D 0; + } else { + CpuMpData->BspNumber =3D GetBspNumber (FirstMpHandOff); + } + + CpuMpData->WaitEvent =3D NULL; + CpuMpData->SwitchBspFlag =3D FALSE; + CpuMpData->CpuData =3D (CPU_AP_DATA *)(CpuMpData + 1); + CpuMpData->CpuInfoInHob =3D (UINT64)(UINTN)(CpuMpData->CpuData + MaxLog= icalProcessorNumber); InitializeSpinLock (&CpuMpData->MpLock); CpuMpData->SevEsIsEnabled =3D ConfidentialComputingGuestHas (CCAttrAmd= SevEs); CpuMpData->SevSnpIsEnabled =3D ConfidentialComputingGuestHas (CCAttrAmd= SevSnp); @@ -2186,11 +2195,11 @@ MpInitLibInitialize ( // Don't pass BSP's TR to APs to avoid AP init failure. // VolatileRegisters.Tr =3D 0; - CopyMem (&CpuMpData->CpuData[0].VolatileRegisters, &VolatileRegisters, s= izeof (VolatileRegisters)); + CopyMem (&CpuMpData->CpuData[CpuMpData->BspNumber].VolatileRegisters, &V= olatileRegisters, sizeof (VolatileRegisters)); // // Set BSP basic information // - InitializeApData (CpuMpData, 0, 0, CpuMpData->Buffer + ApStackSize); + InitializeApData (CpuMpData, CpuMpData->BspNumber, 0, CpuMpData->Buffer = + ApStackSize * (CpuMpData->BspNumber + 1)); // // Save assembly code information // @@ -2245,9 +2254,8 @@ MpInitLibInitialize ( AmdSevUpdateCpuMpData (CpuMpData); } - CpuMpData->CpuCount =3D MaxLogicalProcessorNumber; - CpuMpData->BspNumber =3D GetBspNumber (FirstMpHandOff); - CpuInfoInHob =3D (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoI= nHob; + CpuMpData->CpuCount =3D MaxLogicalProcessorNumber; + CpuInfoInHob =3D (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoIn= Hob; for (MpHandOff =3D FirstMpHandOff; MpHandOff !=3D NULL; MpHandOff =3D GetNextMpHandOffHob (MpHandOff)) @@ -2615,7 +2623,12 @@ SwitchBSPWorker ( SaveVolatileRegisters (&CpuMpData->BSPInfo.VolatileRegisters); AsmExchangeRole (&CpuMpData->BSPInfo, &CpuMpData->APInfo); RestoreVolatileRegisters (&CpuMpData->BSPInfo.VolatileRegisters, FALSE); - + // + // Restore VolatileRegs saved in CpuMpData->CpuData + // Don't pass BSP's TR to APs to avoid AP init failure. + // + CopyMem (&CpuMpData->CpuData[CpuMpData->NewBspNumber].VolatileRegisters,= &CpuMpData->BSPInfo.VolatileRegisters, sizeof (CPU_VOLATILE_REGISTERS)); + CpuMpData->CpuData[CpuMpData->NewBspNumber].VolatileRegisters.Tr =3D 0; // // Set the BSP bit of MSR_IA32_APIC_BASE on new BSP // -- 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#119264): https://edk2.groups.io/g/devel/message/119264 Mute This Topic: https://groups.io/mt/106291092/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_MN6PR11MB82441022813E0A1E4BCF9AA08CF62MN6PR11MB8244namp_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
I created PR for merge: UefiCpuPkg/MpLib:Do not assume BSP is #0. by niruiyu =B7 Pull Request #5683= =B7 tianocore/edk2 (github.com)
But, I cannot set "push" label.

@Gao, Liming?

Thanks,
Ray
From: devel@edk2.groups.io = <devel@edk2.groups.io> on behalf of Ni, Ray <ray.ni@intel.com><= br> Sent: Saturday, May 25, 2024 9:32
To: Feng, Ning <ning.feng@intel.com>; devel@edk2.groups.io <= ;devel@edk2.groups.io>
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg/MpLib:Do not assume BSP= is #0.
 
Reviewed-by: Ray Ni <ray.ni@intel.com>

Thanks,
Ray
From: Feng, Ning <ning= .feng@intel.com>
Sent: Saturday, May 25, 2024 15:42
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Feng, Ning <ning.feng@intel.com>; Ni, Ray <ray.ni@intel= .com>
Subject: [PATCH] UefiCpuPkg/MpLib:Do not assume BSP is #0.
 
REF:https://bugzilla.tianocore.org/show_bug.cgi?= id=3D4778
MPInitlib have wrong expectation that BSP index should always be 0 in
MpInitLibInitialize(), SwitchBsp(),ApWakeupFunction().
That will cause the data mismatch, if the initial BSP is not 0.
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Ning Feng <ning.feng@intel.com>
---
 UefiCpuPkg/Library/MpInitLib/MpLib.c | 47 ++++++++++++++++++---------= -
 1 file changed, 30 insertions(+), 17 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c
index d724456502..ba497cbfd9 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -114,6 +114,10 @@ FutureBSPProc (
   SaveVolatileRegisters (&DataInHob->APInfo.VolatileRegis= ters);

   AsmExchangeRole (&DataInHob->APInfo, &DataInHob->= ;BSPInfo);

   RestoreVolatileRegisters (&DataInHob->APInfo.VolatileRe= gisters, FALSE);

+  //

+  // Restore VolatileReg saved in CpuMpData->CpuData

+  //

+  CopyMem (&DataInHob->CpuData[DataInHob->BspNumber].Volati= leRegisters, &DataInHob->APInfo.VolatileRegisters, sizeof (CPU_VOLAT= ILE_REGISTERS));

 }

 

 /**

@@ -761,11 +765,11 @@ ApWakeupFunction (
       BistData     =3D (= UINT32)ApStackData->Bist;

 

       //

-      // CpuMpData->CpuData[0].VolatileRegiste= rs is initialized based on BSP environment,

+      // CpuMpData->CpuData[BspNumber].Volatil= eRegisters is initialized based on BSP environment,

       //   to initialize AP in Ini= tConfig path.

-      // NOTE: IDTR.BASE stored in CpuMpData->= CpuData[0].VolatileRegisters points to a different IDT shared by all APs.
+      // NOTE: IDTR.BASE stored in CpuMpData->= CpuData[BspNumber].VolatileRegisters points to a different IDT shared by al= l APs.

       //

-      RestoreVolatileRegisters (&CpuMpData-&g= t;CpuData[0].VolatileRegisters, FALSE);

+      RestoreVolatileRegisters (&CpuMpData-&g= t;CpuData[CpuMpData->BspNumber].VolatileRegisters, FALSE);

       InitializeApData (CpuMpData, Processor= Number, BistData, ApTopOfStack);

       ApStartupSignalBuffer =3D CpuMpData-&g= t;CpuData[ProcessorNumber].StartupApSignal;

     } else {

@@ -798,10 +802,10 @@ ApWakeupFunction (
         // 1. AP is re-enabled aft= er it's disabled, in either PEI or DXE phase.

         // 2. AP is initialized in= DXE phase.

         // In either case, use the= volatile registers value derived from BSP.

-        // NOTE: IDTR.BASE stored in Cp= uMpData->CpuData[0].VolatileRegisters points to a

+        // NOTE: IDTR.BASE stored in Cp= uMpData->CpuData[BspNumber].VolatileRegisters points to a

         //   different I= DT shared by all APs.

         //

-        RestoreVolatileRegisters (&= CpuMpData->CpuData[0].VolatileRegisters, FALSE);

+        RestoreVolatileRegisters (&= CpuMpData->CpuData[CpuMpData->BspNumber].VolatileRegisters, FALSE);
       } else {

         if (CpuMpData->ApLoopMo= de =3D=3D ApInHltLoop) {

           //

@@ -927,7 +931,7 @@ DxeApEntryPoint (
     AsmWriteMsr64 (MSR_IA32_EFER, EferMsr.Uint64);

   }

 

-  RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileReg= isters, FALSE);

+  RestoreVolatileRegisters (&CpuMpData->CpuData[CpuMpData->= BspNumber].VolatileRegisters, FALSE);

   InterlockedIncrement ((UINT32 *)&CpuMpData->FinishedCou= nt);

   PlaceAPInMwaitLoopOrRunLoop (

     CpuMpData->ApLoopMode,

@@ -2151,11 +2155,16 @@ MpInitLibInitialize (
   CpuMpData->BackupBufferSize =3D ApResetVectorSizeBelow1Mb;<= br>
   CpuMpData->WakeupBuffer     =3D (UINTN)= -1;

   CpuMpData->CpuCount      &nbs= p;  =3D 1;

-  CpuMpData->BspNumber        = =3D 0;

-  CpuMpData->WaitEvent        = =3D NULL;

-  CpuMpData->SwitchBspFlag    =3D FALSE;

-  CpuMpData->CpuData       &nbs= p;  =3D (CPU_AP_DATA *)(CpuMpData + 1);

-  CpuMpData->CpuInfoInHob     =3D (UINT64)(UIN= TN)(CpuMpData->CpuData + MaxLogicalProcessorNumber);

+  if (FirstMpHandOff =3D=3D NULL) {

+    CpuMpData->BspNumber =3D 0;

+  } else {

+    CpuMpData->BspNumber =3D GetBspNumber (FirstMpHandOf= f);

+  }

+

+  CpuMpData->WaitEvent     =3D NULL;

+  CpuMpData->SwitchBspFlag =3D FALSE;

+  CpuMpData->CpuData       =3D (CPU_= AP_DATA *)(CpuMpData + 1);

+  CpuMpData->CpuInfoInHob  =3D (UINT64)(UINTN)(CpuMpData->= CpuData + MaxLogicalProcessorNumber);

   InitializeSpinLock (&CpuMpData->MpLock);

   CpuMpData->SevEsIsEnabled   =3D ConfidentialCompu= tingGuestHas (CCAttrAmdSevEs);

   CpuMpData->SevSnpIsEnabled  =3D ConfidentialComputingG= uestHas (CCAttrAmdSevSnp);

@@ -2186,11 +2195,11 @@ MpInitLibInitialize (
   // Don't pass BSP's TR to APs to avoid AP init failure.

   //

   VolatileRegisters.Tr =3D 0;

-  CopyMem (&CpuMpData->CpuData[0].VolatileRegisters, &Vola= tileRegisters, sizeof (VolatileRegisters));

+  CopyMem (&CpuMpData->CpuData[CpuMpData->BspNumber].Volati= leRegisters, &VolatileRegisters, sizeof (VolatileRegisters));

   //

   // Set BSP basic information

   //

-  InitializeApData (CpuMpData, 0, 0, CpuMpData->Buffer + ApStackSi= ze);

+  InitializeApData (CpuMpData, CpuMpData->BspNumber, 0, CpuMpData-= >Buffer + ApStackSize * (CpuMpData->BspNumber + 1));

   //

   // Save assembly code information

   //

@@ -2245,9 +2254,8 @@ MpInitLibInitialize (
       AmdSevUpdateCpuMpData (CpuMpData);

     }

 

-    CpuMpData->CpuCount  =3D MaxLogicalProcessorNum= ber;

-    CpuMpData->BspNumber =3D GetBspNumber (FirstMpHandOf= f);

-    CpuInfoInHob       &= nbsp; =3D (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;

+    CpuMpData->CpuCount =3D MaxLogicalProcessorNumber;
+    CpuInfoInHob        = =3D (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;

     for (MpHandOff =3D FirstMpHandOff;

          MpHandOff !=3D NULL;=

          MpHandOff =3D GetNex= tMpHandOffHob (MpHandOff))

@@ -2615,7 +2623,12 @@ SwitchBSPWorker (
   SaveVolatileRegisters (&CpuMpData->BSPInfo.VolatileRegi= sters);

   AsmExchangeRole (&CpuMpData->BSPInfo, &CpuMpData-&g= t;APInfo);

   RestoreVolatileRegisters (&CpuMpData->BSPInfo.VolatileR= egisters, FALSE);

-

+  //

+  // Restore VolatileRegs saved in CpuMpData->CpuData

+  // Don't pass BSP's TR to APs to avoid AP init failure.

+  //

+  CopyMem (&CpuMpData->CpuData[CpuMpData->NewBspNumber].Vol= atileRegisters, &CpuMpData->BSPInfo.VolatileRegisters, sizeof (CPU_V= OLATILE_REGISTERS));

+  CpuMpData->CpuData[CpuMpData->NewBspNumber].VolatileRegisters= .Tr =3D 0;

   //

   // Set the BSP bit of MSR_IA32_APIC_BASE on new BSP

   //

--
2.25.1

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