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contact devel+owner@edk2.groups.io Resent-Date: Mon, 15 Apr 2024 20:27:56 -0700 Resent-From: ray.ni@intel.com Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: g4V3wzZLpPvOvZmbuPm8K4Jox7686176AA= Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN6PR11MB8244106AE4D06AA27577235A8C082MN6PR11MB8244namp_" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=e9JxT1s+; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.9 as permitted sender) smtp.mailfrom=bounce@groups.io --_000_MN6PR11MB8244106AE4D06AA27577235A8C082MN6PR11MB8244namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Acked-by: Ray Ni Thanks, Ray ________________________________ From: Wu, Jiaxin Sent: Monday, April 15, 2024 21:30 To: devel@edk2.groups.io Cc: Abdul Lateef Attar ; Abner Chang ; Tom Lendacky ; Ni, Ray ; Zeng, Star ; Gerd Hoffmann ; K= umar, Rahul R Subject: [PATCH v2 03/10] UefiCpuPkg/SmmRelocationLib: Add library instance= for AMD Due to the definition difference of SMRAM Save State, SmmBase config in SMRAM Save State for AMD is also different. This patch provides the AmdSmmRelocationLib library instance to handle the SMRAM Save State difference. Cc: Abdul Lateef Attar Cc: Abner Chang Cc: Tom Lendacky Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- ...mmRelocationLib.inf =3D> AmdSmmRelocationLib.inf} | 5 +- ...SaveStateConfig.c =3D> AmdSmramSaveStateConfig.c} | 93 ++++++++++------= ------ UefiCpuPkg/UefiCpuPkg.dsc | 1 + 3 files changed, 46 insertions(+), 53 deletions(-) copy UefiCpuPkg/Library/SmmRelocationLib/{SmmRelocationLib.inf =3D> AmdSmm= RelocationLib.inf} (89%) copy UefiCpuPkg/Library/SmmRelocationLib/{SmramSaveStateConfig.c =3D> AmdS= mramSaveStateConfig.c} (50%) diff --git a/UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.inf b/Uef= iCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf similarity index 89% copy from UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.inf copy to UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf index 6581fa2dad..710cd1948b 100644 --- a/UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.inf +++ b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf @@ -13,18 +13,18 @@ ## [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D SmmRelocationLib - FILE_GUID =3D 853E97B3-790C-4EA3-945C-8F622FC47FE8 + FILE_GUID =3D 65C74DCD-0D09-494A-8BFF-A64226EB8054 MODULE_TYPE =3D PEIM VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D SmmRelocationLib [Sources] InternalSmmRelocationLib.h - SmramSaveStateConfig.c + AmdSmramSaveStateConfig.c SmmRelocationLib.c [Sources.Ia32] Ia32/Semaphore.c Ia32/SmmInit.nasm @@ -40,11 +40,10 @@ [LibraryClasses] BaseLib BaseMemoryLib CpuExceptionHandlerLib - CpuLib DebugLib HobLib LocalApicLib MemoryAllocationLib PcdLib diff --git a/UefiCpuPkg/Library/SmmRelocationLib/SmramSaveStateConfig.c b/U= efiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c similarity index 50% copy from UefiCpuPkg/Library/SmmRelocationLib/SmramSaveStateConfig.c copy to UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c index fb69b2b5c5..95a1ce8d46 100644 --- a/UefiCpuPkg/Library/SmmRelocationLib/SmramSaveStateConfig.c +++ b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c @@ -1,14 +1,17 @@ /** @file Config SMRAM Save State for SmmBases Relocation. + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
Copyright (c) 2024, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include "InternalSmmRelocationLib.h" -#include +#include + +#define EFER_ADDRESS 0XC0000080ul /** Determine the mode of the CPU at the time an SMI occurs @retval EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT 32 bit. @@ -18,44 +21,18 @@ UINT8 CheckMmSaveStateRegisterLma ( VOID ) { - CPUID_VERSION_INFO_EAX RegEax; - CPUID_EXTENDED_CPU_SIG_EDX RegEdx; - UINTN FamilyId; - UINTN ModelId; - UINT32 Eax; - UINT8 SmmSaveStateRegisterLma; - - // - // Determine the mode of the CPU at the time an SMI occurs - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 34.4.1.1 - // - RegEax.Uint32 =3D GetCpuFamilyModel (); - FamilyId =3D RegEax.Bits.FamilyId; - ModelId =3D RegEax.Bits.Model; - if ((FamilyId =3D=3D 0x06) || (FamilyId =3D=3D 0x0f)) { - ModelId =3D ModelId | RegEax.Bits.ExtendedModelId << 4; - } + UINT8 SmmSaveStateRegisterLma; + UINT32 LMAValue; - RegEdx.Uint32 =3D 0; - AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL); - if (Eax >=3D CPUID_EXTENDED_CPU_SIG) { - AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &(RegEdx.Uint32)); - } - - SmmSaveStateRegisterLma =3D EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT; - if (RegEdx.Bits.LM) { - SmmSaveStateRegisterLma =3D EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT; - } + SmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; - if (FamilyId =3D=3D 0x06) { - if ((ModelId =3D=3D 0x17) || (ModelId =3D=3D 0x0f) || (ModelId =3D=3D = 0x1c)) { - SmmSaveStateRegisterLma =3D EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT; - } + LMAValue =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; + if (LMAValue) { + SmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; } return SmmSaveStateRegisterLma; } @@ -73,18 +50,32 @@ EFIAPI ConfigureSmBase ( IN UINTN CpuIndex, IN OUT SMRAM_SAVE_STATE_MAP *CpuState ) { - CpuState->x86.SMBASE =3D (UINT32)mSmBaseForAllCpus[CpuIndex]; + AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState; + + AmdCpuState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; + + AmdCpuState->x64.SMBASE =3D (UINT32)mSmBaseForAllCpus[CpuIndex]; } /** - Hook the code executed immediately after an RSM instruction on the curre= ntly - executing CPU. The mode of code executed immediately after RSM must be - detected, and the appropriate hook must be selected. Always clear the a= uto - HALT restart flag if it is set. + This function updates the SMRAM save state on the currently executing CP= U + to resume execution at a specific address after an RSM instruction. Thi= s + function must evaluate the SMRAM save state to determine the execution m= ode + the RSM instruction resumes and update the resume execution address with + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT re= start + flag in the SMRAM save state must always be cleared. This function retu= rns + the value of the instruction pointer from the SMRAM save state that was + replaced. If this function returns 0, then the SMRAM save state was not + modified. + + This function is called during the very first SMI on each CPU after + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mo= de + to signal that the SMBASE of each CPU has been updated before the defaul= t + SMBASE address is used for the first SMI to the next CPU. @param[in] CpuIndex The processor index for the curr= ently executing CPU. @param[in,out] CpuState Pointer to SMRAM Save State Map = for the currently executing CPU. @@ -103,37 +94,39 @@ HookReturnFromSmm ( IN OUT SMRAM_SAVE_STATE_MAP *CpuState, IN UINT64 NewInstructionPointer32, IN UINT64 NewInstructionPointer ) { - UINT64 OriginalInstructionPointer; + UINT64 OriginalInstructionPointer; + AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState; - if (CheckMmSaveStateRegisterLma () =3D=3D EFI_MM_SAVE_STATE_REGISTER_LMA= _32BIT) { - OriginalInstructionPointer =3D (UINT64)CpuState->x86._EIP; - CpuState->x86._EIP =3D (UINT32)NewInstructionPointer; + AmdCpuState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; + if (CheckMmSaveStateRegisterLma () =3D=3D EFI_MM_SAVE_STATE_REGISTER_LMA= _32BIT) { + OriginalInstructionPointer =3D (UINT64)AmdCpuState->x86._EIP; + AmdCpuState->x86._EIP =3D (UINT32)NewInstructionPointer; // // Clear the auto HALT restart flag so the RSM instruction returns // program control to the instruction following the HLT instruction. // - if ((CpuState->x86.AutoHALTRestart & BIT0) !=3D 0) { - CpuState->x86.AutoHALTRestart &=3D ~BIT0; + if ((AmdCpuState->x86.AutoHALTRestart & BIT0) !=3D 0) { + AmdCpuState->x86.AutoHALTRestart &=3D ~BIT0; } } else { - OriginalInstructionPointer =3D CpuState->x64._RIP; - if ((CpuState->x64.IA32_EFER & LMA) =3D=3D 0) { - CpuState->x64._RIP =3D (UINT32)NewInstructionPointer32; + OriginalInstructionPointer =3D AmdCpuState->x64._RIP; + if ((AmdCpuState->x64.EFER & LMA) =3D=3D 0) { + AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer32; } else { - CpuState->x64._RIP =3D (UINT32)NewInstructionPointer; + AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer; } // // Clear the auto HALT restart flag so the RSM instruction returns // program control to the instruction following the HLT instruction. // - if ((CpuState->x64.AutoHALTRestart & BIT0) !=3D 0) { - CpuState->x64.AutoHALTRestart &=3D ~BIT0; + if ((AmdCpuState->x64.AutoHALTRestart & BIT0) !=3D 0) { + AmdCpuState->x64.AutoHALTRestart &=3D ~BIT0; } } return OriginalInstructionPointer; } diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index dd2ad398c0..0c5fdcffde 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -195,10 +195,11 @@ } UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.inf + UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf [Components.X64] UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHandle= rLibUnitTest.inf [Components.RISCV64] -- 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117840): https://edk2.groups.io/g/devel/message/117840 Mute This Topic: https://groups.io/mt/105535807/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_MN6PR11MB8244106AE4D06AA27577235A8C082MN6PR11MB8244namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Acked-by: Ray Ni <ray.ni@intel.com>

Thanks,
Ray
From: Wu, Jiaxin <jiaxin= .wu@intel.com>
Sent: Monday, April 15, 2024 21:30
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>; Abner Chan= g <abner.chang@amd.com>; Tom Lendacky <thomas.lendacky@amd.com>= ; Ni, Ray <ray.ni@intel.com>; Zeng, Star <star.zeng@intel.com>;= Gerd Hoffmann <kraxel@redhat.com>; Kumar, Rahul R <rahul.r.kumar@= intel.com>
Subject: [PATCH v2 03/10] UefiCpuPkg/SmmRelocationLib: Add library i= nstance for AMD
 
Due to the definition difference of SMRAM Save Sta= te,
SmmBase config in SMRAM Save State for AMD is also different.

This patch provides the AmdSmmRelocationLib library instance
to handle the SMRAM Save State difference.

Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zeng Star <star.zeng@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
---
 ...mmRelocationLib.inf =3D> AmdSmmRelocationLib.inf} |  5 +-<= br>  ...SaveStateConfig.c =3D> AmdSmramSaveStateConfig.c} | 93 ++++++++= ++------------
 UefiCpuPkg/UefiCpuPkg.dsc       &n= bsp;            = ;      |  1 +
 3 files changed, 46 insertions(+), 53 deletions(-)
 copy UefiCpuPkg/Library/SmmRelocationLib/{SmmRelocationLib.inf =3D>= ; AmdSmmRelocationLib.inf} (89%)
 copy UefiCpuPkg/Library/SmmRelocationLib/{SmramSaveStateConfig.c =3D&= gt; AmdSmramSaveStateConfig.c} (50%)

diff --git a/UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.inf b/Uef= iCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf
similarity index 89%
copy from UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.inf
copy to UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf
index 6581fa2dad..710cd1948b 100644
--- a/UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.inf
+++ b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf
@@ -13,18 +13,18 @@
 ##
 
 [Defines]
   INF_VERSION        &nb= sp;           =3D 0x00010= 005
   BASE_NAME         = ;             = =3D SmmRelocationLib
-  FILE_GUID         &nbs= p;            =3D 85= 3E97B3-790C-4EA3-945C-8F622FC47FE8
+  FILE_GUID         &nbs= p;            =3D 65= C74DCD-0D09-494A-8BFF-A64226EB8054
   MODULE_TYPE        &nb= sp;           =3D PEIM    VERSION_STRING        =          =3D 1.0
   LIBRARY_CLASS        &= nbsp;         =3D SmmRelocationLib<= br>  
 [Sources]
   InternalSmmRelocationLib.h
-  SmramSaveStateConfig.c
+  AmdSmramSaveStateConfig.c
   SmmRelocationLib.c
 
 [Sources.Ia32]
   Ia32/Semaphore.c
   Ia32/SmmInit.nasm
@@ -40,11 +40,10 @@
 
 [LibraryClasses]
   BaseLib
   BaseMemoryLib
   CpuExceptionHandlerLib
-  CpuLib
   DebugLib
   HobLib
   LocalApicLib
   MemoryAllocationLib
   PcdLib
diff --git a/UefiCpuPkg/Library/SmmRelocationLib/SmramSaveStateConfig.c b/U= efiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c
similarity index 50%
copy from UefiCpuPkg/Library/SmmRelocationLib/SmramSaveStateConfig.c
copy to UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c
index fb69b2b5c5..95a1ce8d46 100644
--- a/UefiCpuPkg/Library/SmmRelocationLib/SmramSaveStateConfig.c
+++ b/UefiCpuPkg/Library/SmmRelocationLib/AmdSmramSaveStateConfig.c
@@ -1,14 +1,17 @@
 /** @file
   Config SMRAM Save State for SmmBases Relocation.
 
+  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved= .<BR>
   Copyright (c) 2024, Intel Corporation. All rights reserved.<= ;BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 #include "InternalSmmRelocationLib.h"
-#include <Library/CpuLib.h>
+#include <Register/Amd/SmramSaveStateMap.h>
+
+#define EFER_ADDRESS  0XC0000080ul
 
 /**
   Determine the mode of the CPU at the time an SMI occurs
 
   @retval EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT   32 bi= t.
@@ -18,44 +21,18 @@
 UINT8
 CheckMmSaveStateRegisterLma (
   VOID
   )
 {
-  CPUID_VERSION_INFO_EAX      RegEax;
-  CPUID_EXTENDED_CPU_SIG_EDX  RegEdx;
-  UINTN          &n= bsp;            Fami= lyId;
-  UINTN          &n= bsp;            Mode= lId;
-  UINT32          &= nbsp;           Eax;
-  UINT8          &n= bsp;            SmmS= aveStateRegisterLma;
-
-  //
-  // Determine the mode of the CPU at the time an SMI occurs
-  //   Intel(R) 64 and IA-32 Architectures Software Develop= er's Manual
-  //   Volume 3C, Section 34.4.1.1
-  //
-  RegEax.Uint32 =3D GetCpuFamilyModel ();
-  FamilyId      =3D RegEax.Bits.FamilyId; -  ModelId       =3D RegEax.Bits.Model;<= br> -  if ((FamilyId =3D=3D 0x06) || (FamilyId =3D=3D 0x0f)) {
-    ModelId =3D ModelId | RegEax.Bits.ExtendedModelId <&= lt; 4;
-  }
+  UINT8   SmmSaveStateRegisterLma;
+  UINT32  LMAValue;
 
-  RegEdx.Uint32 =3D 0;
-  AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
-  if (Eax >=3D CPUID_EXTENDED_CPU_SIG) {
-    AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &am= p;(RegEdx.Uint32));
-  }
-
-  SmmSaveStateRegisterLma =3D EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT; -  if (RegEdx.Bits.LM) {
-    SmmSaveStateRegisterLma =3D EFI_MM_SAVE_STATE_REGISTER_= LMA_64BIT;
-  }
+  SmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;<= br>  
-  if (FamilyId =3D=3D 0x06) {
-    if ((ModelId =3D=3D 0x17) || (ModelId =3D=3D 0x0f) || (= ModelId =3D=3D 0x1c)) {
-      SmmSaveStateRegisterLma =3D EFI_MM_SAVE_STA= TE_REGISTER_LMA_64BIT;
-    }
+  LMAValue =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
+  if (LMAValue) {
+    SmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER= _LMA_64BIT;
   }
 
   return SmmSaveStateRegisterLma;
 }
 
@@ -73,18 +50,32 @@ EFIAPI
 ConfigureSmBase (
   IN     UINTN     =             CpuIndex= ,
   IN OUT SMRAM_SAVE_STATE_MAP  *CpuState
   )
 {
-  CpuState->x86.SMBASE =3D (UINT32)mSmBaseForAllCpus[CpuIndex]; +  AMD_SMRAM_SAVE_STATE_MAP  *AmdCpuState;
+
+  AmdCpuState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
+
+  AmdCpuState->x64.SMBASE =3D (UINT32)mSmBaseForAllCpus[CpuIndex];=
 }
 
 /**
-  Hook the code executed immediately after an RSM instruction on the = currently
-  executing CPU.  The mode of code executed immediately after RS= M must be
-  detected, and the appropriate hook must be selected.  Always c= lear the auto
-  HALT restart flag if it is set.
+  This function updates the SMRAM save state on the currently executi= ng CPU
+  to resume execution at a specific address after an RSM instruction.=   This
+  function must evaluate the SMRAM save state to determine the execut= ion mode
+  the RSM instruction resumes and update the resume execution address= with
+  either NewInstructionPointer32 or NewInstructionPoint.  The au= to HALT restart
+  flag in the SMRAM save state must always be cleared.  This fun= ction returns
+  the value of the instruction pointer from the SMRAM save state that= was
+  replaced.  If this function returns 0, then the SMRAM save sta= te was not
+  modified.
+
+  This function is called during the very first SMI on each CPU after=
+  SmmCpuFeaturesInitializeProcessor() to set a flag in normal executi= on mode
+  to signal that the SMBASE of each CPU has been updated before the d= efault
+  SMBASE address is used for the first SMI to the next CPU.
 
   @param[in]     CpuIndex   &= nbsp;           &nbs= p; The processor index for the currently
            &nb= sp;            =             &nb= sp;     executing CPU.
   @param[in,out] CpuState      &nb= sp;          Pointer to SMRAM = Save State Map for the
            &nb= sp;            =             &nb= sp;     currently executing CPU.
@@ -103,37 +94,39 @@ HookReturnFromSmm (
   IN OUT SMRAM_SAVE_STATE_MAP  *CpuState,
   IN     UINT64     = ;           NewInstructio= nPointer32,
   IN     UINT64     = ;           NewInstructio= nPointer
   )
 {
-  UINT64  OriginalInstructionPointer;
+  UINT64          &= nbsp;         OriginalInstructionPo= inter;
+  AMD_SMRAM_SAVE_STATE_MAP  *AmdCpuState;
 
-  if (CheckMmSaveStateRegisterLma () =3D=3D EFI_MM_SAVE_STATE_REGISTE= R_LMA_32BIT) {
-    OriginalInstructionPointer =3D (UINT64)CpuState->x86= ._EIP;
-    CpuState->x86._EIP     &nbs= p;   =3D (UINT32)NewInstructionPointer;
+  AmdCpuState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
 
+  if (CheckMmSaveStateRegisterLma () =3D=3D EFI_MM_SAVE_STATE_REGISTE= R_LMA_32BIT) {
+    OriginalInstructionPointer =3D (UINT64)AmdCpuState->= x86._EIP;
+    AmdCpuState->x86._EIP      = =3D (UINT32)NewInstructionPointer;
     //
     // Clear the auto HALT restart flag so the RSM ins= truction returns
     // program control to the instruction following th= e HLT instruction.
     //
-    if ((CpuState->x86.AutoHALTRestart & BIT0) !=3D = 0) {
-      CpuState->x86.AutoHALTRestart &=3D ~= BIT0;
+    if ((AmdCpuState->x86.AutoHALTRestart & BIT0) != =3D 0) {
+      AmdCpuState->x86.AutoHALTRestart &= =3D ~BIT0;
     }
   } else {
-    OriginalInstructionPointer =3D CpuState->x64._RIP; -    if ((CpuState->x64.IA32_EFER & LMA) =3D=3D 0) {<= br> -      CpuState->x64._RIP =3D (UINT32)NewInstru= ctionPointer32;
+    OriginalInstructionPointer =3D AmdCpuState->x64._RIP= ;
+    if ((AmdCpuState->x64.EFER & LMA) =3D=3D 0) { +      AmdCpuState->x64._RIP =3D (UINT32)NewIns= tructionPointer32;
     } else {
-      CpuState->x64._RIP =3D (UINT32)NewInstru= ctionPointer;
+      AmdCpuState->x64._RIP =3D (UINT32)NewIns= tructionPointer;
     }
 
     //
     // Clear the auto HALT restart flag so the RSM ins= truction returns
     // program control to the instruction following th= e HLT instruction.
     //
-    if ((CpuState->x64.AutoHALTRestart & BIT0) !=3D = 0) {
-      CpuState->x64.AutoHALTRestart &=3D ~= BIT0;
+    if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != =3D 0) {
+      AmdCpuState->x64.AutoHALTRestart &= =3D ~BIT0;
     }
   }
 
   return OriginalInstructionPointer;
 }
diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index dd2ad398c0..0c5fdcffde 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -195,10 +195,11 @@
   }
   UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
   UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf
   UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf<= br>    UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.inf
+  UefiCpuPkg/Library/SmmRelocationLib/AmdSmmRelocationLib.inf
 
 [Components.X64]
   UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExcep= tionHandlerLibUnitTest.inf
 
 [Components.RISCV64]
--
2.16.2.windows.1

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