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Thread-Topic: [PATCH v4] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay. 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Chiu, Chasel > Sent: Tuesday, April 4, 2023 2:34 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star ; Ni, > Ray ; Kuo, Ted > Subject: [PATCH v4] IntelFsp2Pkg: LoadMicrocodeDefault() causing > unnecessary delay. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4391 >=20 > FSP should support the scenario that CPU microcode already loaded > before calling LoadMicrocodeDefault(), in this case it should return > directly without spending more time. > Also the LoadMicrocodeDefault() should only attempt to load one version > of the microcode for current CPU and return directly without parsing > rest of the microcode in FV. >=20 > This patch also removed unnecessary LoadCheck code after supporting > CPU microcode already loaded scenario. >=20 > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Ray Ni > Signed-off-by: Chasel Chiu > Reviewed-by: Ted Kuo > --- > IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 46 > ++++++++++++++++++++++++---------------------- > IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 45 > ++++++++++++++++++++++++--------------------- > 2 files changed, 48 insertions(+), 43 deletions(-) >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > index 2cff8b3643..900126b93b 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > @@ -245,6 +245,22 @@ ASM_PFX(LoadMicrocodeDefault): > cmp esp, 0 >=20 > jz ParamError >=20 >=20 >=20 > + ; >=20 > + ; If microcode already loaded before this function, exit this functio= n with > SUCCESS. >=20 > + ; >=20 > + mov ecx, MSR_IA32_BIOS_SIGN_ID >=20 > + xor eax, eax ; Clear EAX >=20 > + xor edx, edx ; Clear EDX >=20 > + wrmsr ; Load 0 to MSR at 8Bh >=20 > + >=20 > + mov eax, 1 >=20 > + cpuid >=20 > + mov ecx, MSR_IA32_BIOS_SIGN_ID >=20 > + rdmsr ; Get current microcode signature >=20 > + xor eax, eax >=20 > + test edx, edx >=20 > + jnz Exit2 >=20 > + >=20 > ; skip loading Microcode if the MicrocodeCodeSize is zero >=20 > ; and report error if size is less than 2k >=20 > ; first check UPD header revision >=20 > @@ -330,7 +346,7 @@ CheckMainHeader: > cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor] >=20 > jne LoadMicrocodeDefault1 >=20 > test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ] >=20 > - jnz LoadCheck ; Jif signature and platform ID match >=20 > + jnz LoadMicrocode ; Jif signature and platform ID match >=20 >=20 >=20 > LoadMicrocodeDefault1: >=20 > ; Check if extended header exists >=20 > @@ -363,7 +379,7 @@ CheckExtSig: > cmp dword [edi + ExtSig.ExtSigProcessor], ebx >=20 > jne LoadMicrocodeDefault2 >=20 > test dword [edi + ExtSig.ExtSigFlags], edx >=20 > - jnz LoadCheck ; Jif signature and platform ID match >=20 > + jnz LoadMicrocode ; Jif signature and platform ID match >=20 > LoadMicrocodeDefault2: >=20 > ; Check if any more extended signatures exist >=20 > add edi, ExtSig.size >=20 > @@ -435,23 +451,7 @@ LoadMicrocodeDefault4: > ; Is valid Microcode start point ? >=20 > cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh >=20 > jz Done >=20 > - >=20 > -LoadCheck: >=20 > - ; Get the revision of the current microcode update loaded >=20 > - mov ecx, MSR_IA32_BIOS_SIGN_ID >=20 > - xor eax, eax ; Clear EAX >=20 > - xor edx, edx ; Clear EDX >=20 > - wrmsr ; Load 0 to MSR at 8Bh >=20 > - >=20 > - mov eax, 1 >=20 > - cpuid >=20 > - mov ecx, MSR_IA32_BIOS_SIGN_ID >=20 > - rdmsr ; Get current microcode signature >=20 > - >=20 > - ; Verify this microcode update is not already loaded >=20 > - cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx >=20 > - je Continue >=20 > - >=20 > + jmp CheckMainHeader >=20 > LoadMicrocode: >=20 > ; EAX contains the linear address of the start of the Update Data >=20 > ; EDX contains zero >=20 > @@ -465,10 +465,12 @@ LoadMicrocode: > mov eax, 1 >=20 > cpuid >=20 >=20 >=20 > -Continue: >=20 > - jmp NextMicrocode >=20 > - >=20 > Done: >=20 > + mov ecx, MSR_IA32_BIOS_SIGN_ID >=20 > + xor eax, eax ; Clear EAX >=20 > + xor edx, edx ; Clear EDX >=20 > + wrmsr ; Load 0 to MSR at 8Bh >=20 > + >=20 > mov eax, 1 >=20 > cpuid >=20 > mov ecx, MSR_IA32_BIOS_SIGN_ID >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > index b32fa32a89..698bb063a7 100644 > --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > @@ -141,6 +141,22 @@ ASM_PFX(LoadMicrocodeDefault): > jz ParamError >=20 > mov rsp, rcx >=20 >=20 >=20 > + ; >=20 > + ; If microcode already loaded before this function, exit this functio= n with > SUCCESS. >=20 > + ; >=20 > + mov ecx, MSR_IA32_BIOS_SIGN_ID >=20 > + xor eax, eax ; Clear EAX >=20 > + xor edx, edx ; Clear EDX >=20 > + wrmsr ; Load 0 to MSR at 8Bh >=20 > + >=20 > + mov eax, 1 >=20 > + cpuid >=20 > + mov ecx, MSR_IA32_BIOS_SIGN_ID >=20 > + rdmsr ; Get current microcode signature >=20 > + xor rax, rax >=20 > + test edx, edx >=20 > + jnz Exit2 >=20 > + >=20 > ; skip loading Microcode if the MicrocodeCodeSize is zero >=20 > ; and report error if size is less than 2k >=20 > ; first check UPD header revision >=20 > @@ -198,7 +214,7 @@ CheckMainHeader: > cmp ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor] >=20 > jne LoadMicrocodeDefault1 >=20 > test edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ] >=20 > - jnz LoadCheck ; Jif signature and platform ID match >=20 > + jnz LoadMicrocode ; Jif signature and platform ID match >=20 >=20 >=20 > LoadMicrocodeDefault1: >=20 > ; Check if extended header exists >=20 > @@ -231,7 +247,7 @@ CheckExtSig: > cmp dword [edi + ExtSig.ExtSigProcessor], ebx >=20 > jne LoadMicrocodeDefault2 >=20 > test dword [edi + ExtSig.ExtSigFlags], edx >=20 > - jnz LoadCheck ; Jif signature and platform ID match >=20 > + jnz LoadMicrocode ; Jif signature and platform ID match >=20 > LoadMicrocodeDefault2: >=20 > ; Check if any more extended signatures exist >=20 > add edi, ExtSig.size >=20 > @@ -276,22 +292,7 @@ LoadMicrocodeDefault4: > ; Is valid Microcode start point ? >=20 > cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh >=20 > jz Done >=20 > - >=20 > -LoadCheck: >=20 > - ; Get the revision of the current microcode update loaded >=20 > - mov ecx, MSR_IA32_BIOS_SIGN_ID >=20 > - xor eax, eax ; Clear EAX >=20 > - xor edx, edx ; Clear EDX >=20 > - wrmsr ; Load 0 to MSR at 8Bh >=20 > - >=20 > - mov eax, 1 >=20 > - cpuid >=20 > - mov ecx, MSR_IA32_BIOS_SIGN_ID >=20 > - rdmsr ; Get current microcode signature >=20 > - >=20 > - ; Verify this microcode update is not already loaded >=20 > - cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx >=20 > - je Continue >=20 > + jmp CheckMainHeader >=20 >=20 >=20 > LoadMicrocode: >=20 > ; EAX contains the linear address of the start of the Update Data >=20 > @@ -306,10 +307,12 @@ LoadMicrocode: > mov eax, 1 >=20 > cpuid >=20 >=20 >=20 > -Continue: >=20 > - jmp NextMicrocode >=20 > - >=20 > Done: >=20 > + mov ecx, MSR_IA32_BIOS_SIGN_ID >=20 > + xor eax, eax ; Clear EAX >=20 > + xor edx, edx ; Clear EDX >=20 > + wrmsr ; Load 0 to MSR at 8Bh >=20 > + >=20 > mov eax, 1 >=20 > cpuid >=20 > mov ecx, MSR_IA32_BIOS_SIGN_ID >=20 > -- > 2.35.0.windows.1