From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 72586940E93 for ; Wed, 6 Dec 2023 01:09:13 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=omXMcW4y190QY6pzlCLI2zKb2vJFpgYONiKiAMTXpnU=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1701824952; v=1; b=IoApFU/8kiwVAY7cdVljimonDJ0ZiXOa2P0LbcCF/dyrG7asAoemw7wDM4g7ibBJZWcuJY3s nuJBbRrKMB4I3g9HDnoYfmVLx5iwF3jhesfzXo5kDuNA2+s6eV7bmhVfQoqptG+DMKrZLwU2J0t 8ock/Q1X4MtaHv6bYJXtnino= X-Received: by 127.0.0.2 with SMTP id 0lMyYY7687511x6tQ7SyhyV3; Tue, 05 Dec 2023 17:09:12 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mx.groups.io with SMTP id smtpd.web10.18468.1701824951028561651 for ; Tue, 05 Dec 2023 17:09:11 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="1073006" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="1073006" X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2023 17:09:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="889141010" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="889141010" X-Received: from orsmsx601.amr.corp.intel.com ([10.22.229.14]) by fmsmga002.fm.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 05 Dec 2023 17:09:07 -0800 X-Received: from orsmsx612.amr.corp.intel.com (10.22.229.25) by ORSMSX601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 5 Dec 2023 17:09:04 -0800 X-Received: from orsmsx611.amr.corp.intel.com (10.22.229.24) by ORSMSX612.amr.corp.intel.com (10.22.229.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 5 Dec 2023 17:09:04 -0800 X-Received: from orsedg603.ED.cps.intel.com (10.7.248.4) by orsmsx611.amr.corp.intel.com (10.22.229.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Tue, 5 Dec 2023 17:09:04 -0800 X-Received: from NAM11-DM6-obe.outbound.protection.outlook.com (104.47.57.168) by edgegateway.intel.com (134.134.137.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.34; Tue, 5 Dec 2023 17:09:03 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lQhh0/nFSWeg6h5XSyMh4ZBPHQ3xe6P+StVYOpQHOAYH3Ng6VmofV7zvlDS2Wn1dYS62NNUajDq7yz22G/j1/Vv6rNI2nj0cQdC8Idl/iklmlAZUbfDs7Rlt1Q/N7iQlWQOvbrVRdLMVX8qu116KQdS45SmTb6pRUENI/dohDpbqK4/jl+B+cWrMva40MKDJJjn2lokFnW0MSFzV7FSXStAsi03RsHd/Ak3jBLrjDQgzFOvPDDPPdK6qMMJvIGZqYdF8+7NjJsYUsAwNDy47NoyoLpBJCgqPuMVawBu4J7QmmRevcNDA+t+WxE8GZMqKHs7HUWWyOWDcH1fkJQ+FOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2+3kqxFU3YSnhlSAPGzTLtnXlMAbDLzzBmgr/NJDLkM=; b=WAKKKc8iiaSGM5Ef77/NVqVJILEUOwoV/cbUg8SuxULQoXDIbzEf/a/udVc3e3/ZXNcNLwPB0FFqJl1UDhunAJ6XrAgRoM3Wjko3AOWwy0PO9jiGvyVCMyiBFTnVkK3czr1KZeQomDAmiRD0wNzZi1mnFkyYXbQYYvQyzYUZb71Gke8edtBi78cuGEe9IGAcYvd1OcOAbaIqOuW6t2Dmlw/H35CzITRSc44JQpUmSUQBcluaKySGcd2EeigKkhL6evJuMqnCo6xEs7oDmg/mymVt3RIQGbIlvS9sYaod3L+srAxiDUn9vISwlZmhOxSHowDbxX0qri5TXIuRkzJ1Iw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none X-Received: from MN6PR11MB8244.namprd11.prod.outlook.com (2603:10b6:208:470::14) by IA0PR11MB8334.namprd11.prod.outlook.com (2603:10b6:208:483::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.34; Wed, 6 Dec 2023 01:08:56 +0000 X-Received: from MN6PR11MB8244.namprd11.prod.outlook.com ([fe80::b614:1f5e:8b0c:9858]) by MN6PR11MB8244.namprd11.prod.outlook.com ([fe80::b614:1f5e:8b0c:9858%4]) with mapi id 15.20.7046.034; Wed, 6 Dec 2023 01:08:53 +0000 From: "Ni, Ray" To: "Wu, Jiaxin" , "devel@edk2.groups.io" CC: Laszlo Ersek , "Dong, Eric" , "Zeng, Star" , Gerd Hoffmann , "Kumar, Rahul R" Subject: Re: [edk2-devel] [PATCH v2 2/6] UefiCpuPkg: Adds SmmCpuSyncLib library class Thread-Topic: [PATCH v2 2/6] UefiCpuPkg: Adds SmmCpuSyncLib library class Thread-Index: AQHaI1byq+QZ/ldByEWMbLmzyvN9irCbejVA Date: Wed, 6 Dec 2023 01:08:53 +0000 Message-ID: References: <20231130063139.7472-1-jiaxin.wu@intel.com> <20231130063139.7472-3-jiaxin.wu@intel.com> In-Reply-To: <20231130063139.7472-3-jiaxin.wu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MN6PR11MB8244:EE_|IA0PR11MB8334:EE_ x-ms-office365-filtering-correlation-id: c5ae1590-fdbf-484b-ab3b-08dbf5f7e9d6 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: hNoC55LhpGX6D4lYrLNxIqMUnPofBe1NH78g2xu9ZeTpZvjWPwc0Fl34Qv/yFS1eaq9dgPhoQk3E+0iXvA1+bt8Sr3GHOsvryV4Rtr3UxzpLV4ps3RNoXcXGCwBOeNzm0cJufo2LxOQ0bmTngVgOlq7y6aJsxGDEuxMRHPeYTP5csZcZm50Kpp+bsoYD6jv3qAC8OisDFcV0q4r9S0FGN5dCM15rwxQNGqzKJnD56i5dtna90qo6LWnPKgrFQod4KXS/TiJXYTpVQwOPeKO2DqEBVW7BrebssDt0+xSPa8UCmKQClpgybulV9saLC2cBhBISUroDsUsDTxx/gCFPlngcgSHSuKEv2h38IqxV/i2GjuHBZ+HBxOsuudvIR6KRNEq5kKrRXqKBf/IT8Zfsb2EGq+ab/OmYyUZsM96gBTnEcaZ9NBuMUm00EnaqUADBR64EbygYrsgqjqhjAoE4dAcG4T61Snym9sqwBzFGjY2TocKeyT9H6FAKfJ6dNx0YTAWRIwns5uo3NasaKozbmjsZemxzl2nMnQ0B3O1m5PraKRCgXRpM9+gDdEN+fFavD68iO5GK85ByAm2O2121keqbPsG2pc3fsxKjXKlqJu64Pup/IBC1MyGK0l69eVVa x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?eR5BjQdsntilt6FCw5NsGPPEx6sbVEqCtOjGJ1sB9/kj8WeBTCZoxU8cM/SS?= =?us-ascii?Q?0O31mh2NEmkMLqndZRB99QKhJi4oEmUmawtYbFP6npTJzeCquOrFNAB6VFqK?= =?us-ascii?Q?ooMRW7XvjpGFepf+KeXS6hv3SqOHvwq3KVPq48E3l/n9sl5ccYhhlDszoxZ3?= =?us-ascii?Q?X8V9dhRZu10vGVH4QC3vTibujZU5ZBGFRlIO/w5mOuuafEq5pkeBRAoQZ/nb?= =?us-ascii?Q?Q022v23lV23U2A8opqRQbL3/yYPBQktljT6as9UMU+hjXGkzSGRiXm5DGrvY?= =?us-ascii?Q?+2OybEvfGJJsi7N+GW7QP4M/63KOXbg5MqElKW0IkMKS2hCIXbJw+tTVL2aG?= =?us-ascii?Q?/G3btRf1W4h/fncgLG2w3GD1Fz/FhdhZytZd9Dc55XjUMf56vV8nVlTXqeJQ?= =?us-ascii?Q?CR29cV0UVu3qonwj8oWGrMtRmGmZf7twq/F2H2ZYwt/5LgQpegiULmHYRI6e?= =?us-ascii?Q?F/z/MH84nlv4yyh53KTVYuhkc4frB78CN5ROSNwfUhOSSOPVtAsryHRbjjVW?= =?us-ascii?Q?qpEMlIHwGGgKBf+JTXT2SGswkaMskpy2WoRCYVEAFMTn04ML31hlb1NQFXya?= =?us-ascii?Q?gbteRxhoVv+k/Ijcd3UV+PyUSkBsBFSjaXnBvRXgoipn94wvWSka1vfqbbfD?= =?us-ascii?Q?C/+fx/igg4sbC7kiiIG2oi0GFzRomfdh6c1nybstllaJ+49St0wzWKvp+l5O?= =?us-ascii?Q?bq0NPUKsxFUjYJ9o1w1BrCeNBwqG/jAqlVmljL/buGAuqvofciJ+Bz6bt88z?= =?us-ascii?Q?P2RaHtJ6Xtbu1tNMww6jgFXs/5yXnmc+sOqcgoTiLtRMCQ+8tFhuD4vblrZz?= =?us-ascii?Q?jbQns6kQNnncjjcFpMIrkUennyhucdbTtjzfVcxzV4MTaPF8UxQbWGn+Cqcz?= =?us-ascii?Q?xcYJbOnuu3oAtePGoybCY2tDhv2Is342C7vIgRI9kS5NJxxhe3/Ey5Hh+95D?= =?us-ascii?Q?Owk37evLCX6DsGfU+q4zWj+K68hlFa4kpyUkaccKfc3TkHohzoO2e7BhQ11l?= =?us-ascii?Q?UIsXU6E3kyBtCyto32o3822zrbHgJ0+FW9rhqJLW/hrUvwUJS8SH929sc8zJ?= =?us-ascii?Q?mKZqemGOCmsQkk4+d6umuAFXwkFuYQI42657NNH8DKf+uLYAtbLFBiNAZIJ1?= =?us-ascii?Q?chJ4h3DG3N5CEBb0nkQWq2FbFo7+BOrX415pAFCPQ3ZsuKtP9xD6MH01zpz5?= =?us-ascii?Q?vNXGzfxclV/Pr/t94TfMyeSYSMYIQ+NASN5BqYWKCQ+8QvH6mHMJ1YjKhokE?= =?us-ascii?Q?+Kamg8SnAA/u1+Q9mjwLlRGcw5JlUq7ySPH4APFaOdcsIubpS90UKRMwd4St?= =?us-ascii?Q?uFRLlpDBW3OTDh8T4g/Y82Hpaf5aZ49dhgf7BFpE6PZ7ThLjhhcvEeXnjqBa?= =?us-ascii?Q?GMG6qepheyPRIyhuowkCDAVCx66hJgfMDpSZ+/JZXlssFo11OjqjtBMF979t?= =?us-ascii?Q?H8TFLwDjdQALO8WqZSqADE4pUiopGaLOewpR0X+lPxn9k9B+GVTZuEmp6m/u?= =?us-ascii?Q?q4l6zJf1n1FEiVwNdST303qVL6GEmINc/p4ylm2uP3vKhKoF8A2Mvg/adT+D?= =?us-ascii?Q?CBt+dHQnAqwCxiRAZMw=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN6PR11MB8244.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c5ae1590-fdbf-484b-ab3b-08dbf5f7e9d6 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Dec 2023 01:08:53.1474 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: h/Wkf3Q7xmfOMmrOuUyQv5VsymqbfAHJEFfCG67p8Vh+V1ZwLz4Poy31zTysPZiOOCiUwpvKyR4vGT4v7DExzQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR11MB8334 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: LLjPq3EzxvTszOAqc2NTVOadx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="IoApFU/8"; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Patch is good to me. Only one comment: The file header comments should have 2 space chars in the= beginning of each line. Thanks, Ray > -----Original Message----- > From: Wu, Jiaxin > Sent: Thursday, November 30, 2023 2:32 PM > To: devel@edk2.groups.io > Cc: Laszlo Ersek ; Dong, Eric ; N= i, > Ray ; Zeng, Star ; Gerd Hoffmann > ; Kumar, Rahul R > Subject: [PATCH v2 2/6] UefiCpuPkg: Adds SmmCpuSyncLib library class >=20 > Intel is planning to provide different SMM CPU Sync implementation > along with some specific registers to improve the SMI performance, > hence need SmmCpuSyncLib Library for Intel. >=20 > This patch is to: > 1.Adds SmmCpuSyncLib Library class in UefiCpuPkg.dec. > 2.Adds SmmCpuSyncLib.h function declaration header file. >=20 > For the new SmmCpuSyncLib, it provides 3 sets of APIs: >=20 > 1. ContextInit/ContextDeinit/ContextReset: > ContextInit() is called in driver's entrypoint to allocate and > initialize the SMM CPU Sync context. ContextDeinit() is called in > driver's unload function to deinitialize SMM CPU Sync context. > ContextReset() is called before CPU exist SMI, which allows CPU to > check into the next SMI from this point. >=20 > 2. GetArrivedCpuCount/CheckInCpu/CheckOutCpu/LockDoor: > When SMI happens, all processors including BSP enter to SMM mode by > calling CheckInCpu(). The elected BSP calls LockDoor() so that > CheckInCpu() will return the error code after that. CheckOutCpu() can > be called in error handling flow for the CPU who calls CheckInCpu() > earlier. GetArrivedCpuCount() returns the number of checked-in CPUs. >=20 > 3. WaitForAPs/ReleaseOneAp/WaitForBsp/ReleaseBsp > WaitForAPs() & ReleaseOneAp() are called from BSP to wait the number > of APs and release one specific AP. WaitForBsp() & ReleaseBsp() are > called from APs to wait and release BSP. The 4 APIs are used to > synchronize the running flow among BSP and APs. BSP and AP Sync flow > can be easy understand as below: > BSP: ReleaseOneAp --> AP: WaitForBsp > BSP: WaitForAPs <-- AP: ReleaseBsp >=20 > Cc: Laszlo Ersek > Cc: Eric Dong > Cc: Ray Ni > Cc: Zeng Star > Cc: Gerd Hoffmann > Cc: Rahul Kumar > Signed-off-by: Jiaxin Wu > --- > UefiCpuPkg/Include/Library/SmmCpuSyncLib.h | 278 > +++++++++++++++++++++++++++++ > UefiCpuPkg/UefiCpuPkg.dec | 3 + > 2 files changed, 281 insertions(+) > create mode 100644 UefiCpuPkg/Include/Library/SmmCpuSyncLib.h >=20 > diff --git a/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h > b/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h > new file mode 100644 > index 0000000000..22935cc006 > --- /dev/null > +++ b/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h > @@ -0,0 +1,278 @@ > +/** @file > +Library that provides SMM CPU Sync related operations. > +The lib provides 3 sets of APIs: > +1. ContextInit/ContextDeinit/ContextReset: > +ContextInit() is called in driver's entrypoint to allocate and initializ= e the SMM > CPU Sync context. > +ContextDeinit() is called in driver's unload function to deinitialize th= e SMM > CPU Sync context. > +ContextReset() is called before CPU exist SMI, which allows CPU to check > into the next SMI from this point. > + > +2. GetArrivedCpuCount/CheckInCpu/CheckOutCpu/LockDoor: > +When SMI happens, all processors including BSP enter to SMM mode by > calling CheckInCpu(). > +The elected BSP calls LockDoor() so that CheckInCpu() will return the er= ror > code after that. > +CheckOutCpu() can be called in error handling flow for the CPU who calls > CheckInCpu() earlier. > +GetArrivedCpuCount() returns the number of checked-in CPUs. > + > +3. WaitForAPs/ReleaseOneAp/WaitForBsp/ReleaseBsp > +WaitForAPs() & ReleaseOneAp() are called from BSP to wait the number of > APs and release one specific AP. > +WaitForBsp() & ReleaseBsp() are called from APs to wait and release BSP. > +The 4 APIs are used to synchronize the running flow among BSP and APs. B= SP > and AP Sync flow can be > +easy understand as below: > +BSP: ReleaseOneAp --> AP: WaitForBsp > +BSP: WaitForAPs <-- AP: ReleaseBsp > + > +Copyright (c) 2023, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef SMM_CPU_SYNC_LIB_H_ > +#define SMM_CPU_SYNC_LIB_H_ > + > +#include > + > +// > +// Opaque structure for SMM CPU Sync context. > +// > +typedef struct SMM_CPU_SYNC_CTX SMM_CPU_SYNC_CTX; > + > +/** > + Create and initialize the SMM CPU Sync context. > + > + SmmCpuSyncContextInit() function is to allocate and initialize the SMM > CPU Sync context. > + > + @param[in] NumberOfCpus The number of Logical > Processors in the system. > + @param[out] SmmCpuSyncCtx Pointer to the new created and > initialized SMM CPU Sync context object. > + NULL will be returned if any > error happen during init. > + > + @retval RETURN_SUCCESS The SMM CPU Sync context > was successful created and initialized. > + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. > + @retval RETURN_BUFFER_TOO_SMALL Overflow happen > + @retval RETURN_OUT_OF_RESOURCES There are not enough > resources available to create and initialize SMM CPU Sync context. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SmmCpuSyncContextInit ( > + IN UINTN NumberOfCpus, > + OUT SMM_CPU_SYNC_CTX **SmmCpuSyncCtx > + ); > + > +/** > + Deinit an allocated SMM CPU Sync context. > + > + SmmCpuSyncContextDeinit() function is to deinitialize SMM CPU Sync > context, the resources allocated in > + SmmCpuSyncContextInit() will be freed. > + > + Note: This function only can be called after SmmCpuSyncContextInit() > return success. > + > + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync > context object to be deinitialized. > + > + @retval RETURN_SUCCESS The SMM CPU Sync context > was successful deinitialized. > + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SmmCpuSyncContextDeinit ( > + IN OUT SMM_CPU_SYNC_CTX *SmmCpuSyncCtx > + ); > + > +/** > + Reset SMM CPU Sync context. > + > + SmmCpuSyncContextReset() function is to reset SMM CPU Sync context to > the initialized state. > + > + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync > context object to be reset. > + > + @retval RETURN_SUCCESS The SMM CPU Sync context > was successful reset. > + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SmmCpuSyncContextReset ( > + IN OUT SMM_CPU_SYNC_CTX *SmmCpuSyncCtx > + ); > + > +/** > + Get current number of arrived CPU in SMI. > + > + For traditional CPU synchronization method, BSP might need to know the > current number of arrived CPU in > + SMI to make sure all APs in SMI. This API can be for that purpose. > + > + @param[in] SmmCpuSyncCtx Pointer to the SMM CPU Sync > context object. > + @param[in,out] CpuCount Current count of arrived CPU in > SMI. > + > + @retval RETURN_SUCCESS Get current number of arrived > CPU in SMI successfully. > + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx or CpuCount > is NULL. > + @retval RETURN_ABORTED Function Aborted due to the > door has been locked by SmmCpuSyncLockDoor() function. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SmmCpuSyncGetArrivedCpuCount ( > + IN SMM_CPU_SYNC_CTX *SmmCpuSyncCtx, > + IN OUT UINTN *CpuCount > + ); > + > +/** > + Performs an atomic operation to check in CPU. > + > + When SMI happens, all processors including BSP enter to SMM mode by > calling SmmCpuSyncCheckInCpu(). > + > + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync > context object. > + @param[in] CpuIndex Check in CPU index. > + > + @retval RETURN_SUCCESS Check in CPU (CpuIndex) > successfully. > + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. > + @retval RETURN_ABORTED Check in CPU failed due to > SmmCpuSyncLockDoor() has been called by one elected CPU. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SmmCpuSyncCheckInCpu ( > + IN OUT SMM_CPU_SYNC_CTX *SmmCpuSyncCtx, > + IN UINTN CpuIndex > + ); > + > +/** > + Performs an atomic operation to check out CPU. > + > + CheckOutCpu() can be called in error handling flow for the CPU who cal= ls > CheckInCpu() earlier. > + > + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync > context object. > + @param[in] CpuIndex Check out CPU index. > + > + @retval RETURN_SUCCESS Check out CPU (CpuIndex) > successfully. > + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL. > + @retval RETURN_NOT_READY The CPU is not checked-in. > + @retval RETURN_ABORTED Check out CPU failed due to > SmmCpuSyncLockDoor() has been called by one elected CPU. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SmmCpuSyncCheckOutCpu ( > + IN OUT SMM_CPU_SYNC_CTX *SmmCpuSyncCtx, > + IN UINTN CpuIndex > + ); > + > +/** > + Performs an atomic operation lock door for CPU checkin or checkout. > + > + After this function: > + CPU can not check in via SmmCpuSyncCheckInCpu(). > + CPU can not check out via SmmCpuSyncCheckOutCpu(). > + CPU can not get number of arrived CPU in SMI via > SmmCpuSyncGetArrivedCpuCount(). The number of > + arrived CPU in SMI will be returned in CpuCount. > + > + The CPU specified by CpuIndex is elected to lock door. > + > + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync > context object. > + @param[in] CpuIndex Indicate which CPU to lock door. > + @param[in,out] CpuCount Number of arrived CPU in SMI > after look door. > + > + @retval RETURN_SUCCESS Lock door for CPU successfully. > + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx or CpuCount > is NULL. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SmmCpuSyncLockDoor ( > + IN OUT SMM_CPU_SYNC_CTX *SmmCpuSyncCtx, > + IN UINTN CpuIndex, > + IN OUT UINTN *CpuCount > + ); > + > +/** > + Used by the BSP to wait for APs. > + > + The number of APs need to be waited is specified by NumberOfAPs. The > BSP is specified by BspIndex. > + > + Note: This function is blocking mode, and it will return only after th= e > number of APs released by > + calling SmmCpuSyncReleaseBsp(): > + BSP: WaitForAPs <-- AP: ReleaseBsp > + > + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync > context object. > + @param[in] NumberOfAPs Number of APs need to be > waited by BSP. > + @param[in] BspIndex The BSP Index to wait for APs. > + > + @retval RETURN_SUCCESS BSP to wait for APs > successfully. > + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or > NumberOfAPs > total number of processors in system. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SmmCpuSyncWaitForAPs ( > + IN OUT SMM_CPU_SYNC_CTX *SmmCpuSyncCtx, > + IN UINTN NumberOfAPs, > + IN UINTN BspIndex > + ); > + > +/** > + Used by the BSP to release one AP. > + > + The AP is specified by CpuIndex. The BSP is specified by BspIndex. > + > + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync > context object. > + @param[in] CpuIndex Indicate which AP need to be > released. > + @param[in] BspIndex The BSP Index to release AP. > + > + @retval RETURN_SUCCESS BSP to release one AP > successfully. > + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or > CpuIndex is same as BspIndex. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SmmCpuSyncReleaseOneAp ( > + IN OUT SMM_CPU_SYNC_CTX *SmmCpuSyncCtx, > + IN UINTN CpuIndex, > + IN UINTN BspIndex > + ); > + > +/** > + Used by the AP to wait BSP. > + > + The AP is specified by CpuIndex. The BSP is specified by BspIndex. > + > + Note: This function is blocking mode, and it will return only after th= e AP > released by > + calling SmmCpuSyncReleaseOneAp(): > + BSP: ReleaseOneAp --> AP: WaitForBsp > + > + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync > context object. > + @param[in] CpuIndex Indicate which AP wait BSP. > + @param[in] BspIndex The BSP Index to be waited. > + > + @retval RETURN_SUCCESS AP to wait BSP successfully. > + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or > CpuIndex is same as BspIndex. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SmmCpuSyncWaitForBsp ( > + IN OUT SMM_CPU_SYNC_CTX *SmmCpuSyncCtx, > + IN UINTN CpuIndex, > + IN UINTN BspIndex > + ); > + > +/** > + Used by the AP to release BSP. > + > + The AP is specified by CpuIndex. The BSP is specified by BspIndex. > + > + @param[in,out] SmmCpuSyncCtx Pointer to the SMM CPU Sync > context object. > + @param[in] CpuIndex Indicate which AP release BSP. > + @param[in] BspIndex The BSP Index to be released. > + > + @retval RETURN_SUCCESS AP to release BSP successfully. > + @retval RETURN_INVALID_PARAMETER SmmCpuSyncCtx is NULL or > CpuIndex is same as BspIndex. > + > +**/ > +RETURN_STATUS > +EFIAPI > +SmmCpuSyncReleaseBsp ( > + IN OUT SMM_CPU_SYNC_CTX *SmmCpuSyncCtx, > + IN UINTN CpuIndex, > + IN UINTN BspIndex > + ); > + > +#endif > diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec > index 0b5431dbf7..20ab079219 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dec > +++ b/UefiCpuPkg/UefiCpuPkg.dec > @@ -62,10 +62,13 @@ > CpuPageTableLib|Include/Library/CpuPageTableLib.h >=20 > ## @libraryclass Provides functions for manipulating smram savestate > registers. > MmSaveStateLib|Include/Library/MmSaveStateLib.h >=20 > + ## @libraryclass Provides functions for SMM CPU Sync Operation. > + SmmCpuSyncLib|Include/Library/SmmCpuSyncLib.h > + > [LibraryClasses.RISCV64] > ## @libraryclass Provides functions to manage MMU features on > RISCV64 CPUs. > ## > RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h >=20 > -- > 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112086): https://edk2.groups.io/g/devel/message/112086 Mute This Topic: https://groups.io/mt/102889292/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/19134562= 12/xyzzy [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-