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charset="us-ascii" Content-Transfer-Encoding: quoted-printable I failed to apply the patch in my local tree. It seems you invented a new EdkiiRootBridgeIo protocol and a certain propri= etary driver would produce this protocol instance. Then the open source PciHostBridge driver starts on that. Then, why not implement your own PciHostBridgeLib and let it depends on som= e "AllRootBridgeIoInformationIsReady" protocol. So that the PciHostBridge driver could still call PciHostBridgeLib and all = your implementation in this patch can be in that lib. Thanks, Ray > -----Original Message----- > From: Jeff Brasen > Sent: Friday, June 30, 2023 4:54 AM > To: devel@edk2.groups.io > Cc: Wang, Jian J ; Gao, Liming > ; Wu, Hao A ; Ni, Ray > ; Jeff Brasen > Subject: [PATCH] MdeModulePkg/PciHostBridge: Add support for driver bindi= ng >=20 > If the platform does not support any PCIe devices using the library >=20 > method allow devices to connect to host bridge via driver binding. >=20 >=20 >=20 > Signed-off-by: Jeff Brasen >=20 > --- >=20 > .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 649 ++++++++++++++---- >=20 > .../Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf | 1 + >=20 > .../Bus/Pci/PciHostBridgeDxe/PciRootBridge.h | 13 + >=20 > .../Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 24 + >=20 > MdeModulePkg/MdeModulePkg.dec | 4 + >=20 > 5 files changed, 562 insertions(+), 129 deletions(-) >=20 >=20 >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c > b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c >=20 > index d573e532ba..506c6660ae 100644 >=20 > --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c >=20 > +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c >=20 > @@ -422,167 +422,320 @@ IoMmuProtocolCallback ( >=20 > } >=20 >=20 >=20 > /** >=20 > + PCI Root Bridge Memory setup. >=20 >=20 >=20 > - Entry point of this driver. >=20 > + @param RootBridge Root Bridge instance. >=20 >=20 >=20 > - @param ImageHandle Image handle of this driver. >=20 > - @param SystemTable Pointer to standard EFI system table. >=20 > - >=20 > - @retval EFI_SUCCESS Succeed. >=20 > - @retval EFI_DEVICE_ERROR Fail to install PCI_ROOT_BRIDGE_IO protocol. >=20 > + @retval EFI_SUCCESS Memory was setup correctly >=20 > + @retval others Error in setup >=20 >=20 >=20 > **/ >=20 > EFI_STATUS >=20 > EFIAPI >=20 > -InitializePciHostBridge ( >=20 > - IN EFI_HANDLE ImageHandle, >=20 > - IN EFI_SYSTEM_TABLE *SystemTable >=20 > +PciRootBridgeMemorySetup ( >=20 > + IN PCI_ROOT_BRIDGE *RootBridge >=20 > ) >=20 > { >=20 > EFI_STATUS Status; >=20 > - PCI_HOST_BRIDGE_INSTANCE *HostBridge; >=20 > - PCI_ROOT_BRIDGE_INSTANCE *RootBridge; >=20 > - PCI_ROOT_BRIDGE *RootBridges; >=20 > - UINTN RootBridgeCount; >=20 > - UINTN Index; >=20 > + UINT64 HostAddress; >=20 > PCI_ROOT_BRIDGE_APERTURE *MemApertures[4]; >=20 > UINTN MemApertureIndex; >=20 > - BOOLEAN ResourceAssigned; >=20 > - LIST_ENTRY *Link; >=20 > - UINT64 HostAddress; >=20 >=20 >=20 > - RootBridges =3D PciHostBridgeGetRootBridges (&RootBridgeCount); >=20 > - if ((RootBridges =3D=3D NULL) || (RootBridgeCount =3D=3D 0)) { >=20 > - return EFI_UNSUPPORTED; >=20 > - } >=20 > - >=20 > - Status =3D gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID > **)&mCpuIo); >=20 > - ASSERT_EFI_ERROR (Status); >=20 > - >=20 > - // >=20 > - // Most systems in the world including complex servers have only one H= ost > Bridge. >=20 > - // >=20 > - HostBridge =3D AllocateZeroPool (sizeof (PCI_HOST_BRIDGE_INSTANCE)); >=20 > - ASSERT (HostBridge !=3D NULL); >=20 > - >=20 > - HostBridge->Signature =3D PCI_HOST_BRIDGE_SIGNATURE; >=20 > - HostBridge->CanRestarted =3D TRUE; >=20 > - InitializeListHead (&HostBridge->RootBridges); >=20 > - ResourceAssigned =3D FALSE; >=20 > - >=20 > - // >=20 > - // Create Root Bridge Device Handle in this Host Bridge >=20 > - // >=20 > - for (Index =3D 0; Index < RootBridgeCount; Index++) { >=20 > + if (RootBridge->Io.Base <=3D RootBridge->Io.Limit) { >=20 > // >=20 > - // Create Root Bridge Handle Instance >=20 > + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. >=20 > + // For GCD resource manipulation, we need to use host address. >=20 > // >=20 > - RootBridge =3D CreateRootBridge (&RootBridges[Index]); >=20 > - ASSERT (RootBridge !=3D NULL); >=20 > - if (RootBridge =3D=3D NULL) { >=20 > - continue; >=20 > + HostAddress =3D TO_HOST_ADDRESS ( >=20 > + RootBridge->Io.Base, >=20 > + RootBridge->Io.Translation >=20 > + ); >=20 > + >=20 > + Status =3D AddIoSpace ( >=20 > + HostAddress, >=20 > + RootBridge->Io.Limit - RootBridge->Io.Base + 1 >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > } >=20 >=20 >=20 > - // >=20 > - // Make sure all root bridges share the same ResourceAssigned value. >=20 > - // >=20 > - if (Index =3D=3D 0) { >=20 > - ResourceAssigned =3D RootBridges[Index].ResourceAssigned; >=20 > - } else { >=20 > - ASSERT (ResourceAssigned =3D=3D RootBridges[Index].ResourceAssigne= d); >=20 > + if (RootBridge->ResourceAssigned) { >=20 > + Status =3D gDS->AllocateIoSpace ( >=20 > + EfiGcdAllocateAddress, >=20 > + EfiGcdIoTypeIo, >=20 > + 0, >=20 > + RootBridge->Io.Limit - RootBridge->Io.Base + 1, >=20 > + &HostAddress, >=20 > + gImageHandle, >=20 > + NULL >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > } >=20 > + } >=20 > + >=20 > + // >=20 > + // Add all the Mem/PMem aperture to GCD >=20 > + // Mem/PMem shouldn't overlap with each other >=20 > + // Root bridge which needs to combine MEM and PMEM should only report >=20 > + // the MEM aperture in Mem >=20 > + // >=20 > + MemApertures[0] =3D &RootBridge->Mem; >=20 > + MemApertures[1] =3D &RootBridge->MemAbove4G; >=20 > + MemApertures[2] =3D &RootBridge->PMem; >=20 > + MemApertures[3] =3D &RootBridge->PMemAbove4G; >=20 >=20 >=20 > - if (RootBridges[Index].Io.Base <=3D RootBridges[Index].Io.Limit) { >=20 > + for (MemApertureIndex =3D 0; MemApertureIndex < ARRAY_SIZE > (MemApertures); MemApertureIndex++) { >=20 > + if (MemApertures[MemApertureIndex]->Base <=3D > MemApertures[MemApertureIndex]->Limit) { >=20 > // >=20 > // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. >=20 > // For GCD resource manipulation, we need to use host address. >=20 > // >=20 > HostAddress =3D TO_HOST_ADDRESS ( >=20 > - RootBridges[Index].Io.Base, >=20 > - RootBridges[Index].Io.Translation >=20 > + MemApertures[MemApertureIndex]->Base, >=20 > + MemApertures[MemApertureIndex]->Translation >=20 > ); >=20 > - >=20 > - Status =3D AddIoSpace ( >=20 > + Status =3D AddMemoryMappedIoSpace ( >=20 > HostAddress, >=20 > - RootBridges[Index].Io.Limit - RootBridges[Index].Io.Bas= e + 1 >=20 > + MemApertures[MemApertureIndex]->Limit - > MemApertures[MemApertureIndex]->Base + 1, >=20 > + EFI_MEMORY_UC >=20 > ); >=20 > ASSERT_EFI_ERROR (Status); >=20 > - if (ResourceAssigned) { >=20 > - Status =3D gDS->AllocateIoSpace ( >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > + >=20 > + Status =3D gDS->SetMemorySpaceAttributes ( >=20 > + HostAddress, >=20 > + MemApertures[MemApertureIndex]->Limit - > MemApertures[MemApertureIndex]->Base + 1, >=20 > + EFI_MEMORY_UC >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_WARN, "PciHostBridge driver failed to set > EFI_MEMORY_UC to MMIO aperture - %r.\n", Status)); >=20 > + } >=20 > + >=20 > + if (RootBridge->ResourceAssigned) { >=20 > + Status =3D gDS->AllocateMemorySpace ( >=20 > EfiGcdAllocateAddress, >=20 > - EfiGcdIoTypeIo, >=20 > + EfiGcdMemoryTypeMemoryMappedIo, >=20 > 0, >=20 > - RootBridges[Index].Io.Limit - RootBridges[Index]= .Io.Base + 1, >=20 > + MemApertures[MemApertureIndex]->Limit - > MemApertures[MemApertureIndex]->Base + 1, >=20 > &HostAddress, >=20 > gImageHandle, >=20 > NULL >=20 > ); >=20 > ASSERT_EFI_ERROR (Status); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > } >=20 > } >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 >=20 >=20 > +/** >=20 > + PCI Root Bridge Memory free. >=20 > + >=20 > + @param RootBridge Root Bridge instance. >=20 > + >=20 > + @retval EFI_SUCCESS Memory was setup correctly >=20 > + @retval others Error in setup >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PciRootBridgeMemoryFree ( >=20 > + IN PCI_ROOT_BRIDGE *RootBridge >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINT64 HostAddress; >=20 > + PCI_ROOT_BRIDGE_APERTURE *MemApertures[4]; >=20 > + UINTN MemApertureIndex; >=20 > + >=20 > + if (RootBridge->Io.Base <=3D RootBridge->Io.Limit) { >=20 > // >=20 > - // Add all the Mem/PMem aperture to GCD >=20 > - // Mem/PMem shouldn't overlap with each other >=20 > - // Root bridge which needs to combine MEM and PMEM should only repor= t >=20 > - // the MEM aperture in Mem >=20 > + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. >=20 > + // For GCD resource manipulation, we need to use host address. >=20 > // >=20 > - MemApertures[0] =3D &RootBridges[Index].Mem; >=20 > - MemApertures[1] =3D &RootBridges[Index].MemAbove4G; >=20 > - MemApertures[2] =3D &RootBridges[Index].PMem; >=20 > - MemApertures[3] =3D &RootBridges[Index].PMemAbove4G; >=20 > - >=20 > - for (MemApertureIndex =3D 0; MemApertureIndex < ARRAY_SIZE > (MemApertures); MemApertureIndex++) { >=20 > - if (MemApertures[MemApertureIndex]->Base <=3D > MemApertures[MemApertureIndex]->Limit) { >=20 > - // >=20 > - // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address= . >=20 > - // For GCD resource manipulation, we need to use host address. >=20 > - // >=20 > - HostAddress =3D TO_HOST_ADDRESS ( >=20 > - MemApertures[MemApertureIndex]->Base, >=20 > - MemApertures[MemApertureIndex]->Translation >=20 > - ); >=20 > - Status =3D AddMemoryMappedIoSpace ( >=20 > - HostAddress, >=20 > - MemApertures[MemApertureIndex]->Limit - > MemApertures[MemApertureIndex]->Base + 1, >=20 > - EFI_MEMORY_UC >=20 > - ); >=20 > + HostAddress =3D TO_HOST_ADDRESS ( >=20 > + RootBridge->Io.Base, >=20 > + RootBridge->Io.Translation >=20 > + ); >=20 > + >=20 > + if (RootBridge->ResourceAssigned) { >=20 > + Status =3D gDS->FreeIoSpace (HostAddress, RootBridge->Io.Limit - R= ootBridge- > >Io.Base + 1); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Add all the Mem/PMem aperture to GCD >=20 > + // Mem/PMem shouldn't overlap with each other >=20 > + // Root bridge which needs to combine MEM and PMEM should only report >=20 > + // the MEM aperture in Mem >=20 > + // >=20 > + MemApertures[0] =3D &RootBridge->Mem; >=20 > + MemApertures[1] =3D &RootBridge->MemAbove4G; >=20 > + MemApertures[2] =3D &RootBridge->PMem; >=20 > + MemApertures[3] =3D &RootBridge->PMemAbove4G; >=20 > + >=20 > + for (MemApertureIndex =3D 0; MemApertureIndex < ARRAY_SIZE > (MemApertures); MemApertureIndex++) { >=20 > + if (MemApertures[MemApertureIndex]->Base <=3D > MemApertures[MemApertureIndex]->Limit) { >=20 > + // >=20 > + // Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address. >=20 > + // For GCD resource manipulation, we need to use host address. >=20 > + // >=20 > + HostAddress =3D TO_HOST_ADDRESS ( >=20 > + MemApertures[MemApertureIndex]->Base, >=20 > + MemApertures[MemApertureIndex]->Translation >=20 > + ); >=20 > + if (RootBridge->ResourceAssigned) { >=20 > + Status =3D gDS->FreeMemorySpace (HostAddress, RootBridge->Io.Lim= it - > RootBridge->Io.Base + 1); >=20 > ASSERT_EFI_ERROR (Status); >=20 > - Status =3D gDS->SetMemorySpaceAttributes ( >=20 > - HostAddress, >=20 > - MemApertures[MemApertureIndex]->Limit - > MemApertures[MemApertureIndex]->Base + 1, >=20 > - EFI_MEMORY_UC >=20 > - ); >=20 > if (EFI_ERROR (Status)) { >=20 > - DEBUG ((DEBUG_WARN, "PciHostBridge driver failed to set > EFI_MEMORY_UC to MMIO aperture - %r.\n", Status)); >=20 > - } >=20 > - >=20 > - if (ResourceAssigned) { >=20 > - Status =3D gDS->AllocateMemorySpace ( >=20 > - EfiGcdAllocateAddress, >=20 > - EfiGcdMemoryTypeMemoryMappedIo, >=20 > - 0, >=20 > - MemApertures[MemApertureIndex]->Limit - > MemApertures[MemApertureIndex]->Base + 1, >=20 > - &HostAddress, >=20 > - gImageHandle, >=20 > - NULL >=20 > - ); >=20 > - ASSERT_EFI_ERROR (Status); >=20 > + return Status; >=20 > } >=20 > } >=20 > } >=20 > + } >=20 >=20 >=20 > - // >=20 > - // Insert Root Bridge Handle Instance >=20 > - // >=20 > - InsertTailList (&HostBridge->RootBridges, &RootBridge->Link); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Test to see if this driver supports ControllerHandle. Any ControllerHa= ndle >=20 > + than contains a gEdkiiPciHostBridgeProtocolGuid protocol can be suppor= ted. >=20 > + >=20 > + @param This Protocol instance pointer. >=20 > + @param Controller Handle of device to test. >=20 > + @param RemainingDevicePath Optional parameter use to pick a specific = child >=20 > + device to start. >=20 > + >=20 > + @retval EFI_SUCCESS This driver supports this device. >=20 > + @retval EFI_ALREADY_STARTED This driver is already running on this dev= ice. >=20 > + @retval other This driver does not support this device. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PciHostBrigeDriverBindingSupported ( >=20 > + IN EFI_DRIVER_BINDING_PROTOCOL *This, >=20 > + IN EFI_HANDLE Controller, >=20 > + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + PCI_ROOT_BRIDGE *PciRootBridge; >=20 > + >=20 > + // >=20 > + // Check if Pci Host Bridge protocol is installed by platform >=20 > + // >=20 > + Status =3D gBS->OpenProtocol ( >=20 > + Controller, >=20 > + &gEdkiiPciHostBridgeProtocolGuid, >=20 > + (VOID **)&PciRootBridge, >=20 > + This->DriverBindingHandle, >=20 > + Controller, >=20 > + EFI_OPEN_PROTOCOL_BY_DRIVER >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > } >=20 >=20 >=20 > // >=20 > - // When resources were assigned, it's not needed to expose >=20 > - // PciHostBridgeResourceAllocation protocol. >=20 > + // Close the protocol used to perform the supported test >=20 > + // >=20 > + gBS->CloseProtocol ( >=20 > + Controller, >=20 > + &gEdkiiPciHostBridgeProtocolGuid, >=20 > + This->DriverBindingHandle, >=20 > + Controller >=20 > + ); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Start this driver on ControllerHandle and enumerate Pci bus and start >=20 > + all device under PCI bus. >=20 > + >=20 > + @param This Protocol instance pointer. >=20 > + @param Controller Handle of device to bind driver to. >=20 > + @param RemainingDevicePath Optional parameter use to pick a specific= child >=20 > + device to start. >=20 > + >=20 > + @retval EFI_SUCCESS This driver is added to ControllerHandle. >=20 > + @retval EFI_ALREADY_STARTED This driver is already running on > ControllerHandle. >=20 > + @retval other This driver does not support this device. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PciHostBrigeDriverBindingStart ( >=20 > + IN EFI_DRIVER_BINDING_PROTOCOL *This, >=20 > + IN EFI_HANDLE Controller, >=20 > + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + PCI_ROOT_BRIDGE *PciRootBridge; >=20 > + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; >=20 > + PCI_HOST_BRIDGE_INSTANCE *HostBridge; >=20 > + BOOLEAN MemorySetupDone; >=20 > + >=20 > + MemorySetupDone =3D FALSE; >=20 > + // >=20 > + // Check if Pci Host Bridge protocol is installed by platform >=20 > // >=20 > - if (!ResourceAssigned) { >=20 > + Status =3D gBS->OpenProtocol ( >=20 > + Controller, >=20 > + &gEdkiiPciHostBridgeProtocolGuid, >=20 > + (VOID **)&PciRootBridge, >=20 > + This->DriverBindingHandle, >=20 > + Controller, >=20 > + EFI_OPEN_PROTOCOL_BY_DRIVER >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > + >=20 > + RootBridge =3D CreateRootBridge (PciRootBridge); >=20 > + ASSERT (RootBridge !=3D NULL); >=20 > + if (RootBridge =3D=3D NULL) { >=20 > + Status =3D EFI_DEVICE_ERROR; >=20 > + goto ErrorExit; >=20 > + } >=20 > + >=20 > + Status =3D PciRootBridgeMemorySetup (PciRootBridge); >=20 > + if (EFI_ERROR (Status)) { >=20 > + goto ErrorExit; >=20 > + } >=20 > + >=20 > + MemorySetupDone =3D TRUE; >=20 > + >=20 > + if (!PciRootBridge->ResourceAssigned) { >=20 > + // Create host bridge >=20 > + HostBridge =3D AllocateZeroPool (sizeof (PCI_HOST_BRIDGE_INSTANCE)); >=20 > + ASSERT (HostBridge !=3D NULL); >=20 > + if (HostBridge =3D=3D NULL) { >=20 > + Status =3D EFI_OUT_OF_RESOURCES; >=20 > + goto ErrorExit; >=20 > + } >=20 > + >=20 > + HostBridge->Handle =3D 0; >=20 > + HostBridge->Signature =3D PCI_HOST_BRIDGE_SIGNATURE; >=20 > + HostBridge->CanRestarted =3D TRUE; >=20 > + InitializeListHead (&HostBridge->RootBridges); >=20 > + >=20 > HostBridge->ResAlloc.NotifyPhase =3D NotifyPhase; >=20 > HostBridge->ResAlloc.GetNextRootBridge =3D GetNextRootBridge; >=20 > HostBridge->ResAlloc.GetAllocAttributes =3D GetAttributes; >=20 > @@ -599,28 +752,266 @@ InitializePciHostBridge ( >=20 > NULL >=20 > ); >=20 > ASSERT_EFI_ERROR (Status); >=20 > - } >=20 > + if (EFI_ERROR (Status)) { >=20 > + goto ErrorExit; >=20 > + } >=20 >=20 >=20 > - for (Link =3D GetFirstNode (&HostBridge->RootBridges) >=20 > - ; !IsNull (&HostBridge->RootBridges, Link) >=20 > - ; Link =3D GetNextNode (&HostBridge->RootBridges, Link) >=20 > - ) >=20 > - { >=20 > - RootBridge =3D ROOT_BRIDGE_FROM_LINK (Lin= k); >=20 > + // >=20 > + // Insert Root Bridge Handle Instance >=20 > + // >=20 > + InsertTailList (&HostBridge->RootBridges, &RootBridge->Link); >=20 > RootBridge->RootBridgeIo.ParentHandle =3D HostBridge->Handle; >=20 > + } else { >=20 > + RootBridge->RootBridgeIo.ParentHandle =3D 0; >=20 > + } >=20 >=20 >=20 > - Status =3D gBS->InstallMultipleProtocolInterfaces ( >=20 > - &RootBridge->Handle, >=20 > - &gEfiDevicePathProtocolGuid, >=20 > - RootBridge->DevicePath, >=20 > - &gEfiPciRootBridgeIoProtocolGuid, >=20 > - &RootBridge->RootBridgeIo, >=20 > - NULL >=20 > - ); >=20 > - ASSERT_EFI_ERROR (Status); >=20 > + RootBridge->Handle =3D Controller; >=20 > + Status =3D gBS->InstallMultipleProtocolInterfaces ( >=20 > + &RootBridge->Handle, >=20 > + &gEfiPciRootBridgeIoProtocolGuid, >=20 > + &RootBridge->RootBridgeIo, >=20 > + NULL >=20 > + ); >=20 > + >=20 > +ErrorExit: >=20 > + if (EFI_ERROR (Status)) { >=20 > + if (MemorySetupDone) { >=20 > + PciRootBridgeMemoryFree (PciRootBridge); >=20 > + } >=20 > + >=20 > + if (RootBridge !=3D NULL) { >=20 > + if (!IsListEmpty (&RootBridge->Link)) { >=20 > + RemoveEntryList (&RootBridge->Link); >=20 > + } >=20 > + >=20 > + FreeRootBridge (RootBridge); >=20 > + } >=20 > + >=20 > + gBS->CloseProtocol ( >=20 > + Controller, >=20 > + &gEdkiiPciHostBridgeProtocolGuid, >=20 > + This->DriverBindingHandle, >=20 > + Controller >=20 > + ); >=20 > } >=20 >=20 >=20 > - PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount); >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + Stop this driver on ControllerHandle. Support stopping any child handl= es >=20 > + created by this driver. >=20 > + >=20 > + @param This Protocol instance pointer. >=20 > + @param Controller Handle of device to stop driver on. >=20 > + @param NumberOfChildren Number of Handles in ChildHandleBuffer. If > number of >=20 > + children is zero stop the entire bus driver. >=20 > + @param ChildHandleBuffer List of Child Handles to Stop. >=20 > + >=20 > + @retval EFI_SUCCESS This driver is removed ControllerHandle. >=20 > + @retval other This driver was not removed from this device= . >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PciHostBrigeDriverBindingStop ( >=20 > + IN EFI_DRIVER_BINDING_PROTOCOL *This, >=20 > + IN EFI_HANDLE Controller, >=20 > + IN UINTN NumberOfChildren, >=20 > + IN EFI_HANDLE *ChildHandleBuffer >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + PCI_ROOT_BRIDGE *PciRootBridge; >=20 > + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; >=20 > + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo; >=20 > + >=20 > + Status =3D gBS->HandleProtocol ( >=20 > + Controller, >=20 > + &gEfiPciRootBridgeIoProtocolGuid, >=20 > + (VOID **)&RootBridgeIo >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > + >=20 > + RootBridge =3D ROOT_BRIDGE_FROM_THIS (RootBridgeIo); >=20 > + >=20 > + Status =3D gBS->HandleProtocol ( >=20 > + Controller, >=20 > + &gEdkiiPciHostBridgeProtocolGuid, >=20 > + (VOID **)&PciRootBridge >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > + >=20 > + Status =3D gBS->UninstallMultipleProtocolInterfaces ( >=20 > + Controller, >=20 > + &gEfiPciRootBridgeIoProtocolGuid, >=20 > + (VOID **)&PciRootBridge >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > + >=20 > + if (!IsListEmpty (&RootBridge->Link)) { >=20 > + RemoveEntryList (&RootBridge->Link); >=20 > + } >=20 > + >=20 > + PciRootBridgeMemoryFree (PciRootBridge); >=20 > + >=20 > + FreeRootBridge (RootBridge); >=20 > + gBS->CloseProtocol ( >=20 > + Controller, >=20 > + &gEdkiiPciHostBridgeProtocolGuid, >=20 > + This->DriverBindingHandle, >=20 > + Controller >=20 > + ); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +// >=20 > +// PCI Bus Driver Global Variables >=20 > +// >=20 > +EFI_DRIVER_BINDING_PROTOCOL gPciHostBrigeDriverBinding =3D { >=20 > + PciHostBrigeDriverBindingSupported, >=20 > + PciHostBrigeDriverBindingStart, >=20 > + PciHostBrigeDriverBindingStop, >=20 > + 0xa, >=20 > + NULL, >=20 > + NULL >=20 > +}; >=20 > + >=20 > +/** >=20 > + >=20 > + Entry point of this driver. >=20 > + >=20 > + @param ImageHandle Image handle of this driver. >=20 > + @param SystemTable Pointer to standard EFI system table. >=20 > + >=20 > + @retval EFI_SUCCESS Succeed. >=20 > + @retval EFI_DEVICE_ERROR Fail to install PCI_ROOT_BRIDGE_IO protocol. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +InitializePciHostBridge ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN EFI_SYSTEM_TABLE *SystemTable >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + PCI_HOST_BRIDGE_INSTANCE *HostBridge; >=20 > + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; >=20 > + PCI_ROOT_BRIDGE *RootBridges; >=20 > + UINTN RootBridgeCount; >=20 > + UINTN Index; >=20 > + BOOLEAN ResourceAssigned; >=20 > + LIST_ENTRY *Link; >=20 > + >=20 > + Status =3D gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID > **)&mCpuIo); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + RootBridges =3D PciHostBridgeGetRootBridges (&RootBridgeCount); >=20 > + if ((RootBridges =3D=3D NULL) || (RootBridgeCount =3D=3D 0)) { >=20 > + // Register for binding protocol if library enumeration is not used >=20 > + Status =3D EfiLibInstallDriverBinding ( >=20 > + ImageHandle, >=20 > + SystemTable, >=20 > + &gPciHostBrigeDriverBinding, >=20 > + ImageHandle >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + } else { >=20 > + // >=20 > + // Most systems in the world including complex servers have only one= Host > Bridge. >=20 > + // >=20 > + HostBridge =3D AllocateZeroPool (sizeof (PCI_HOST_BRIDGE_INSTANCE)); >=20 > + ASSERT (HostBridge !=3D NULL); >=20 > + >=20 > + HostBridge->Signature =3D PCI_HOST_BRIDGE_SIGNATURE; >=20 > + HostBridge->CanRestarted =3D TRUE; >=20 > + InitializeListHead (&HostBridge->RootBridges); >=20 > + ResourceAssigned =3D FALSE; >=20 > + >=20 > + // >=20 > + // Create Root Bridge Device Handle in this Host Bridge >=20 > + // >=20 > + for (Index =3D 0; Index < RootBridgeCount; Index++) { >=20 > + // >=20 > + // Create Root Bridge Handle Instance >=20 > + // >=20 > + RootBridge =3D CreateRootBridge (&RootBridges[Index]); >=20 > + ASSERT (RootBridge !=3D NULL); >=20 > + if (RootBridge =3D=3D NULL) { >=20 > + continue; >=20 > + } >=20 > + >=20 > + // >=20 > + // Make sure all root bridges share the same ResourceAssigned valu= e. >=20 > + // >=20 > + if (Index =3D=3D 0) { >=20 > + ResourceAssigned =3D RootBridges[Index].ResourceAssigned; >=20 > + } else { >=20 > + ASSERT (ResourceAssigned =3D=3D RootBridges[Index].ResourceAssig= ned); >=20 > + } >=20 > + >=20 > + Status =3D PciRootBridgeMemorySetup (&RootBridges[Index]); >=20 > + if (EFI_ERROR (Status)) { >=20 > + continue; >=20 > + } >=20 > + >=20 > + // >=20 > + // Insert Root Bridge Handle Instance >=20 > + // >=20 > + InsertTailList (&HostBridge->RootBridges, &RootBridge->Link); >=20 > + } >=20 > + >=20 > + // >=20 > + // When resources were assigned, it's not needed to expose >=20 > + // PciHostBridgeResourceAllocation protocol. >=20 > + // >=20 > + if (!ResourceAssigned) { >=20 > + HostBridge->ResAlloc.NotifyPhase =3D NotifyPhase; >=20 > + HostBridge->ResAlloc.GetNextRootBridge =3D GetNextRootBridge; >=20 > + HostBridge->ResAlloc.GetAllocAttributes =3D GetAttributes; >=20 > + HostBridge->ResAlloc.StartBusEnumeration =3D StartBusEnumeration; >=20 > + HostBridge->ResAlloc.SetBusNumbers =3D SetBusNumbers; >=20 > + HostBridge->ResAlloc.SubmitResources =3D SubmitResources; >=20 > + HostBridge->ResAlloc.GetProposedResources =3D GetProposedResources= ; >=20 > + HostBridge->ResAlloc.PreprocessController =3D PreprocessController= ; >=20 > + >=20 > + Status =3D gBS->InstallMultipleProtocolInterfaces ( >=20 > + &HostBridge->Handle, >=20 > + &gEfiPciHostBridgeResourceAllocationProtocolGuid, >=20 > + &HostBridge->ResAlloc, >=20 > + NULL >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + } >=20 > + >=20 > + for (Link =3D GetFirstNode (&HostBridge->RootBridges) >=20 > + ; !IsNull (&HostBridge->RootBridges, Link) >=20 > + ; Link =3D GetNextNode (&HostBridge->RootBridges, Link) >=20 > + ) >=20 > + { >=20 > + RootBridge =3D ROOT_BRIDGE_FROM_LINK (L= ink); >=20 > + RootBridge->RootBridgeIo.ParentHandle =3D HostBridge->Handle; >=20 > + >=20 > + Status =3D gBS->InstallMultipleProtocolInterfaces ( >=20 > + &RootBridge->Handle, >=20 > + &gEfiDevicePathProtocolGuid, >=20 > + RootBridge->DevicePath, >=20 > + &gEfiPciRootBridgeIoProtocolGuid, >=20 > + &RootBridge->RootBridgeIo, >=20 > + NULL >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + } >=20 > + >=20 > + PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount); >=20 > + } >=20 >=20 >=20 > if (!EFI_ERROR (Status)) { >=20 > mIoMmuEvent =3D EfiCreateProtocolNotifyEvent ( >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf >=20 > index 9c24cacc30..ee4740b14f 100644 >=20 > --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf >=20 > +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf >=20 > @@ -46,6 +46,7 @@ >=20 > gEfiPciRootBridgeIoProtocolGuid ## BY_START >=20 > gEfiPciHostBridgeResourceAllocationProtocolGuid ## BY_START >=20 > gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES >=20 > + gEdkiiPciHostBridgeProtocolGuid ## SOMETIMES_CONSUMES >=20 >=20 >=20 > [Depex] >=20 > gEfiCpuIo2ProtocolGuid AND >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h > b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h >=20 > index 10a6200719..7923c4677b 100644 >=20 > --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h >=20 > +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h >=20 > @@ -93,6 +93,19 @@ CreateRootBridge ( >=20 > IN PCI_ROOT_BRIDGE *Bridge >=20 > ); >=20 >=20 >=20 > +/** >=20 > + Free the Pci Root Bridge instance. >=20 > + >=20 > + @param Bridge The root bridge instance. >=20 > + >=20 > + @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created >=20 > + or NULL if creation fails. >=20 > +**/ >=20 > +VOID >=20 > +FreeRootBridge ( >=20 > + IN PCI_ROOT_BRIDGE_INSTANCE *Bridge >=20 > + ); >=20 > + >=20 > // >=20 > // Protocol Member Function Prototypes >=20 > // >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c > b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c >=20 > index 157a0ada80..f0eb465a9d 100644 >=20 > --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c >=20 > +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c >=20 > @@ -286,6 +286,30 @@ CreateRootBridge ( >=20 > return RootBridge; >=20 > } >=20 >=20 >=20 > +/** >=20 > + Free the Pci Root Bridge instance. >=20 > + >=20 > + @param Bridge The root bridge instance. >=20 > + >=20 > + @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created >=20 > + or NULL if creation fails. >=20 > +**/ >=20 > +VOID >=20 > +FreeRootBridge ( >=20 > + IN PCI_ROOT_BRIDGE_INSTANCE *Bridge >=20 > + ) >=20 > +{ >=20 > + if (Bridge->ConfigBuffer !=3D NULL) { >=20 > + FreePool (Bridge->ConfigBuffer); >=20 > + } >=20 > + >=20 > + if (Bridge->DevicePath !=3D NULL) { >=20 > + FreePool (Bridge->DevicePath); >=20 > + } >=20 > + >=20 > + FreePool (Bridge); >=20 > +} >=20 > + >=20 > /** >=20 > Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridg= e IO. >=20 >=20 >=20 > diff --git a/MdeModulePkg/MdeModulePkg.dec > b/MdeModulePkg/MdeModulePkg.dec >=20 > index d65dae18aa..24700fa797 100644 >=20 > --- a/MdeModulePkg/MdeModulePkg.dec >=20 > +++ b/MdeModulePkg/MdeModulePkg.dec >=20 > @@ -692,6 +692,10 @@ >=20 > ## Include/Protocol/VariablePolicy.h >=20 > gEdkiiVariablePolicyProtocolGuid =3D { 0x81D1675C, 0x86F6, 0x48DF, { 0= xBD, > 0x95, 0x9A, 0x6E, 0x4F, 0x09, 0x25, 0xC3 } } >=20 >=20 >=20 > + ## Include/Library/PciHostBridgeLib.h >=20 > + # Exposes a PCI_HOST_BRIDGE structure for driver binding usage >=20 > + gEdkiiPciHostBridgeProtocolGuid =3D { 0xaff2b72d, 0x202e, 0x40e3, { 0x= 82, 0xd5, > 0x9f, 0x6f, 0x61, 0xaf, 0x2a, 0x0b } } >=20 > + >=20 > [PcdsFeatureFlag] >=20 > ## Indicates if the platform can support update capsule across a syste= m > reset.

>=20 > # TRUE - Supports update capsule across a system reset.
>=20 > -- >=20 > 2.25.1 >=20 >=20