From: "Ni, Ray" <ray.ni@intel.com>
To: "Liu, Zhiguang" <zhiguang.liu@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Dong, Eric" <eric.dong@intel.com>,
"Kumar, Rahul R" <rahul.r.kumar@intel.com>,
Gerd Hoffmann <kraxel@redhat.com>,
"De, Debkumar" <debkumar.de@intel.com>,
"West, Catharine" <catharine.west@intel.com>
Subject: Re: [PATCH v3 1/5] UefiCpuPkg/ResetVector: Rename macros about page table.
Date: Fri, 28 Apr 2023 09:03:16 +0000 [thread overview]
Message-ID: <MN6PR11MB8244396F8C65686BEF1752818C6B9@MN6PR11MB8244.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20230428064223.2048-1-zhiguang.liu@intel.com>
> -----Original Message-----
> From: Liu, Zhiguang <zhiguang.liu@intel.com>
> Sent: Friday, April 28, 2023 2:42 PM
> To: devel@edk2.groups.io
> Cc: Liu, Zhiguang <zhiguang.liu@intel.com>; Dong, Eric
> <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R
> <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>; De,
> Debkumar <debkumar.de@intel.com>; West, Catharine
> <catharine.west@intel.com>
> Subject: [PATCH v3 1/5] UefiCpuPkg/ResetVector: Rename macros about
> page table.
>
> This patch only renames macro, with no code logic impacted.
> Two purpose to rename macro:
> 1. Align some macro name in PageTables1G.asm and PageTables2M.asm, so
> that these two files can be easily combined later.
> 2. Some Macro names such as PDP are not accurate, since 4 level page
> entry also uses this macro. PG_NLE (no leaf entry) is better.
>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Debkumar De <debkumar.de@intel.com>
> Cc: Catharine West <catharine.west@intel.com>
> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
> ---
> .../ResetVector/Vtf0/X64/PageTables1G.asm | 24 ++++++++++----
> .../ResetVector/Vtf0/X64/PageTables2M.asm | 33 +++++++++++--------
> 2 files changed, 37 insertions(+), 20 deletions(-)
>
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
> b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
> index 19bd3d5a92..97e90777c8 100644
> --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
> +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
> @@ -2,7 +2,7 @@
> ; @file
> ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000
> (512GB)
> ;
> -; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.<BR>
> ; SPDX-License-Identifier: BSD-2-Clause-Patent
> ; Linear-Address Translation to a 1-GByte Page
> ;
> @@ -12,11 +12,18 @@ BITS 64
>
> %define ALIGN_TOP_TO_4K_FOR_PAGING
>
> -%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
> +;
> +; Page table no-leaf entry attribute
1. non-leaf entry attribute
> +;
> +%define PAGE_NLE_ATTR (PAGE_ACCESSED + \
> PAGE_READ_WRITE + \
> PAGE_PRESENT)
>
> -%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \
> +;
> +; Page table big leaf page attribute
2. Page table big leaf entry attribute
> +; Big leaf page contains PDPTE 1GB page and PDE 2MB page
3. PDPTE 1GB entry or PDE 2MB entry
> +;
> +%define PAGE_BLP_ATTR (PAGE_ACCESSED + \
4. PAGE_BLE_ATTR
> PAGE_READ_WRITE + \
> PAGE_DIRTY + \
> PAGE_PRESENT + \
> @@ -25,10 +32,13 @@ BITS 64
> %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
> %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
>
> -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
> - PAGE_PDP_ATTR)
> +;
> +; Page table no-leaf entry
> +;
> +%define PG_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
5. PAGE_NLE
Similar comments to the following changes.
> + PAGE_NLE_ATTR)
>
> -%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR)
> +%define PDP_1G(x) ((x << 30) + PAGE_BLP_ATTR)
>
> ALIGN 16
>
> @@ -37,7 +47,7 @@ TopLevelPageDirectory:
> ;
> ; Top level Page Directory Pointers (1 * 512GB entry)
> ;
> - DQ PDP(0x1000)
> + DQ PG_NLE(0x1000)
>
> TIMES 0x1000-PGTBLS_OFFSET($) DB 0
> ;
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
> b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
> index b97df384ac..e46694c799 100644
> --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
> +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
> @@ -2,7 +2,7 @@
> ; @file
> ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)
> ;
> -; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
> ; SPDX-License-Identifier: BSD-2-Clause-Patent
> ;
> ;------------------------------------------------------------------------------
> @@ -11,29 +11,36 @@ BITS 64
>
> %define ALIGN_TOP_TO_4K_FOR_PAGING
>
> -%define PAGE_2M_PDE_ATTR (PAGE_SIZE + \
> +;
> +; Page table big leaf page attribute
> +; Big leaf page contains PDPTE 1GB page and PDE 2MB page
> +;
> +%define PAGE_BLP_ATTR (PAGE_SIZE + \
> PAGE_ACCESSED + \
> PAGE_DIRTY + \
> PAGE_READ_WRITE + \
> PAGE_PRESENT)
>
> -%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
> - PAGE_READ_WRITE + \
> - PAGE_PRESENT)
> +;
> +; Page table no-leaf entry attribute
> +;
> +%define PAGE_NLE_ATTR (PAGE_ACCESSED + \
> + PAGE_READ_WRITE + \
> + PAGE_PRESENT)
>
> %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
> %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
>
> -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
> - PAGE_PDP_ATTR)
> -%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)
> +%define PG_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
> + PAGE_NLE_ATTR)
> +%define PTE_2MB(x) ((x << 21) + PAGE_BLP_ATTR)
>
> TopLevelPageDirectory:
>
> ;
> ; Top level Page Directory Pointers (1 * 512GB entry)
> ;
> - DQ PDP(0x1000)
> + DQ PG_NLE(0x1000)
>
>
> ;
> @@ -41,10 +48,10 @@ TopLevelPageDirectory:
> ;
> TIMES 0x1000-PGTBLS_OFFSET($) DB 0
>
> - DQ PDP(0x2000)
> - DQ PDP(0x3000)
> - DQ PDP(0x4000)
> - DQ PDP(0x5000)
> + DQ PG_NLE(0x2000)
> + DQ PG_NLE(0x3000)
> + DQ PG_NLE(0x4000)
> + DQ PG_NLE(0x5000)
>
> ;
> ; Page Table Entries (2048 * 2MB entries => 4GB)
> --
> 2.31.1.windows.1
next prev parent reply other threads:[~2023-04-28 9:03 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 6:42 [PATCH v3 1/5] UefiCpuPkg/ResetVector: Rename macros about page table Zhiguang Liu
2023-04-28 6:42 ` [PATCH v3 2/5] UefiCpuPkg/ResetVector: Simplify page table creation in ResetVector Zhiguang Liu
2023-04-28 9:05 ` Ni, Ray
2023-04-28 6:42 ` [PATCH v3 3/5] UefiCpuPkg/ResetVector: Combine PageTables1G.asm and PageTables2M.asm Zhiguang Liu
2023-04-28 9:09 ` Ni, Ray
2023-04-28 6:42 ` [PATCH v3 4/5] UefiCpuPkg/ResetVector: Modify Page Table in ResetVector Zhiguang Liu
2023-04-28 9:12 ` Ni, Ray
2023-05-01 7:47 ` [edk2-devel] " Ard Biesheuvel
2023-04-28 6:42 ` [PATCH v3 5/5] UefiCpuPkg/ResetVector: Support 5 level page table " Zhiguang Liu
2023-04-28 9:15 ` Ni, Ray
2023-04-28 9:03 ` Ni, Ray [this message]
[not found] ` <175A0DD0D612EB33.26969@groups.io>
2023-04-28 9:08 ` [edk2-devel] [PATCH v3 1/5] UefiCpuPkg/ResetVector: Rename macros about page table Ni, Ray
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