From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web10.96223.1679645295803029152 for ; Fri, 24 Mar 2023 01:08:15 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=f1Tb7K75; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: ray.ni@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679645295; x=1711181295; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=QAcWsdYP4BR2p/GKeRd/p7owuycbGzU+exskBiDi01o=; b=f1Tb7K75yGZEYByONKqdf37iZuDij8FQleC6BIKM+sTjAujHAVR1ec2p 8GYFqOJJZ1l1w/sHZTCEI1EcRQNLDs+nMS1TrHpk0Yti/GXA9xWW/EdXk xECxf36rYIVv83mGAfiMH3QDVBIIRy94iY/Mlt6kEuTQoAlJ6X/vNoCYc CCOhLkR9Om0Ed/r69G5Tn3E9B/rm9LqM6c5tiV89xOV7GZSkN3n/s5KOm 8ObgRbXzCtuxvf151WgtT6VpVrKLP234GYP7zoNpajEvb6FcCYxzIhKZi IDjcNbdYN3BVJ58E7t+Zusnij/9tKqZ5htoY3chiPQJ1+Pf8QAD8M7FpW Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="320114111" X-IronPort-AV: E=Sophos;i="5.98,287,1673942400"; d="scan'208";a="320114111" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2023 01:08:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10658"; a="928572246" X-IronPort-AV: E=Sophos;i="5.98,287,1673942400"; d="scan'208";a="928572246" Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by fmsmga006.fm.intel.com with ESMTP; 24 Mar 2023 01:08:15 -0700 Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 24 Mar 2023 01:08:14 -0700 Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21 via Frontend Transport; Fri, 24 Mar 2023 01:08:14 -0700 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (104.47.55.172) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.21; Fri, 24 Mar 2023 01:08:14 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GCBWGG0G0AZS4bPUMMH/5gmtho32cJhwxd//tIsjNIH5LS9rCD/n4x/fhX1wR1XEcR34ZsQDx0UaCpiJoW/Nc/T3UKBAOcFvpQfLtbpsdY+XdEllQRCdUM8Mcim0RhRG0JsjsL88aaa+8Bk6l69kQYXeewK7OrLqCr7NOMI9cFz+Ek26/qtauD7ZgtMnoAXSbwitpTFhNerKcWjFIwPTXTcZNr+rqOch1DQciVN6r5GtQfO9tCmyrIdN2/Azkf9wffdg7WfTAJeULNn7ARjrKiUDXTLSwJfAs4XTUG9BbPh/iKd4JesAimT+fyhb/mEP77n4ltgMEMLoay7MiahFBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qXoPUt5tPZidGadhb0sNBzlMoef8P+pfV3xkVC6QJ2w=; b=F0mX9sKLdHDzMK5KTkqqzl+hy/hucW5mRQ2sBoEXFS19xmY39ezRrkAvh1BADjH4R0cA9Y1wYojWRSNi0qDRTA8/erCc+a4TWyjvhQF3COP2GIc1tQFJs+y9bN/HrcurzDdI/umIdzOgRm3Z/uTpcWLdq2uZkX7wByAdbwxOu3ajNcHJA/HZ6SCI344vZhOo+L3dJ1CE8Bf0ReZdTxkX7BCiDBGZlNVYbtRttwW+Gxv/ZirenNBAsAUFzVqEkCEbe03y05241dUnLzjyeAx6HUFRLIFM3ouInDYlVYw9HVk5SdPue/FpI5F9/F4jQuf/aIT5fDagUrTgd+SEAsjFDw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from MN6PR11MB8244.namprd11.prod.outlook.com (2603:10b6:208:470::14) by PH8PR11MB6705.namprd11.prod.outlook.com (2603:10b6:510:1c4::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.37; Fri, 24 Mar 2023 08:08:11 +0000 Received: from MN6PR11MB8244.namprd11.prod.outlook.com ([fe80::ae07:e96a:4a24:8a69]) by MN6PR11MB8244.namprd11.prod.outlook.com ([fe80::ae07:e96a:4a24:8a69%7]) with mapi id 15.20.6178.037; Fri, 24 Mar 2023 08:08:11 +0000 From: "Ni, Ray" To: "Tan, Dun" , "devel@edk2.groups.io" CC: "Dong, Eric" , "Kumar, Rahul R" , Gerd Hoffmann Subject: Re: [Patch V5 14/22] UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter. Thread-Topic: [Patch V5 14/22] UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter. Thread-Index: AQHZXhYJebxeuRxGwkOdgJOBj2mW568Jk1zQ Date: Fri, 24 Mar 2023 08:08:11 +0000 Message-ID: References: <20230324060020.940-1-dun.tan@intel.com> <20230324060020.940-15-dun.tan@intel.com> In-Reply-To: <20230324060020.940-15-dun.tan@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MN6PR11MB8244:EE_|PH8PR11MB6705:EE_ x-ms-office365-filtering-correlation-id: 402eb024-8e18-4aff-3edb-08db2c3ee94c x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: wGBNy+cN+jc4bDyMWXuFxeIHvY+bsH7l/5unHjMd4wb3322UBbdy/sDrDeKmIJuZ5+ylcs03+mDeWrpXEguGk/VS5wcVnphHISZGyYxzZKTwLqwVDBl0x5OoNtLOA7MsOSR8IfHeOBtZSbFWFqFapfCBQGqMx1gSfRMgRsJjECemNuWiJ84r6PW7cluZJFbk1ECZK+yV/ucBcCzUlhzKn5qAs0vk2OYMaSjLXZCsRHMdiuPk+nZCRxC24/ak+J1LOFk+CmgV4QnB38Z67foZ6yiPR4jLlsBYkXNMw7wtZ1zVjAhmUZmSXVrECXsuAAUA8TbzgVSrGUCpTLchVLBTR00Pn8Hr8ZELStdzgV7j9SVsfAuo4/rK662vt2OS1z0IBhBx0k3VMPZHNe9j4t3wzRMuAu2vnKvdyibvixYVFXiZO+qwWKdstldWhiWH4WG/eOnN/WPqcpPGa4ykTO2zFziPpz5/fCLAJznMNH0IzpGHi7S0LJRurjXhCCLb88IeeeFPuFv8FaG5/H9elRvLFUtUQEovpml020bC/Ch4le/9vQOlS6JmLhKPN/+g551GNMQjjnhfqhZcTXVApWIBYg+sN6pFV/7fb75h/01OL6ZTC0zws+VsOkJGItIP/4dV8TRB+kgGWtJo1P0CIkfYbLBNFKsY1GLEJgZUhcso2EkUU+36D3+LgPxEuFt/Btr8QmaYxR+YPmiKk4tY5hMF5w== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN6PR11MB8244.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230025)(6029001)(346002)(396003)(366004)(136003)(39860400002)(376002)(451199018)(33656002)(186003)(26005)(6506007)(30864003)(53546011)(83380400001)(86362001)(38070700005)(2906002)(66946007)(66556008)(66446008)(71200400001)(19627235002)(76116006)(64756008)(54906003)(9686003)(8676002)(110136005)(66476007)(55016003)(4326008)(82960400001)(122000001)(478600001)(38100700002)(41300700001)(316002)(7696005)(52536014)(5660300002)(8936002)(559001)(579004);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?SPsKHdEI4vE2AU5zyE7p3SF7StCumYQ6GuLVO/Ik11RWQfwqVq6aALKWM3dH?= =?us-ascii?Q?CkoybKYg+74vBwv+Ny6SkUMCGvn/kkxOKHwaTeJX29T0oWqgcYvCoy61OyH3?= =?us-ascii?Q?uSTITNswpalB1j62CbRI4EnkneEwhN5KUj5HlEHT3zDE+DTMYxd3vZ0pMouQ?= =?us-ascii?Q?jVfUsg01XM7FeZ3s4th9jcJoaLK39DCUZfwo4F243gJy0hUZTGw8BWnIMiaO?= =?us-ascii?Q?U9GfOMiJz+GXCCBXvFz8MCgNmQ/E7d/YtkhKsB0JRWzi+uhCJvfhx2IIn/tg?= =?us-ascii?Q?6+RnOoZfnrR7yz5dgXiiJ+HvmzvdcHNrsvK3nMPgzZt98KUNbr80k5AP+xty?= =?us-ascii?Q?reKS6tNBvESrcMy/mYuodrzBabdsOKlMdsjQwpYp8bv2ijaAbZf24uXDNdla?= =?us-ascii?Q?A4o37fInnHUBxL1WGZFEwUXFZYh9tKJ9SiiNsAd00DHAHm5Nc/nRSPtbuvNK?= =?us-ascii?Q?9Oa+cTCckUziej82ikjbQbfYrhV5dyuedmT2wRkOcyLkZLFrlSf5Ptt8g2wK?= =?us-ascii?Q?Dd3wZnkaJGMJ6xloIxwPuINvIXlwS/ZFxWwrTNHuZiywrlazkpBr2aRC56PJ?= =?us-ascii?Q?h5y6vxEiODLJVTxFgTo4Dno/Eg/jT9c24H+XqWIOKXRKQENrklDrOz/nE7c/?= =?us-ascii?Q?903jk+I+7A0tTDcLJclz4fVR2KMsDpwpHJMihf6w/+msrI/F1N+AEUPrr1sP?= =?us-ascii?Q?sbI54Esafd10P5sQCjLEesOnTKfkEuib/OiMBfWZ+6rcleIL6NWW68r/FNEz?= =?us-ascii?Q?QMwSMLlqbiHJzTBg3c0cMWLfc7lvGPhiiWANrFS24jIbiGku5BKjHjwaAwyf?= =?us-ascii?Q?EZvs35zdRvthJUOkqHX4uAl2uLP991Xz004hc4NrOg7aa68RY4eSwET/HX8k?= =?us-ascii?Q?4VPlklBkkEV3Y5h+eYGDLl7UqLXoFrTBxULla0OpoYqV5HQ2DVpVS/tNWzJ9?= =?us-ascii?Q?HnCS7RNJeMnF6C6z9ccwdDIPHX9oKsHZCec9dmcB4RLod5hKbO7ZGQDPx6tb?= =?us-ascii?Q?vSm0cSzl3wuypwOeGNMqQ9ml0aOyhFFIE0NBJMC1sQtVFZwMaovQzP+mWFBO?= =?us-ascii?Q?6Lgm0oPIim1QSpItrb/CZtD+dqxXo/6cDSXXqGyz//Nb8ed1EAMgS5mR3+RJ?= =?us-ascii?Q?kmWxPSs8SsXuZxmOOc93SYiuyWQynNjo3OlYUIsBZ3s6BdNwjV9FRcpMmmXC?= =?us-ascii?Q?ZknSNiwtvuvhXUu4lxKOpnEMrBDlv3okAUeXTSrNXqMlc1/CJUmV+ueREeyt?= =?us-ascii?Q?eBoYGQyF6prvvHRI2dhO8Ql9Fv9/NBbdFx0SRCGAw5iLvI71PEglhg9PZFyR?= =?us-ascii?Q?q6dF8+h6d12AuMG1CT3Fs2VcA830DHm3s5H1N/ElIp5MVPtpreL0v5y+gjKK?= =?us-ascii?Q?PaZyWe5P+9N9RkdQeWMLCdsVqFQfUbUWkxIfosu579UDCD9ibIX7nDuQiEU9?= =?us-ascii?Q?kvRjTsNZ22S+xDAOCGkRdhR2qLChUe1hCO9/0j/nwnF00bnJxykrjjsP4tuH?= =?us-ascii?Q?+nYQAoDVFIovH+WeWYKBewnrJtKAe1crEquN8c6RmHl3SPwfQNRNZ4CaI0u8?= =?us-ascii?Q?8LMvIn58I5dRvIn9e18=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN6PR11MB8244.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 402eb024-8e18-4aff-3edb-08db2c3ee94c X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Mar 2023 08:08:11.6114 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: HqR4v/JvrpdhPB3vsBJ5zc/KbJkJYVj0Pj1F1AFRCtGOG8i4LpFfHgB7K4IJVmkmrOIATphoq4hS3PEgJUYEvw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR11MB6705 Return-Path: ray.ni@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Tan, Dun > Sent: Friday, March 24, 2023 2:00 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Kumar, > Rahul R ; Gerd Hoffmann > Subject: [Patch V5 14/22] UefiCpuPkg/CpuPageTableLib: Add OUTPUT > IsModified parameter. >=20 > Add OUTPUT IsModified parameter in PageTableMap() to indicate > if page table has been modified. With this parameter, caller > can know if need to call FlushTlb when the page table is in CR3. >=20 > Signed-off-by: Dun Tan > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Tested-by: Gerd Hoffmann > Acked-by: Gerd Hoffmann > --- > UefiCpuPkg/Include/Library/CpuPageTableLib.h = | 4 +++- > UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c = | 46 > +++++++++++++++++++++++++++++++++++++++++----- >=20 > UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo > st.c | 72 ++++++++++++++++++++++++++++++++++++-------------------------- > ---------- > UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c = | 6 > ++++-- > UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c = | 6 ++++- > - > 5 files changed, 88 insertions(+), 46 deletions(-) >=20 > diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h > b/UefiCpuPkg/Include/Library/CpuPageTableLib.h > index 4ef4a8b6af..352b6df6c6 100644 > --- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h > +++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h > @@ -74,6 +74,7 @@ typedef enum { > Page table entries that map the linear = address range are > reset to 0 before set to the new attribute > when a new physical base address is set= . > @param[in] Mask The mask used for attribute. The corres= ponding > field in Attribute is ignored if that in Mask is 0. > + @param[out] IsModified TRUE means page table is modified. FALS= E > means page table is not modified. >=20 > @retval RETURN_UNSUPPORTED PagingMode is not supported. > @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute > or Mask is NULL. > @@ -97,7 +98,8 @@ PageTableMap ( > IN UINT64 LinearAddress, > IN UINT64 Length, > IN IA32_MAP_ATTRIBUTE *Attribute, > - IN IA32_MAP_ATTRIBUTE *Mask > + IN IA32_MAP_ATTRIBUTE *Mask, > + OUT BOOLEAN *IsModified OPTIONAL > ); >=20 > typedef struct { > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > index c0b41472ce..885f1601fc 100644 > --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > @@ -274,6 +274,7 @@ IsAttributesAndMaskValidForNonPresentEntry ( > Page table entries that map the line= ar address range are > reset to 0 before set to the new attribute > when a new physical base address is = set. > @param[in] Mask The mask used for attribute. The cor= responding > field in Attribute is ignored if that in Mask is 0. > + @param[out] IsModified TRUE means page table is modified. F= ALSE > means page table is not modified. >=20 > @retval RETURN_INVALID_PARAMETER For non-present range, Mask- > >Bits.Present is 0 but some other attributes are provided. > @retval RETURN_INVALID_PARAMETER For non-present range, Mask- > >Bits.Present is 1, Attribute->Bits.Present is 1 but some other attribute= s are > not provided. > @@ -292,7 +293,8 @@ PageTableLibMapInLevel ( > IN UINT64 Length, > IN UINT64 Offset, > IN IA32_MAP_ATTRIBUTE *Attribute, > - IN IA32_MAP_ATTRIBUTE *Mask > + IN IA32_MAP_ATTRIBUTE *Mask, > + OUT BOOLEAN *IsModified > ) > { > RETURN_STATUS Status; > @@ -318,6 +320,8 @@ PageTableLibMapInLevel ( > IA32_MAP_ATTRIBUTE LocalParentAttribute; > UINT64 PhysicalAddrInEntry; > UINT64 PhysicalAddrInAttr; > + IA32_PAGING_ENTRY OriginalParentPagingEntry; > + IA32_PAGING_ENTRY OriginalCurrentPagingEntry; >=20 > ASSERT (Level !=3D 0); > ASSERT ((Attribute !=3D NULL) && (Mask !=3D NULL)); > @@ -333,6 +337,8 @@ PageTableLibMapInLevel ( > LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; > ParentAttribute =3D &LocalParentAttribute; >=20 > + OriginalParentPagingEntry.Uint64 =3D ParentPagingEntry->Uint64; > + > // > // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 <<= 21) or > 4K (1 << 12). > // > @@ -568,7 +574,15 @@ PageTableLibMapInLevel ( > ASSERT (CreateNew || (Mask->Bits.Nx =3D=3D 0) || (Attribute->B= its.Nx =3D=3D > 1)); > } >=20 > + // > + // Check if any leaf PagingEntry is modified. > + // > + OriginalCurrentPagingEntry.Uint64 =3D CurrentPagingEntry->Uint64= ; > PageTableLibSetPle (Level, CurrentPagingEntry, Offset, Attribute= , > &CurrentMask); > + > + if (OriginalCurrentPagingEntry.Uint64 !=3D CurrentPagingEntry->U= int64) { > + *IsModified =3D TRUE; > + } > } > } else { > // > @@ -591,7 +605,8 @@ PageTableLibMapInLevel ( > Length, > Offset, > Attribute, > - Mask > + Mask, > + IsModified > ); > if (RETURN_ERROR (Status)) { > return Status; > @@ -603,6 +618,14 @@ PageTableLibMapInLevel ( > Index++; > } >=20 > + // > + // Check if ParentPagingEntry entry is modified here is enough. Except= the > changes happen in leaf PagingEntry during > + // the while loop, if there is any other change happens in page table,= the > ParentPagingEntry must has been modified. > + // > + if (OriginalParentPagingEntry.Uint64 !=3D ParentPagingEntry->Uint64) { > + *IsModified =3D TRUE; > + } > + > return RETURN_SUCCESS; > } >=20 > @@ -623,6 +646,7 @@ PageTableLibMapInLevel ( > Page table entries that map the linear = address range are > reset to 0 before set to the new attribute > when a new physical base address is set= . > @param[in] Mask The mask used for attribute. The corres= ponding > field in Attribute is ignored if that in Mask is 0. > + @param[out] IsModified TRUE means page table is modified. FALS= E > means page table is not modified. >=20 > @retval RETURN_UNSUPPORTED PagingMode is not supported. > @retval RETURN_INVALID_PARAMETER PageTable, BufferSize, Attribute > or Mask is NULL. > @@ -646,7 +670,8 @@ PageTableMap ( > IN UINT64 LinearAddress, > IN UINT64 Length, > IN IA32_MAP_ATTRIBUTE *Attribute, > - IN IA32_MAP_ATTRIBUTE *Mask > + IN IA32_MAP_ATTRIBUTE *Mask, > + OUT BOOLEAN *IsModified OPTIONAL > ) > { > RETURN_STATUS Status; > @@ -656,6 +681,7 @@ PageTableMap ( > IA32_PAGE_LEVEL MaxLevel; > IA32_PAGE_LEVEL MaxLeafLevel; > IA32_MAP_ATTRIBUTE ParentAttribute; > + BOOLEAN LocalIsModified; >=20 > if (Length =3D=3D 0) { > return RETURN_SUCCESS; > @@ -718,6 +744,12 @@ PageTableMap ( > TopPagingEntry.Pce.Nx =3D 0; > } >=20 > + if (IsModified =3D=3D NULL) { > + IsModified =3D &LocalIsModified; > + } > + > + *IsModified =3D FALSE; > + > ParentAttribute.Uint64 =3D 0; > ParentAttribute.Bits.PageTableBaseAddress =3D 1; > ParentAttribute.Bits.Present =3D 1; > @@ -741,8 +773,10 @@ PageTableMap ( > Length, > 0, > Attribute, > - Mask > + Mask, > + IsModified > ); > + ASSERT (*IsModified =3D=3D FALSE); > if (RETURN_ERROR (Status)) { > return Status; > } > @@ -773,8 +807,10 @@ PageTableMap ( > Length, > 0, > Attribute, > - Mask > + Mask, > + IsModified > ); > + > if (!RETURN_ERROR (Status)) { > *PageTable =3D (UINTN)(TopPagingEntry.Uintn & > IA32_PE_BASE_ADDRESS_MASK_40); > } > diff --git > a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > Host.c > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > Host.c > index c682d4ea04..759da09271 100644 > --- > a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > Host.c > +++ > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > Host.c > @@ -51,26 +51,26 @@ TestCaseForParameter ( > // > // If the input linear address is not 4K align, it should return inval= id > parameter > // > - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), > RETURN_INVALID_PARAMETER); > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask, NULL), > RETURN_INVALID_PARAMETER); >=20 > // > // If the input PageTableBufferSize is not 4K align, it should return = invalid > parameter > // > PageTableBufferSize =3D 10; > - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > &PageTableBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask), > RETURN_INVALID_PARAMETER); > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > &PageTableBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask, NULL), > RETURN_INVALID_PARAMETER); >=20 > // > // If the input PagingMode is Paging32bit, it should return invalid pa= rameter > // > PageTableBufferSize =3D 0; > PagingMode =3D Paging32bit; > - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), > RETURN_UNSUPPORTED); > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask, NULL), > RETURN_UNSUPPORTED); >=20 > // > // If the input MapMask is NULL, it should return invalid parameter > // > PagingMode =3D Paging5Level1GB; > - UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, NULL), > RETURN_INVALID_PARAMETER); > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, NULL, NULL), > RETURN_INVALID_PARAMETER); >=20 > return UNIT_TEST_PASSED; > } > @@ -119,10 +119,10 @@ TestCaseWhichNoNeedExtraSize ( > // > // Create page table to cover [0, 10M], it should have 5 PTE > // > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > TestStatus =3D IsPageTableValid (PageTable, PagingMode); > if (TestStatus !=3D UNIT_TEST_PASSED) { > @@ -134,7 +134,7 @@ TestCaseWhichNoNeedExtraSize ( > // We assume the fucntion doesn't need to change page table, return > success and output BufferSize is 0 > // > Buffer =3D NULL; > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask, > NULL); > UT_ASSERT_EQUAL (PageTableBufferSize, 0); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > TestStatus =3D IsPageTableValid (PageTable, PagingMode); > @@ -148,7 +148,7 @@ TestCaseWhichNoNeedExtraSize ( > // > MapMask.Bits.Nx =3D 0; > PageTableBufferSize =3D 0; > - Status =3D PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask, > NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > UT_ASSERT_EQUAL (PageTableBufferSize, 0); > TestStatus =3D IsPageTableValid (PageTable, PagingMode); > @@ -164,7 +164,7 @@ TestCaseWhichNoNeedExtraSize ( > MapAttribute.Bits.Accessed =3D 1; > MapMask.Bits.Accessed =3D 1; > PageTableBufferSize =3D 0; > - Status =3D PageTableMap (&PageTable, PagingMode, N= ULL, > &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, > &MapAttribute, &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, N= ULL, > &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, > &MapAttribute, &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > UT_ASSERT_EQUAL (PageTableBufferSize, 0); > TestStatus =3D IsPageTableValid (PageTable, PagingMode); > @@ -217,10 +217,10 @@ TestCase1Gmapto4K ( > MapAttribute.Bits.Present =3D 1; > MapMask.Bits.Present =3D 1; > MapMask.Uint64 =3D MAX_UINT64; > - Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); >=20 > // > @@ -281,11 +281,11 @@ TestCaseManualChangeReadWrite ( > // > // Create Page table to cover [0,2G], with ReadWrite =3D 1 > // > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > BackupPageTableBufferSize =3D PageTableBufferSize; > Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES > (PageTableBufferSize)); > - Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Bu= ffer, > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > IsPageTableValid (PageTable, PagingMode); >=20 > @@ -331,7 +331,7 @@ TestCaseManualChangeReadWrite ( > // Call library to change ReadWrite to 0 for [0,2M] > // > MapAttribute.Bits.ReadWrite =3D 0; > - Status =3D PageTableMap (&PageTable, PagingMode, = NULL, > &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, = NULL, > &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > IsPageTableValid (PageTable, PagingMode); > MapCount =3D 0; > @@ -360,7 +360,7 @@ TestCaseManualChangeReadWrite ( > // > MapAttribute.Bits.ReadWrite =3D 1; > PageTableBufferSize =3D 0; > - Status =3D PageTableMap (&PageTable, PagingMode, = NULL, > &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, = NULL, > &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > IsPageTableValid (PageTable, PagingMode); > MapCount =3D 0; > @@ -434,10 +434,10 @@ TestCaseManualSizeNotMatch ( > // > // Create Page table to cover [2M-4K, 4M], with ReadWrite =3D 1 > // > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, > &MapAttribute, &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, > &MapAttribute, &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, > &MapAttribute, &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, > &MapAttribute, &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > IsPageTableValid (PageTable, PagingMode); >=20 > @@ -493,7 +493,7 @@ TestCaseManualSizeNotMatch ( > MapAttribute.Bits.ReadWrite =3D 1; > PageTableBufferSize =3D 0; > MapAttribute.Bits.PageTableBaseAddress =3D (SIZE_2MB - SIZE_4KB) >> 12= ; > - Status =3D PageTableMap (&PageTable, P= agingMode, Buffer, > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, P= agingMode, Buffer, > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > return UNIT_TEST_PASSED; > } > @@ -540,10 +540,10 @@ TestCaseManualNotMergeEntry ( > // > // Create Page table to cover [0,4M], and [4M, 1G] is not present > // > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > TestStatus =3D IsPageTableValid (PageTable, PagingMode); > if (TestStatus !=3D UNIT_TEST_PASSED) { > @@ -555,7 +555,7 @@ TestCaseManualNotMergeEntry ( > // It looks like the chioce is not bad, but sometime, we need to keep = some > small entry > // > PageTableBufferSize =3D 0; > - Status =3D PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > TestStatus =3D IsPageTableValid (PageTable, PagingMode); > if (TestStatus !=3D UNIT_TEST_PASSED) { > @@ -564,7 +564,7 @@ TestCaseManualNotMergeEntry ( >=20 > MapAttribute.Bits.Accessed =3D 1; > PageTableBufferSize =3D 0; > - Status =3D PageTableMap (&PageTable, PagingMode, N= ULL, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, N= ULL, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, > &MapMask, NULL); > // > // If it didn't use a big 1G entry to cover whole range, only change [= 0,2M] > for some attribute won't need extra memory > // > @@ -619,10 +619,10 @@ TestCaseManualChangeNx ( > // > // Create Page table to cover [0,2G], with Nx =3D 0 > // > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > TestStatus =3D IsPageTableValid (PageTable, PagingMode); > if (TestStatus !=3D UNIT_TEST_PASSED) { > @@ -666,7 +666,7 @@ TestCaseManualChangeNx ( > // > // Call library to change Nx to 0 for [0,1G] > // > - Status =3D PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > TestStatus =3D IsPageTableValid (PageTable, PagingMode); > if (TestStatus !=3D UNIT_TEST_PASSED) { > @@ -741,30 +741,30 @@ TestCaseToCheckMapMaskAndAttr ( > // > // Create Page table to cover [0, 2G]. All fields of MapMask should be= set. > // > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); > MapMask.Uint64 =3D MAX_UINT64; > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); >=20 > // > // Update Page table to set [2G - 8K, 2G] from present to non-present.= All > fields of MapMask except present should not be set. > // > PageTableBufferSize =3D 0; > - MapAttribute.Uint64 =3D SIZE_2GB - SIZE_8KB; > + MapAttribute.Uint64 =3D 0; > MapMask.Uint64 =3D 0; > MapMask.Bits.Present =3D 1; > MapMask.Bits.ReadWrite =3D 1; > - Status =3D PageTableMap (&PageTable, PagingMode, Buffe= r, > &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffe= r, > &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); > MapMask.Bits.ReadWrite =3D 0; > - Status =3D PageTableMap (&PageTable, PagingMode, Buffe= r, > &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffe= r, > &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > Buffer =3D AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); >=20 > // > @@ -774,11 +774,11 @@ TestCaseToCheckMapMaskAndAttr ( > MapAttribute.Uint64 =3D 0; > MapMask.Uint64 =3D 0; > MapMask.Bits.Present =3D 1; > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > MapAttribute.Bits.ReadWrite =3D 1; > MapMask.Bits.ReadWrite =3D 1; > - Status =3D PageTableMap (&PageTable, PagingMode, = Buffer, > &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, = Buffer, > &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); >=20 > // > @@ -791,10 +791,10 @@ TestCaseToCheckMapMaskAndAttr ( > MapMask.Uint64 =3D 0; > MapMask.Bits.ReadWrite =3D 1; > MapMask.Bits.Present =3D 1; > - Status =3D PageTableMap (&PageTable, PagingMode, = Buffer, > &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, = Buffer, > &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_INVALID_PARAMETER); > MapMask.Uint64 =3D MAX_UINT64; > - Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, > &MapMask); > + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, SIZE_2GB - SIZE_8KB, SIZE_8KB, &MapAttribute, > &MapMask, NULL); > UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); >=20 > MapCount =3D 0; > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c > index 121cc4f2b2..e603dba269 100644 > --- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c > +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c > @@ -699,7 +699,8 @@ SingleMapEntryTest ( > LastMapEntry->LinearAddress, > LastMapEntry->Length, > &LastMapEntry->Attribute, > - &LastMapEntry->Mask > + &LastMapEntry->Mask, > + NULL > ); >=20 > Attribute =3D &LastMapEntry->Attribute; > @@ -759,7 +760,8 @@ SingleMapEntryTest ( > LastMapEntry->LinearAddress, > LastMapEntry->Length, > &LastMapEntry->Attribute, > - &LastMapEntry->Mask > + &LastMapEntry->Mask, > + NULL > ); > } >=20 > diff --git a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c > b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c > index f20068152b..da8729e752 100644 > --- a/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c > +++ b/UefiCpuPkg/Library/MpInitLib/X64/CreatePageTable.c > @@ -57,7 +57,8 @@ CreatePageTable ( > Address, > Length, > &MapAttribute, > - &MapMask > + &MapMask, > + NULL > ); > ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); > DEBUG ((DEBUG_INFO, "AP Page Table Buffer Size =3D %x\n", > PageTableBufferSize)); > @@ -72,7 +73,8 @@ CreatePageTable ( > Address, > Length, > &MapAttribute, > - &MapMask > + &MapMask, > + NULL > ); > ASSERT_EFI_ERROR (Status); > return PageTable; > -- > 2.31.1.windows.1