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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 8idPNz3UvnjoOxxuyYOO1koix7686176AA= Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN6PR11MB824443A178E8EE9C2EFC364E8CDCAMN6PR11MB8244namp_" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=OJKM2a2L; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") --_000_MN6PR11MB824443A178E8EE9C2EFC364E8CDCAMN6PR11MB8244namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I am not sure which driver is responsible for producing the ACPI tables. + Foster Thanks, Ray ________________________________ From: Yoshinoya Sent: Friday, October 27, 2023 9:29 AM To: devel@edk2.groups.io Cc: jonathan.cameron@huawei.com ; Laszlo Ersek= ; kraxel@redhat.com ; Ni, Ray ; Sayanta Pattanayak Subject: Re:Re: [edk2-devel] question about cxl device enumeration in pci b= us driver Hi, Thanks for reply! I download code from this git https://github.com/SayantaP-arm/edk2-platform= s/ For this ARM edk2 sample package, it provided cxldxe driver which being exe= cuted after UEFI DXE PciBus enumeration finishes. This ppt (https://lpc.events/event/16/contributions/1254/) describes good. Intel also provied a CXL Type 3 memory device software guide. This guide also describes system firmware boot sequence and uefi boot seque= nce. But i could not match these describes with standard UEFI BIOS Boot flow, su= ch as dxe phase's standard pci enumeration driver. It sees needing add some cxl discovery code into dxe pci bus driver. Thanks At 2023-10-26 21:35:38, "Jonathan Cameron via groups.io" wrote: >On Thu, 26 Oct 2023 11:49:28 +0200 >"Laszlo Ersek" wrote: > >> On 10/26/23 10:33, Gerd Hoffmann wrote: >> > On Thu, Oct 26, 2023 at 10:36:35AM +0800, Yoshinoya wrote: >> > >> >> CXL Host Bridge / Root Port / Switch / Device enumeration / HDM Confi= g, maybe could be integrated into pci drivers stack. >> > >> > Point being? Can or should the firmware do anything useful with >> > the CXL hardware? If so, what exactly and why? >> > >> > Current state of affairs is that the PCI stack does the usual PCI >> > initialization (enumerate, assign resources to PCI bars) and leaves >> > everything else to the OS. >> >> (I don't know what "HDM Config" stands for.) >> >> The only utility for driving CXL devices from the firmware could be, AFA= ICT: >> >> - booting off of such a device (or at least "supporting OS boot" in some >> manner) >> >> - using such a device for UEFI console purposes > >There are different models for how to use CXL devices and what's possible = depends on the >version of CXL. CXL 1.1 wasn't great for standards defined discovery, so >EDK2 platform logic basically has to do everything. > >The one mostly expected for early CXL servers, for backwards compatibility= , makes >setting up the CXL memory decoders (Host managed Device Memory - HDM) in a= ll the >components in the path to memory + locking them down an EDK2 problem. The= y are then >presented in the memory map and in SRAT, HMAT etc the same as normal DDR m= emory. >Idea being that an old OS will be fine with that and doesn't have to be CX= L aware >at all. Note this also involves walking the CDAT tables via DOE mailboxes= in PCI >config space to get the magic numbers needed to compute HMAT. > >The other model is to do very little in EDK2 and make entirely a problem f= or the OS. >The logic is necessary anyway if you want to support hotplug etc, so use i= t for the >cold plug paths 2. That's all we've currently supported on QEMU. > >There was a presentation at Linux Plumbers last year on some out of tree s= upport >from ARM for doing the setup on a CXL 2.0 platform (I think) in EDK2 >https://lpc.events/event/16/contributions/1254/ >But I guess it never went upstream. >https://github.com/SayantaP-arm/edk2-platforms/tree/cxl-type-3 > >+CC Sayanta > >Jonathan >> >> Laszlo >> >> >> >> >> >> > > > > > -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110191): https://edk2.groups.io/g/devel/message/110191 Mute This Topic: https://groups.io/mt/102173204/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/19134562= 12/xyzzy [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_MN6PR11MB824443A178E8EE9C2EFC364E8CDCAMN6PR11MB8244namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
I am not sure which driver is responsible for producing the ACPI tables.

+ Foster


Thanks,
Ray
From: Yoshinoya <yoshino= yatoko@163.com>
Sent: Friday, October 27, 2023 9:29 AM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: jonathan.cameron@huawei.com <jonathan.cameron@huawei.com>;= Laszlo Ersek <lersek@redhat.com>; kraxel@redhat.com <kraxel@redha= t.com>; Ni, Ray <ray.ni@intel.com>; Sayanta Pattanayak <sayanta= .pattanayak@arm.com>
Subject: Re:Re: [edk2-devel] question about cxl device enumeration i= n pci bus driver
 


Hi,
Thanks for reply!


For this ARM edk2 sample package, it provided cxldx= e driver which being executed after UEFI DXE PciBus enumeration finishes.

Intel also provie= d a CXL Type 3 memory device software guide.
This guide also d= escribes system firmware boot sequence and uefi boot sequence.
But i could not m= atch these describes with standard UEFI BIOS Boot flow, such as dxe phase's= standard pci enumeration driver.
It sees needing a= dd some cxl discovery code into dxe pci bus driver.

Thanks 






At 2023-10-26 21:35:38, "Jonathan Cameron via groups.io"=
 <jonathan.cameron=3Dhuawei.com@groups.io> wrote:
>On Thu, 26 Oct 2023 11:49:28 +0200
>"Laszlo Ersek" <lersek@redhat.com> wrote:
>
>> On 10/26/23 10:33, Gerd Hoffmann wrote:
>> > On Thu, Oct 26, 2023 at 10:36:35AM +0800, Yoshinoya wrote:
>> >  =20
>> >> CXL Host Bridge / Root Port / Switch / Device enumeration=
 / HDM Config, maybe could be integrated into pci drivers stack. =20
>> >=20
>> > Point being?  Can or should the firmware do anything useful w=
ith
>> > the CXL hardware?  If so, what exactly and why?
>> >=20
>> > Current state of affairs is that the PCI stack does the usual=
 PCI
>> > initialization (enumerate, assign resources to PCI bars) and =
leaves
>> > everything else to the OS. =20
>>=20
>> (I don't know what "HDM Config" stands for.)
>>=20
>> The only utility for driving CXL devices from the firmware could b=
e, AFAICT:
>>=20
>> - booting off of such a device (or at least "supporting OS bo=
ot" in some
>> manner)
>>=20
>> - using such a device for UEFI console purposes
>
>There are different models for how to use CXL devices and what's possib=
le depends on the
>version of CXL.  CXL 1.1 wasn't great for standards defined discovery, =
so
>EDK2 platform logic basically has to do everything.
>
>The one mostly expected for early CXL servers, for backwards compatibil=
ity, makes
>setting up the CXL memory decoders (Host managed Device Memory - HDM) i=
n all the
>components in the path to memory + locking them down an EDK2 problem.  =
They are then
>presented in the memory map and in SRAT, HMAT etc the same as normal DD=
R memory.
>Idea being that an old OS will be fine with that and doesn't have to be=
 CXL aware
>at all.  Note this also involves walking the CDAT tables via DOE mailbo=
xes in PCI
>config space to get the magic numbers needed to compute HMAT.
>
>The other model is to do very little in EDK2 and make entirely a proble=
m for the OS.
>The logic is necessary anyway if you want to support hotplug etc, so us=
e it for the
>cold plug paths 2.  That's all we've currently supported on QEMU.
>
>There was a presentation at Linux Plumbers last year on some out of tre=
e support
>from ARM for doing the setup on a CXL 2.0 platform (I think) in EDK2=20
>https://lpc.events/event/16/contributions/1254/
>But I guess it never went upstream.
>https://github.com/SayantaP-arm/edk2-platforms/tree/cxl-type-3
>
>+CC Sayanta
>
>Jonathan
>>=20
>> Laszlo
>>=20
>>=20
>>=20
>>=20
>>=20
>>=20
>
>
>
>
>
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