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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Dun, Can you split this patch to 2 patches? One to move some local variable initialization to the beginning of the func= tion. The other to fix the bug. So the bug fix changes look smaller. Thanks, Ray > -----Original Message----- > From: Tan, Dun > Sent: Wednesday, March 8, 2023 6:08 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Kumar, > Rahul R ; Gerd Hoffmann > Subject: [Patch V2 03/14] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 > mapping issue >=20 > In previous code logic, when splitting a leaf parent entry to > smaller granularity child page table, if the parent entry > Attribute&Mask(without PageTableBaseAddress field) is equal to the > input attribute&mask(without PageTableBaseAddress field), the split > process won't happen. This may lead to failure in non-1:1 mapping. >=20 > For example, there is a page table in which [0, 1G] is mapped(Lv4[0] > ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we > want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the > same attibute. The expected behaviour should be: split Lv3[0,0] > entry into 512 level2 entries and remap the first level2 entry to > cover [0, 2M]. But the split won't happen in previous code since > PageTableBaseAddress of input Attribute is not checked. >=20 > So, when checking if a leaf parent entry needs to be splitted, we > should also check if PageTableBaseAddress calculated by parent entry > is equal to the value caculated by input attribute. >=20 > Signed-off-by: Dun Tan > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Cc: Gerd Hoffmann > --- > UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 27 > +++++++++++++++++---------- > 1 file changed, 17 insertions(+), 10 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > index 4c9d70fa0a..ee27238edb 100644 > --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > @@ -258,6 +258,7 @@ PageTableLibMapInLevel ( > UINTN BitStart; > UINTN Index; > IA32_PAGING_ENTRY *PagingEntry; > + UINTN PagingEntryIndex; > IA32_PAGING_ENTRY *CurrentPagingEntry; > UINT64 RegionLength; > UINT64 SubLength; > @@ -288,6 +289,13 @@ PageTableLibMapInLevel ( > LocalParentAttribute.Uint64 =3D ParentAttribute->Uint64; > ParentAttribute =3D &LocalParentAttribute; >=20 > + // > + // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 <<= 21) > or 4K (1 << 12). > + // > + BitStart =3D 12 + (Level - 1) * 9; > + PagingEntryIndex =3D (UINTN)BitFieldRead64 (LinearAddress + Offset, > BitStart, BitStart + 9 - 1); > + RegionLength =3D REGION_LENGTH (Level); > + > // > // ParentPagingEntry ONLY is deferenced for checking Present and > MustBeOne bits > // when Modify is FALSE. > @@ -325,8 +333,11 @@ PageTableLibMapInLevel ( > // the actual attributes of grand-parents when determing the memory > type. > // > PleBAttribute.Uint64 =3D PageTableLibGetPleBMapAttribute > (&ParentPagingEntry->PleB, ParentAttribute); > - if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & > IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)) > - =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & > IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))) > + if ((((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & > IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)) > + =3D=3D (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & > IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))) && > + ( (Mask->Bits.PageTableBaseAddress =3D=3D 0) > + || ((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS > (&PleBAttribute) + PagingEntryIndex * RegionLength) > + =3D=3D (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribut= e) > + Offset)))) > { > // > // This function is called when the memory length is less than the= region > length of the parent level. > @@ -353,8 +364,7 @@ PageTableLibMapInLevel ( > // > PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, > &AllOneMask); >=20 > - RegionLength =3D REGION_LENGTH (Level); > - PagingEntry =3D (IA32_PAGING_ENTRY > *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry- > >Pnle); > + PagingEntry =3D (IA32_PAGING_ENTRY > *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry- > >Pnle); > for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { > PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffse= t; > SubOffset +=3D RegionLength; > @@ -425,14 +435,11 @@ PageTableLibMapInLevel ( > } >=20 > // > - // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 <<= 21) or > 4K (1 << 12). > // RegionStart: points to the linear address that's aligned on Region= Length > and lower than (LinearAddress + Offset). > // > - BitStart =3D 12 + (Level - 1) * 9; > - Index =3D (UINTN)BitFieldRead64 (LinearAddress + Offset, BitSta= rt, > BitStart + 9 - 1); > - RegionLength =3D LShiftU64 (1, BitStart); > - RegionMask =3D RegionLength - 1; > - RegionStart =3D (LinearAddress + Offset) & ~RegionMask; > + Index =3D PagingEntryIndex; > + RegionMask =3D RegionLength - 1; > + RegionStart =3D (LinearAddress + Offset) & ~RegionMask; >=20 > ParentAttribute->Uint64 =3D PageTableLibGetPnleMapAttribute > (&ParentPagingEntry->Pnle, ParentAttribute); >=20 > -- > 2.31.1.windows.1