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--_000_MN6PR11MB824462B720D17E1F0C1584218CEE2MN6PR11MB8244namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni Thanks, Ray ________________________________ From: Tan, Dun Sent: Friday, May 17, 2024 17:44 To: devel@edk2.groups.io Cc: Ni, Ray ; Kumar, Rahul R ; G= erd Hoffmann ; Wu, Jiaxin ; Zhou, J= ianfeng Subject: [PATCH] UefiCpuPkg:fix issue when splitting paging entry This patch is to fix issue when splitting leaf paging entry in CpuPageTableLib code. In previous code, before we assign the new child paging structure address to the content of splitted paging entry, PageTableLibSetPnle() is called to make sure the bit7 is set to 0, which indicate the previous leaf entry is changed to non-leaf entry now. There is a gap between we change the bit7 and we assign the new child paging structure address to the content of the splitted paging entry. If the address of code execution or data access happens to be in the range covered by the splitted paging entry, this gap may cause issue. In this patch, we prepare the new paging entry content value in a local variable and assign the value to the splitted paging entry at once. The volatile keyword is used to ensure that no optimization will occur in compilation. Signed-off-by: Dun Tan Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Jiaxin Wu Cc: Zhou Jianfeng --- UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c index b10a3008e4..bdc411338f 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -342,6 +342,7 @@ PageTableLibMapInLevel ( UINT64 PhysicalAddrInAttr; IA32_PAGING_ENTRY OriginalParentPagingEntry; IA32_PAGING_ENTRY OriginalCurrentPagingEntry; + IA32_PAGING_ENTRY TempPagingEntry; ASSERT (Level !=3D 0); ASSERT ((Attribute !=3D NULL) && (Mask !=3D NULL)); @@ -359,6 +360,8 @@ PageTableLibMapInLevel ( OriginalParentPagingEntry.Uint64 =3D ParentPagingEntry->Uint64; OneOfPagingEntry.Uint64 =3D 0; + TempPagingEntry.Uint64 =3D 0; + // // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 2= 1) or 4K (1 << 12). // @@ -441,8 +444,10 @@ PageTableLibMapInLevel ( // Non-leaf entry doesn't have PAT bit. So use ~IA32_PE_BASE_ADDRESS= _MASK_40 is to make sure PAT bit // (bit12) in original big-leaf entry is not assigned to PageTableBa= seAddress field of non-leaf entry. // - PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOn= eMask); - ParentPagingEntry->Uint64 =3D ((UINTN)(VOID *)PagingEntry) | (Parent= PagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40)); + TempPagingEntry.Uint64 =3D ParentPagingEntry->Uint64; + PageTableLibSetPnle (&TempPagingEntry.Pnle, &NopAttribute, &AllOneMa= sk); + TempPagingEntry.Uint64 =3D ((UINTN)(VOID *= )PagingEntry) | (TempPagingEntry.Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40)); + *(volatile UINT64 *)&(ParentPagingEntry->Uint64) =3D TempPagingEntry= .Uint64; } } else { // -- 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Reviewed-by: Ray Ni <ray.ni@intel.com>

Thanks,
Ray
From: Tan, Dun <dun.tan@= intel.com>
Sent: Friday, May 17, 2024 17:44
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R <rahul.r.kum= ar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>; Wu, Jiaxin <j= iaxin.wu@intel.com>; Zhou, Jianfeng <jianfeng.zhou@intel.com>
Subject: [PATCH] UefiCpuPkg:fix issue when splitting paging entry
 
This patch is to fix issue when splitting leaf pag= ing
entry in CpuPageTableLib code.

In previous code, before we assign the new child paging
structure address to the content of splitted paging entry,
PageTableLibSetPnle() is called to make sure the bit7 is
set to 0, which indicate the previous leaf entry is
changed to non-leaf entry now. There is a gap between
we change the bit7 and we assign the new child paging
structure address to the content of the splitted paging
entry. If the address of code execution or data access
happens to be in the range covered by the splitted paging
entry, this gap may cause issue.

In this patch, we prepare the new paging entry content
value in a local variable and assign the value to the
splitted paging entry at once. The volatile keyword
is used to ensure that no optimization will occur in
compilation.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Zhou Jianfeng <jianfeng.zhou@intel.com>
---
 UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 9 +++++++--  1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpu= Pkg/Library/CpuPageTableLib/CpuPageTableMap.c
index b10a3008e4..bdc411338f 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -342,6 +342,7 @@ PageTableLibMapInLevel (
   UINT64         &n= bsp;    PhysicalAddrInAttr;
   IA32_PAGING_ENTRY   OriginalParentPagingEntry;
   IA32_PAGING_ENTRY   OriginalCurrentPagingEntry;
+  IA32_PAGING_ENTRY   TempPagingEntry;
 
   ASSERT (Level !=3D 0);
   ASSERT ((Attribute !=3D NULL) && (Mask !=3D NULL)); @@ -359,6 +360,8 @@ PageTableLibMapInLevel (
 
   OriginalParentPagingEntry.Uint64 =3D ParentPagingEntry->Uin= t64;
   OneOfPagingEntry.Uint64      &nb= sp;   =3D 0;
+  TempPagingEntry.Uint64       &nb= sp;   =3D 0;
+
   //
   // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G= (1 << 30), 2M (1 << 21) or 4K (1 << 12).
   //
@@ -441,8 +444,10 @@ PageTableLibMapInLevel (
       // Non-leaf entry doesn't have PAT bit= . So use ~IA32_PE_BASE_ADDRESS_MASK_40 is to make sure PAT bit
       // (bit12) in original big-leaf entry = is not assigned to PageTableBaseAddress field of non-leaf entry.
       //
-      PageTableLibSetPnle (&ParentPagingEntry= ->Pnle, &NopAttribute, &AllOneMask);
-      ParentPagingEntry->Uint64 =3D ((UINTN)(V= OID *)PagingEntry) | (ParentPagingEntry->Uint64 & (~IA32_PE_BASE_ADD= RESS_MASK_40));
+      TempPagingEntry.Uint64 =3D ParentPagingEntr= y->Uint64;
+      PageTableLibSetPnle (&TempPagingEntry.P= nle, &NopAttribute, &AllOneMask);
+      TempPagingEntry.Uint64   &nb= sp;            =            =3D ((UINTN)(V= OID *)PagingEntry) | (TempPagingEntry.Uint64 & (~IA32_PE_BASE_ADDRESS_M= ASK_40));
+      *(volatile UINT64 *)&(ParentPagingEntry= ->Uint64) =3D TempPagingEntry.Uint64;
     }
   } else {
     //
--
2.31.1.windows.1

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