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contact devel+owner@edk2.groups.io Resent-Date: Thu, 18 Apr 2024 00:33:23 -0700 Resent-From: ray.ni@intel.com Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: utlAr6KDIPDHS6uG5ckUf0aIx7686176AA= Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN6PR11MB824463EC0258869D6EADDEAF8C0E2MN6PR11MB8244namp_" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=lh3BiMZs; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io --_000_MN6PR11MB824463EC0258869D6EADDEAF8C0E2MN6PR11MB8244namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni Thanks, Ray ________________________________ From: Wu, Jiaxin Sent: Thursday, April 18, 2024 14:55 To: devel@edk2.groups.io Cc: Ni, Ray ; Zeng, Star ; Gerd Hoff= mann ; Kumar, Rahul R Subject: [PATCH v3 03/13] UefiCpuPkg/SmmRelocationLib: Rename global variab= les This patch aims to rename global variables for clearer association with Smm Init, ensuring their names are distinct from those used in the PiSmmCpuDxeSmm Driver. Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- .../Library/SmmRelocationLib/Ia32/SmmInit.nasm | 18 +++++++-------- .../SmmRelocationLib/InternalSmmRelocationLib.h | 8 +++---- .../Library/SmmRelocationLib/SmmRelocationLib.c | 26 +++++++++++-------= ---- .../Library/SmmRelocationLib/X64/SmmInit.nasm | 18 +++++++-------- 4 files changed, 35 insertions(+), 35 deletions(-) diff --git a/UefiCpuPkg/Library/SmmRelocationLib/Ia32/SmmInit.nasm b/UefiCp= uPkg/Library/SmmRelocationLib/Ia32/SmmInit.nasm index 3d845e9e16..8916cb7d06 100644 --- a/UefiCpuPkg/Library/SmmRelocationLib/Ia32/SmmInit.nasm +++ b/UefiCpuPkg/Library/SmmRelocationLib/Ia32/SmmInit.nasm @@ -16,15 +16,15 @@ extern ASM_PFX(SmmInitHandler) extern ASM_PFX(mRebasedFlag) extern ASM_PFX(mSmmRelocationOriginalAddress) -global ASM_PFX(gPatchSmmCr3) -global ASM_PFX(gPatchSmmCr4) -global ASM_PFX(gPatchSmmCr0) +global ASM_PFX(gPatchSmmInitCr3) +global ASM_PFX(gPatchSmmInitCr4) +global ASM_PFX(gPatchSmmInitCr0) global ASM_PFX(gPatchSmmInitStack) -global ASM_PFX(gcSmiInitGdtr) +global ASM_PFX(gcSmmInitGdtr) global ASM_PFX(gcSmmInitSize) global ASM_PFX(gcSmmInitTemplate) %define PROTECT_MODE_CS 0x8 %define PROTECT_MODE_DS 0x20 @@ -81,11 +81,11 @@ CodeSeg64: DB 0x9b DB 0xaf ; LimitHigh DB 0 ; BaseHigh GDT_SIZE equ $ - NullSeg -ASM_PFX(gcSmiInitGdtr): +ASM_PFX(gcSmmInitGdtr): DW GDT_SIZE - 1 DD NullSeg SECTION .text @@ -98,22 +98,22 @@ ASM_PFX(SmmStartup): cpuid mov ebx, edx ; rdmsr will change edx. keep it i= n ebx. and ebx, BIT20 ; extract NX capability bit shr ebx, 9 ; shift bit to IA32_EFER.NXE[BIT11= ] position mov eax, strict dword 0 ; source operand will be patched -ASM_PFX(gPatchSmmCr3): +ASM_PFX(gPatchSmmInitCr3): mov cr3, eax -o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))] +o32 lgdt [cs:ebp + (ASM_PFX(gcSmmInitGdtr) - ASM_PFX(SmmStartup))] mov eax, strict dword 0 ; source operand will be patched -ASM_PFX(gPatchSmmCr4): +ASM_PFX(gPatchSmmInitCr4): mov cr4, eax mov ecx, 0xc0000080 ; IA32_EFER MSR rdmsr or eax, ebx ; set NXE bit if NX is available wrmsr mov eax, strict dword 0 ; source operand will be patched -ASM_PFX(gPatchSmmCr0): +ASM_PFX(gPatchSmmInitCr0): mov di, PROTECT_MODE_DS mov cr0, eax jmp PROTECT_MODE_CS : dword @32bit BITS 32 diff --git a/UefiCpuPkg/Library/SmmRelocationLib/InternalSmmRelocationLib.h= b/UefiCpuPkg/Library/SmmRelocationLib/InternalSmmRelocationLib.h index a9d3f271a9..ede61b956f 100644 --- a/UefiCpuPkg/Library/SmmRelocationLib/InternalSmmRelocationLib.h +++ b/UefiCpuPkg/Library/SmmRelocationLib/InternalSmmRelocationLib.h @@ -30,17 +30,17 @@ #include #include #include #include -extern IA32_DESCRIPTOR gcSmiInitGdtr; +extern IA32_DESCRIPTOR gcSmmInitGdtr; extern CONST UINT16 gcSmmInitSize; extern CONST UINT8 gcSmmInitTemplate[]; -X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0; -X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3; -X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4; +X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitCr0; +X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitCr3; +X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitCr4; X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitStack; // // The size 0x20 must be bigger than // the size of template code of SmmInit. Currently, diff --git a/UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.c b/UefiC= puPkg/Library/SmmRelocationLib/SmmRelocationLib.c index 13e62b662d..ca98f06a05 100644 --- a/UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.c +++ b/UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.c @@ -22,11 +22,11 @@ UINTN mNumberOfCpus =3D 1; EFI_PROCESSOR_INFORMATION *mProcessorInfo =3D NULL; // // IDT used during SMM Init // -IA32_DESCRIPTOR gcSmiIdtr; +IA32_DESCRIPTOR gcSmmInitIdtr; // // Smbase for all CPUs // UINT64 *mSmBase =3D NULL; @@ -118,11 +118,11 @@ SmmInitHandler ( UINTN Index; // // Update SMM IDT entries' code segment and load IDT // - AsmWriteIdtr (&gcSmiIdtr); + AsmWriteIdtr (&gcSmmInitIdtr); ApicId =3D GetApicId (); for (Index =3D 0; Index < mNumberOfCpus; Index++) { if (ApicId =3D=3D (UINT32)mProcessorInfo[Index].ProcessorId) { // @@ -167,13 +167,13 @@ SmmRelocateBases ( ASSERT (sizeof (BakBuf) >=3D gcSmmInitSize); // // Patch ASM code template with current CR0, CR3, and CR4 values // - PatchInstructionX86 (gPatchSmmCr0, AsmReadCr0 (), 4); - PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4); - PatchInstructionX86 (gPatchSmmCr4, AsmReadCr4 () & (~CR4_CET_ENABLE), 4)= ; + PatchInstructionX86 (gPatchSmmInitCr0, AsmReadCr0 (), 4); + PatchInstructionX86 (gPatchSmmInitCr3, AsmReadCr3 (), 4); + PatchInstructionX86 (gPatchSmmInitCr4, AsmReadCr4 () & (~CR4_CET_ENABLE)= , 4); U8Ptr =3D (UINT8 *)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET= ); CpuStatePtr =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMR= AM_SAVE_STATE_MAP_OFFSET); // @@ -249,19 +249,19 @@ InitSmmIdt ( // // There are 32 (not 255) entries in it since only processor // generated exceptions will be handled. // - gcSmiIdtr.Limit =3D (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32) - 1; + gcSmmInitIdtr.Limit =3D (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32) - 1; // // Allocate for IDT. // sizeof (UINTN) is for the PEI Services Table pointer. // - gcSmiIdtr.Base =3D (UINTN)AllocateZeroPool (gcSmiIdtr.Limit + 1 + sizeof= (UINTN)); - ASSERT (gcSmiIdtr.Base !=3D 0); - gcSmiIdtr.Base +=3D sizeof (UINTN); + gcSmmInitIdtr.Base =3D (UINTN)AllocateZeroPool (gcSmmInitIdtr.Limit + 1 = + sizeof (UINTN)); + ASSERT (gcSmmInitIdtr.Base !=3D 0); + gcSmmInitIdtr.Base +=3D sizeof (UINTN); // // Disable Interrupt, save InterruptState and save PEI IDT table // InterruptState =3D SaveAndDisableInterrupts (); @@ -270,21 +270,21 @@ InitSmmIdt ( // // Save the PEI Services Table pointer // The PEI Services Table pointer will be stored in the sizeof (UINTN) b= ytes // immediately preceding the IDT in memory. // - PeiServices =3D (CONST EFI_PEI_SERVICE= S **)(*(UINTN *)(PeiIdtr.Base - sizeof (UINTN))); - (*(UINTN *)(gcSmiIdtr.Base - sizeof (UINTN))) =3D (UINTN)PeiServices; + PeiServices =3D (CONST EFI_PEI_SER= VICES **)(*(UINTN *)(PeiIdtr.Base - sizeof (UINTN))); + (*(UINTN *)(gcSmmInitIdtr.Base - sizeof (UINTN))) =3D (UINTN)PeiServices= ; // // Load SMM temporary IDT table // - AsmWriteIdtr (&gcSmiIdtr); + AsmWriteIdtr (&gcSmmInitIdtr); // // Setup SMM default exception handlers, SMM IDT table - // will be updated and saved in gcSmiIdtr + // will be updated and saved in gcSmmInitIdtr // Status =3D InitializeCpuExceptionHandlers (NULL); ASSERT_EFI_ERROR (Status); // diff --git a/UefiCpuPkg/Library/SmmRelocationLib/X64/SmmInit.nasm b/UefiCpu= Pkg/Library/SmmRelocationLib/X64/SmmInit.nasm index c790ad7ad8..8288b723c4 100644 --- a/UefiCpuPkg/Library/SmmRelocationLib/X64/SmmInit.nasm +++ b/UefiCpuPkg/Library/SmmRelocationLib/X64/SmmInit.nasm @@ -16,15 +16,15 @@ extern ASM_PFX(SmmInitHandler) extern ASM_PFX(mRebasedFlag) extern ASM_PFX(mSmmRelocationOriginalAddress) -global ASM_PFX(gPatchSmmCr3) -global ASM_PFX(gPatchSmmCr4) -global ASM_PFX(gPatchSmmCr0) +global ASM_PFX(gPatchSmmInitCr3) +global ASM_PFX(gPatchSmmInitCr4) +global ASM_PFX(gPatchSmmInitCr0) global ASM_PFX(gPatchSmmInitStack) -global ASM_PFX(gcSmiInitGdtr) +global ASM_PFX(gcSmmInitGdtr) global ASM_PFX(gcSmmInitSize) global ASM_PFX(gcSmmInitTemplate) global ASM_PFX(gPatchRebasedFlagAddr32) global ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32) @@ -82,11 +82,11 @@ CodeSeg64: DB 0x9b DB 0xaf ; LimitHigh DB 0 ; BaseHigh GDT_SIZE equ $ - NullSeg -ASM_PFX(gcSmiInitGdtr): +ASM_PFX(gcSmmInitGdtr): DW GDT_SIZE - 1 DQ NullSeg DEFAULT REL @@ -98,15 +98,15 @@ BITS 16 ASM_PFX(SmmStartup): mov eax, 0x80000001 ; read capability cpuid mov ebx, edx ; rdmsr will change edx. keep it i= n ebx. mov eax, strict dword 0 ; source operand will be patched -ASM_PFX(gPatchSmmCr3): +ASM_PFX(gPatchSmmInitCr3): mov cr3, eax -o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))] +o32 lgdt [cs:ebp + (ASM_PFX(gcSmmInitGdtr) - ASM_PFX(SmmStartup))] mov eax, strict dword 0 ; source operand will be patched -ASM_PFX(gPatchSmmCr4): +ASM_PFX(gPatchSmmInitCr4): or ah, 2 ; enable XMM registers access mov cr4, eax mov ecx, 0xc0000080 ; IA32_EFER MSR rdmsr or ah, BIT0 ; set LME bit @@ -114,11 +114,11 @@ ASM_PFX(gPatchSmmCr4): jz .1 or ah, BIT3 ; set NXE bit .1: wrmsr mov eax, strict dword 0 ; source operand will be patched -ASM_PFX(gPatchSmmCr0): +ASM_PFX(gPatchSmmInitCr0): mov cr0, eax ; enable protected mode & paging jmp LONG_MODE_CS : dword 0 ; offset will be patched to @LongM= ode @PatchLongModeOffset: BITS 64 -- 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Reviewed-by: Ray Ni <ray.ni@intel.com>

Thanks,
Ray
From: Wu, Jiaxin <jiaxin= .wu@intel.com>
Sent: Thursday, April 18, 2024 14:55
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Ni, Ray <ray.ni@intel.com>; Zeng, Star <star.zeng@intel= .com>; Gerd Hoffmann <kraxel@redhat.com>; Kumar, Rahul R <rahul= .r.kumar@intel.com>
Subject: [PATCH v3 03/13] UefiCpuPkg/SmmRelocationLib: Rename global= variables
 
This patch aims to rename global variables for cle= arer
association with Smm Init, ensuring their names are
distinct from those used in the PiSmmCpuDxeSmm Driver.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Zeng Star <star.zeng@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
---
 .../Library/SmmRelocationLib/Ia32/SmmInit.nasm    = ; | 18 +++++++--------
 .../SmmRelocationLib/InternalSmmRelocationLib.h    |&n= bsp; 8 +++----
 .../Library/SmmRelocationLib/SmmRelocationLib.c    | 2= 6 +++++++++++-----------
 .../Library/SmmRelocationLib/X64/SmmInit.nasm    =   | 18 +++++++--------
 4 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/UefiCpuPkg/Library/SmmRelocationLib/Ia32/SmmInit.nasm b/UefiCp= uPkg/Library/SmmRelocationLib/Ia32/SmmInit.nasm
index 3d845e9e16..8916cb7d06 100644
--- a/UefiCpuPkg/Library/SmmRelocationLib/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/Library/SmmRelocationLib/Ia32/SmmInit.nasm
@@ -16,15 +16,15 @@
 
 extern ASM_PFX(SmmInitHandler)
 extern ASM_PFX(mRebasedFlag)
 extern ASM_PFX(mSmmRelocationOriginalAddress)
 
-global ASM_PFX(gPatchSmmCr3)
-global ASM_PFX(gPatchSmmCr4)
-global ASM_PFX(gPatchSmmCr0)
+global ASM_PFX(gPatchSmmInitCr3)
+global ASM_PFX(gPatchSmmInitCr4)
+global ASM_PFX(gPatchSmmInitCr0)
 global ASM_PFX(gPatchSmmInitStack)
-global ASM_PFX(gcSmiInitGdtr)
+global ASM_PFX(gcSmmInitGdtr)
 global ASM_PFX(gcSmmInitSize)
 global ASM_PFX(gcSmmInitTemplate)
 
 %define PROTECT_MODE_CS 0x8
 %define PROTECT_MODE_DS 0x20
@@ -81,11 +81,11 @@ CodeSeg64:
             DB=       0x9b
             DB=       0xaf      &nbs= p;         ; LimitHigh
             DB=       0       &= nbsp;           ; BaseHig= h
 GDT_SIZE equ $ - NullSeg
 
-ASM_PFX(gcSmiInitGdtr):
+ASM_PFX(gcSmmInitGdtr):
     DW      GDT_SIZE - 1
     DD      NullSeg
 
 
     SECTION .text
@@ -98,22 +98,22 @@ ASM_PFX(SmmStartup):
     cpuid
     mov     ebx, edx  &n= bsp;            = ;     ; rdmsr will change edx. keep it in ebx.
     and     ebx, BIT20  =             &nb= sp;   ; extract NX capability bit
     shr     ebx, 9  &nbs= p;            &= nbsp;      ; shift bit to IA32_EFER.NXE[BIT11] pos= ition
     mov     eax, strict dword 0&nb= sp;        ; source operand will be patc= hed
-ASM_PFX(gPatchSmmCr3):
+ASM_PFX(gPatchSmmInitCr3):
     mov     cr3, eax
-o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(Smm= Startup))]
+o32 lgdt    [cs:ebp + (ASM_PFX(gcSmmInitGdtr) - ASM_PFX(Smm= Startup))]
     mov     eax, strict dword 0&nb= sp;        ; source operand will be patc= hed
-ASM_PFX(gPatchSmmCr4):
+ASM_PFX(gPatchSmmInitCr4):
     mov     cr4, eax
     mov     ecx, 0xc0000080 &= nbsp;           ; IA32_EF= ER MSR
     rdmsr
     or      eax, ebx &nb= sp;            =       ; set NXE bit if NX is available
     wrmsr
     mov     eax, strict dword 0&nb= sp;        ; source operand will be patc= hed
-ASM_PFX(gPatchSmmCr0):
+ASM_PFX(gPatchSmmInitCr0):
     mov     di, PROTECT_MODE_DS      mov     cr0, eax
     jmp     PROTECT_MODE_CS : dwor= d @32bit
 
 BITS 32
diff --git a/UefiCpuPkg/Library/SmmRelocationLib/InternalSmmRelocationLib.h= b/UefiCpuPkg/Library/SmmRelocationLib/InternalSmmRelocationLib.h
index a9d3f271a9..ede61b956f 100644
--- a/UefiCpuPkg/Library/SmmRelocationLib/InternalSmmRelocationLib.h
+++ b/UefiCpuPkg/Library/SmmRelocationLib/InternalSmmRelocationLib.h
@@ -30,17 +30,17 @@
 #include <Guid/SmmBaseHob.h>
 #include <Register/Intel/Cpuid.h>
 #include <Register/Intel/SmramSaveStateMap.h>
 #include <Protocol/MmCpu.h>
 
-extern IA32_DESCRIPTOR  gcSmiInitGdtr;
+extern IA32_DESCRIPTOR  gcSmmInitGdtr;
 extern CONST UINT16     gcSmmInitSize;
 extern CONST UINT8      gcSmmInitTemplate[];=
 
-X86_ASSEMBLY_PATCH_LABEL  gPatchSmmCr0;
-X86_ASSEMBLY_PATCH_LABEL  gPatchSmmCr3;
-X86_ASSEMBLY_PATCH_LABEL  gPatchSmmCr4;
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmmInitCr0;
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmmInitCr3;
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmmInitCr4;
 X86_ASSEMBLY_PATCH_LABEL  gPatchSmmInitStack;
 
 //
 // The size 0x20 must be bigger than
 // the size of template code of SmmInit. Currently,
diff --git a/UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.c b/UefiC= puPkg/Library/SmmRelocationLib/SmmRelocationLib.c
index 13e62b662d..ca98f06a05 100644
--- a/UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.c
+++ b/UefiCpuPkg/Library/SmmRelocationLib/SmmRelocationLib.c
@@ -22,11 +22,11 @@ UINTN  mNumberOfCpus    =3D 1;
 EFI_PROCESSOR_INFORMATION  *mProcessorInfo =3D NULL;
 
 //
 // IDT used during SMM Init
 //
-IA32_DESCRIPTOR  gcSmiIdtr;
+IA32_DESCRIPTOR  gcSmmInitIdtr;
 
 //
 // Smbase for all CPUs
 //
 UINT64  *mSmBase =3D NULL;
@@ -118,11 +118,11 @@ SmmInitHandler (
   UINTN   Index;
 
   //
   // Update SMM IDT entries' code segment and load IDT
   //
-  AsmWriteIdtr (&gcSmiIdtr);
+  AsmWriteIdtr (&gcSmmInitIdtr);
   ApicId =3D GetApicId ();
 
   for (Index =3D 0; Index < mNumberOfCpus; Index++) {
     if (ApicId =3D=3D (UINT32)mProcessorInfo[Index].Pr= ocessorId) {
       //
@@ -167,13 +167,13 @@ SmmRelocateBases (
   ASSERT (sizeof (BakBuf) >=3D gcSmmInitSize);
 
   //
   // Patch ASM code template with current CR0, CR3, and CR4 valu= es
   //
-  PatchInstructionX86 (gPatchSmmCr0, AsmReadCr0 (), 4);
-  PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);
-  PatchInstructionX86 (gPatchSmmCr4, AsmReadCr4 () & (~CR4_CET_EN= ABLE), 4);
+  PatchInstructionX86 (gPatchSmmInitCr0, AsmReadCr0 (), 4);
+  PatchInstructionX86 (gPatchSmmInitCr3, AsmReadCr3 (), 4);
+  PatchInstructionX86 (gPatchSmmInitCr4, AsmReadCr4 () & (~CR4_CE= T_ENABLE), 4);
 
   U8Ptr       =3D (UINT8 *)(UINTN)= (SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);
   CpuStatePtr =3D (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SM= BASE + SMRAM_SAVE_STATE_MAP_OFFSET);
 
   //
@@ -249,19 +249,19 @@ InitSmmIdt (
 
   //
   // There are 32 (not 255) entries in it since only processor    // generated exceptions will be handled.
   //
-  gcSmiIdtr.Limit =3D (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32) - 1; +  gcSmmInitIdtr.Limit =3D (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32) - = 1;
 
   //
   // Allocate for IDT.
   // sizeof (UINTN) is for the PEI Services Table pointer.
   //
-  gcSmiIdtr.Base =3D (UINTN)AllocateZeroPool (gcSmiIdtr.Limit + 1 + s= izeof (UINTN));
-  ASSERT (gcSmiIdtr.Base !=3D 0);
-  gcSmiIdtr.Base +=3D sizeof (UINTN);
+  gcSmmInitIdtr.Base =3D (UINTN)AllocateZeroPool (gcSmmInitIdtr.Limit= + 1 + sizeof (UINTN));
+  ASSERT (gcSmmInitIdtr.Base !=3D 0);
+  gcSmmInitIdtr.Base +=3D sizeof (UINTN);
 
   //
   // Disable Interrupt, save InterruptState and save PEI IDT tab= le
   //
   InterruptState =3D SaveAndDisableInterrupts ();
@@ -270,21 +270,21 @@ InitSmmIdt (
   //
   // Save the PEI Services Table pointer
   // The PEI Services Table pointer will be stored in the sizeof= (UINTN) bytes
   // immediately preceding the IDT in memory.
   //
-  PeiServices         &n= bsp;            = ;             = =3D (CONST EFI_PEI_SERVICES **)(*(UINTN *)(PeiIdtr.Base - sizeof (UINTN)));=
-  (*(UINTN *)(gcSmiIdtr.Base - sizeof (UINTN))) =3D (UINTN)PeiService= s;
+  PeiServices         &n= bsp;            = ;            &n= bsp;    =3D (CONST EFI_PEI_SERVICES **)(*(UINTN *)(PeiIdtr.B= ase - sizeof (UINTN)));
+  (*(UINTN *)(gcSmmInitIdtr.Base - sizeof (UINTN))) =3D (UINTN)PeiSer= vices;
 
   //
   // Load SMM temporary IDT table
   //
-  AsmWriteIdtr (&gcSmiIdtr);
+  AsmWriteIdtr (&gcSmmInitIdtr);
 
   //
   // Setup SMM default exception handlers, SMM IDT table
-  // will be updated and saved in gcSmiIdtr
+  // will be updated and saved in gcSmmInitIdtr
   //
   Status =3D InitializeCpuExceptionHandlers (NULL);
   ASSERT_EFI_ERROR (Status);
 
   //
diff --git a/UefiCpuPkg/Library/SmmRelocationLib/X64/SmmInit.nasm b/UefiCpu= Pkg/Library/SmmRelocationLib/X64/SmmInit.nasm
index c790ad7ad8..8288b723c4 100644
--- a/UefiCpuPkg/Library/SmmRelocationLib/X64/SmmInit.nasm
+++ b/UefiCpuPkg/Library/SmmRelocationLib/X64/SmmInit.nasm
@@ -16,15 +16,15 @@
 
 extern ASM_PFX(SmmInitHandler)
 extern ASM_PFX(mRebasedFlag)
 extern ASM_PFX(mSmmRelocationOriginalAddress)
 
-global ASM_PFX(gPatchSmmCr3)
-global ASM_PFX(gPatchSmmCr4)
-global ASM_PFX(gPatchSmmCr0)
+global ASM_PFX(gPatchSmmInitCr3)
+global ASM_PFX(gPatchSmmInitCr4)
+global ASM_PFX(gPatchSmmInitCr0)
 global ASM_PFX(gPatchSmmInitStack)
-global ASM_PFX(gcSmiInitGdtr)
+global ASM_PFX(gcSmmInitGdtr)
 global ASM_PFX(gcSmmInitSize)
 global ASM_PFX(gcSmmInitTemplate)
 global ASM_PFX(gPatchRebasedFlagAddr32)
 global ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32)
 
@@ -82,11 +82,11 @@ CodeSeg64:
             DB=       0x9b
             DB=       0xaf      &nbs= p;         ; LimitHigh
             DB=       0       &= nbsp;           ; BaseHig= h
 GDT_SIZE equ $ -   NullSeg
 
-ASM_PFX(gcSmiInitGdtr):
+ASM_PFX(gcSmmInitGdtr):
     DW      GDT_SIZE - 1
     DQ      NullSeg
 
 
     DEFAULT REL
@@ -98,15 +98,15 @@ BITS 16
 ASM_PFX(SmmStartup):
     mov     eax, 0x80000001 &= nbsp;           ; read ca= pability
     cpuid
     mov     ebx, edx  &n= bsp;            = ;     ; rdmsr will change edx. keep it in ebx.
     mov     eax, strict dword 0&nb= sp;        ; source operand will be patc= hed
-ASM_PFX(gPatchSmmCr3):
+ASM_PFX(gPatchSmmInitCr3):
     mov     cr3, eax
-o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(Smm= Startup))]
+o32 lgdt    [cs:ebp + (ASM_PFX(gcSmmInitGdtr) - ASM_PFX(Smm= Startup))]
     mov     eax, strict dword 0&nb= sp;        ; source operand will be patc= hed
-ASM_PFX(gPatchSmmCr4):
+ASM_PFX(gPatchSmmInitCr4):
     or      ah,  2 =             &nb= sp;        ; enable XMM registers access=
     mov     cr4, eax
     mov     ecx, 0xc0000080 &= nbsp;           ; IA32_EF= ER MSR
     rdmsr
     or      ah, BIT0 &nb= sp;            =       ; set LME bit
@@ -114,11 +114,11 @@ ASM_PFX(gPatchSmmCr4):
     jz      .1
     or      ah, BIT3 &nb= sp;            =       ; set NXE bit
 .1:
     wrmsr
     mov     eax, strict dword 0&nb= sp;        ; source operand will be patc= hed
-ASM_PFX(gPatchSmmCr0):
+ASM_PFX(gPatchSmmInitCr0):
     mov     cr0, eax  &n= bsp;            = ;     ; enable protected mode & paging
     jmp     LONG_MODE_CS : dword 0=       ; offset will be patched to @LongMode
 @PatchLongModeOffset:
 
 BITS 64
--
2.16.2.windows.1

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