From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 29820780091 for ; Tue, 19 Dec 2023 06:29:47 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=4kNywjZJsnxStPjMBgUPB74lqeLfRnm4W3ikEqNf6nA=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1702967385; v=1; b=JYlft/NBV20rUCtwsnJPPtdAhqu2QeZUV1urUkoGe9aOupKXZAJAy4ruBqK1V7lF6r9uRtUx cHlF0C0nUIESGkVGIBHUvMcKYTIDnn9afm1B2Gr+y7lHi6KcwTmDJ2j0Ms22B7r28I3hL4s1MWb f7GDDAck+o6RQZfz6XBskUAQ= X-Received: by 127.0.0.2 with SMTP id kzQ4YY7687511xHBpp6W5GbQ; Mon, 18 Dec 2023 22:29:45 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by mx.groups.io with SMTP id smtpd.web11.6870.1702967385235459092 for ; Mon, 18 Dec 2023 22:29:45 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10928"; a="2445632" X-IronPort-AV: E=Sophos;i="6.04,287,1695711600"; d="scan'208";a="2445632" X-Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Dec 2023 22:29:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,287,1695711600"; d="scan'208";a="17485655" X-Received: from orsmsx601.amr.corp.intel.com ([10.22.229.14]) by orviesa002.jf.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 18 Dec 2023 22:29:45 -0800 X-Received: from orsmsx610.amr.corp.intel.com (10.22.229.23) by ORSMSX601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 18 Dec 2023 22:29:44 -0800 X-Received: from orsmsx610.amr.corp.intel.com (10.22.229.23) by ORSMSX610.amr.corp.intel.com (10.22.229.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 18 Dec 2023 22:29:44 -0800 X-Received: from orsedg603.ED.cps.intel.com (10.7.248.4) by orsmsx610.amr.corp.intel.com (10.22.229.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Mon, 18 Dec 2023 22:29:44 -0800 X-Received: from NAM12-MW2-obe.outbound.protection.outlook.com (104.47.66.41) by edgegateway.intel.com (134.134.137.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Mon, 18 Dec 2023 22:29:38 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=W4R49YG7vLXqTkLwbNCnZUKeSAHY41G88+ziUz+gRqTv1fFS+vNG/RAwLwHXiIykKXADTIV7z8uZXJa0/rpOvWcqGnA1BzEgxhMG93XMi7EhgvbTRtF92SRSFvtJL49/Grysoe/dDxbp/cgvcnKU1lwkz4UNKPxfgU0OooeF6+6gpHZpEhpYJ9Z8CxpDxgZGzHxTe+EMr4ZM9NaLzZwgbNvC671lfH00HDJCjsYynxHPlXhDoU/eYq5ynuJZgoQ3bkUhrYy3rnL5Czv/m9v/50Y8wwKghe9vN3PNoH/hM3J/PtAQWkVF3CCghpDBZwjXLuoc8ILgGPRw7+TY0pkA4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=iebuYAIGIxOYbNG8FpBbCZXRkXRbiKy0bYCHhVQvA2g=; b=BrpTvSH/b8St2nW+wjBXkDCFsgvLuujz/kPTfRvLOubOKKISVG/+E0JT/IsoExqhcSRVz1O0V7Zym3I232k9NljK7X28AD2ZWuDotXlIY4LgcKfedGuf198z9Ii9q2j2ysqJCeRmmrj058aAeJoIoI6i3c+mJmSAk19MVJIe1cWr1zkLbx9yiMKjd3IHsNK3vtHNCdLL4VXqGumOcM/jkTK5vfipW5Xi8LgIgztEzSvAHMhVE9hNXVuGLwnpo65Zjtio5vT6NYoDgkC8q2OKXh+M4xCOiddqbjQ4hNc28u5fzUKSFbB3gpjUwlYT2K/45hccytu0bg5H1uyaAuvWXA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none X-Received: from MN6PR11MB8244.namprd11.prod.outlook.com (2603:10b6:208:470::14) by MN0PR11MB6232.namprd11.prod.outlook.com (2603:10b6:208:3c3::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.38; Tue, 19 Dec 2023 06:29:36 +0000 X-Received: from MN6PR11MB8244.namprd11.prod.outlook.com ([fe80::b614:1f5e:8b0c:9858]) by MN6PR11MB8244.namprd11.prod.outlook.com ([fe80::b614:1f5e:8b0c:9858%4]) with mapi id 15.20.7091.034; Tue, 19 Dec 2023 06:29:36 +0000 From: "Ni, Ray" To: Chao Li , "devel@edk2.groups.io" CC: "Dong, Eric" , "Kumar, Rahul R" , Gerd Hoffmann Subject: Re: [edk2-devel] [PATCH v4 10/37] UefiCpuPkg: Add LoongArch64 CPU Timer library Thread-Topic: [PATCH v4 10/37] UefiCpuPkg: Add LoongArch64 CPU Timer library Thread-Index: AQHaLP0Aq6HKHny+f0KLclr1Pe0KS7CwL0NQ Date: Tue, 19 Dec 2023 06:29:36 +0000 Message-ID: References: <20231212130932.2467028-1-lichao@loongson.cn> <20231212131202.2470672-1-lichao@loongson.cn> In-Reply-To: <20231212131202.2470672-1-lichao@loongson.cn> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MN6PR11MB8244:EE_|MN0PR11MB6232:EE_ x-ms-office365-filtering-correlation-id: 8cc959bf-5af8-4623-fd9f-08dc005bdf07 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: vzSaQGwPveHCjRX2hW6Cr/V2iY9VmMT9jLzKeZds3Mu+it1C7M6SoOEVFt0GqpndeQIZa2EvzQbgj7PRpcxuCbDMi74xFaUVZXyxsa2lu1ys2Lu/KS0SWkMKdMgDaSD/IttXx08wmIwpYC7ms3sB0FhPxj6boTeT1p7GJt04dOb/4Nx8Ykz8TTUWV9CUArzsROFnMBhS9GkjH+hr3YH9RpxbJJSfCp/pJQMNF6xx9HEFT1tQwfJ/4ltZDwOR+f6BJM4UUIGOdz8gCHCuCVm02gCcF79BmWTYa+3JsuaoGLW1FfMEgVLDNd75YSP6bC3wtMcjLBbj0x1sG+Sn95tJDFgRCiv9/oHFsZxNF85duREreOzSUpdmVAkIOcEo9Md4PXIkpPcFSwOWyORcDKiXmWNUerlJ/3ACb2W7Tznen/03GzvQ20LW2/lkvKH9musiiZQ0RWNZorUjJi0AxnrlcscDZwZMKcFiDzQKvrkhCqHm/VgFa0mVzo2pjSqYepVQf/8W2FO1Sie/O4s7Unhap+7ISoJqv8doPBHG0cG2OLiG2m4P/vW93HKNSFgR5mziSL6tyk53ZPk9cx2c+juksx7UXqcThD27Y/n/1+zQJOw= x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?9jH1SAgiDGZRZYySWC+lvkAZvgN/Z5fjZ+SLwVNUm7e9SujWtV0zcuM7rMTD?= =?us-ascii?Q?/DrOPtQwUGZWyC7J1EoBD/DdngREHjqM8zWpI9yfIxSyYnrRVymqqbXThssi?= =?us-ascii?Q?B2YjMxzwo9nbXq62zZCkFCqhx2QZCF4BgffEU5vwDGHAAHkI0gRE2BZIvaXf?= =?us-ascii?Q?9GZmq3mGWunEx3r5HldWAvdeZhO+yc3n5rfZLfNW6wjfe8Jg8tUa5NpPS7H5?= =?us-ascii?Q?V35UyjklBHw+LDRjyyxJBKFNqL3ipTD7YD0ouTIDCOJIXdn0oNn1IUu6oobi?= =?us-ascii?Q?kBuvj7v3BRUp8eURNpwydSt3oIF9MqqdhUdxhRJouRkAByre1osfa9UG3m90?= =?us-ascii?Q?Q7tQF60VJJG3ZT0qO1oINSL7VRe37Uouw7zQd5V/l3QOTHE6WuERTzLXiHOB?= =?us-ascii?Q?wDtKt5ofkpFGO1r9OwLqPl0axOmDaCi4eDQ/TNQMhg1ujoCWcblwh+sXvYZL?= =?us-ascii?Q?XkAxATEXjjkDSMTdjTP6DvgKXhzIqQER4/hm2BsmGOWtfk+MlzFgjIs6/7f3?= =?us-ascii?Q?UJhS1aQSh6qrOCrRWA6/OtAiUdusfbHptll3pwRoExvdfvPoP5Qe1LTouCrH?= =?us-ascii?Q?Uwnx5hgyvaVyOG0PerKFqcr/cKWsNwWNdUxomhoLa3ajYpAx/dUxY3+rRCLY?= =?us-ascii?Q?jgID7ihlNRyTBfpjbB7DSjApJ+t6eAPziYi7NwcKQGC75R/RrIlmQaX3fY8C?= =?us-ascii?Q?HPU1HfoxgYcSu1LRb/jVH65Lilv1FOMfuPqVGxHjGeaUslfJ6ImXS3SPiMMo?= =?us-ascii?Q?g/Zm2jUauAR5FQHD4ZReovd16Cpv1qPAOMeCGvJQN42U/5z4YhsDNHsBRRw1?= =?us-ascii?Q?xDeAqNKbNyU/EGiqxXkvpOKWF/f9ubrJTaDOy5tUIptrtXdK1gcgmiKcYPbt?= =?us-ascii?Q?hlUq8Cqmk3loQzBVCA3tr19DAyeDYLLnDPd6IgYSCK7s0LD1/dosfT/Yg/Rm?= =?us-ascii?Q?SanoyxjuVpVTFMPFNHX/AtxoyY5LWFL/x2/pssDBmlXwLIQ4M+85yL6ME5c9?= =?us-ascii?Q?JNhtebtWJQRMiyxlg0y0du2ptD/BQUmdZGQm6P5Alz3fQWGXoZvPLYZ0/V7b?= =?us-ascii?Q?AWvge9/2PH/lFr+abA6whj0UsP17HR5Fzvv6txYRQZzvvIkf0vCsAx4IFGfB?= =?us-ascii?Q?grjpbvEDPADszqGnTfTwJhFy6z3EUKwTdzqiG/cHmhErOp0M5zTcOLl0JwZL?= =?us-ascii?Q?reMi6hNxjfj4Ezy6r9c34ClRtsqay8Z/rF8HWvCDAj5ZLZakkmVWx89jbC3J?= =?us-ascii?Q?FX8SNL5DQB8IIkySdPBCQfPprPFOecFMRGJ9oi2nuEUVf3Tu/13229J/71uO?= =?us-ascii?Q?Gt5zM/Li0VlWencI0+vpaG45PVhdZE42D7VlIn/yZ/jzUBe1hyopEh5GVTpI?= =?us-ascii?Q?5W49YJT9PH/oGXFYnOisLXeFuuGunDz5Yk4+pkykQ6ZITbDuJcNczUMemsU4?= =?us-ascii?Q?N4A6bnJBEpAU5VM/cwt3H5lWSeYFuvN991Y8VPwnUVAlFnejNxCBBF+5BWc0?= =?us-ascii?Q?OsFI8LPEY8r0YtPQkn8GylxYjKQ+Ob2x3wwaILzo5DK6YHbD4qh13MdSpl6t?= =?us-ascii?Q?3mrWKFEc5VCAWO+Scm4=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN6PR11MB8244.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8cc959bf-5af8-4623-fd9f-08dc005bdf07 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Dec 2023 06:29:36.3394 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: B3/dZhXD+dyMqkXuSrJ05t080LaAvBYWpVGaivENv8N837k117cGWcrUoRdejQPuk0crHlBmah5EECOYTLF8tg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR11MB6232 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Trxm6KsZz8zIYnmwBKqEFeb2x7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="JYlft/NB"; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Acked-by: Ray Ni Thanks, Ray > -----Original Message----- > From: Chao Li > Sent: Tuesday, December 12, 2023 9:12 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Kumar, > Rahul R ; Gerd Hoffmann > Subject: [PATCH v4 10/37] UefiCpuPkg: Add LoongArch64 CPU Timer library >=20 > Add the LoongArch64 CPU Timer library, using CPUCFG 0x4 and 0x5 for > Stable Counter frequency. >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4584 >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Cc: Gerd Hoffmann > Signed-off-by: Chao Li > --- > .../BaseLoongArch64CpuTimerLib.inf | 29 ++ > .../BaseLoongArch64CpuTimerLib.uni | 15 ++ > .../BaseLoongArch64CpuTimerLib/CpuTimerLib.c | 251 > ++++++++++++++++++ > UefiCpuPkg/UefiCpuPkg.dsc | 3 + > 4 files changed, 298 insertions(+) > create mode 100644 > UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTim > erLib.inf > create mode 100644 > UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTim > erLib.uni > create mode 100644 > UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c >=20 > diff --git > a/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuT > imerLib.inf > b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuT > imerLib.inf > new file mode 100644 > index 0000000000..ab94d91858 > --- /dev/null > +++ > b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuT > imerLib.inf > @@ -0,0 +1,29 @@ > +## @file > +# Base CPU Timer Library > +# > +# Provides base timer support using CPUCFG 0x4 and 0x5 stable counter > frequency. > +# > +# Copyright (c) 2023, Loongson Technology Corporation Limited. All righ= ts > reserved.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010029 > + BASE_NAME =3D > BaseLoongArch64CpuTimerLib > + FILE_GUID =3D > 740389C7-CC44-4A2F-88DC-89D97D312E7C > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D TimerLib > + MODULE_UNI_FILE =3D > BaseLoongArch64CpuTimerLib.uni > + > +[Sources] > + CpuTimerLib.c > + > +[Packages] > + MdePkg/MdePkg.dec > + > +[LibraryClasses] > + BaseLib > + DebugLib > + SafeIntLib > diff --git > a/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuT > imerLib.uni > b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuT > imerLib.uni > new file mode 100644 > index 0000000000..72d38ec679 > --- /dev/null > +++ > b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuT > imerLib.uni > @@ -0,0 +1,15 @@ > +// /** @file > +// Base CPU Timer Library > +// > +// Provides base timer support using CPUCFG 0x4 and 0x5 stable counter > frequency. > +// > +// Copyright (c) 2023, Loongson Technology Corporation Limited. All righ= ts > reserved.
> +// > +// SPDX-License-Identifier: BSD-2-Clause-Patent > +// > +// **/ > + > + > +#string STR_MODULE_ABSTRACT #language en-US > "LOONGARCH CPU Timer Library" > + > +#string STR_MODULE_DESCRIPTION #language en-US "Provides > basic timer support using CPUCFG 0x4 and 0x5 stable counter frequency." > diff --git a/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c > b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c > new file mode 100644 > index 0000000000..828ca4a51a > --- /dev/null > +++ b/UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/CpuTimerLib.c > @@ -0,0 +1,251 @@ > +/** @file > + CPUCFG 0x4 and 0x5 for Stable Counter frequency instance of Timer > Library. > + > + Copyright (c) 2023, Loongson Technology Corporation Limited. All right= s > reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Calculate clock frequency using CPUCFG 0x4 and 0x5 registers. > + > + @param VOID. > + > + @return The frequency in Hz. > + > +**/ > +STATIC > +UINT64 > +CalcConstFreq ( > + VOID > + ) > +{ > + UINT32 BaseFreq; > + UINT64 ClockMultiplier; > + UINT32 ClockDivide; > + CPUCFG_REG4_INFO_DATA CcFreq; > + CPUCFG_REG5_INFO_DATA CpucfgReg5Data; > + UINT64 StableTimerFreq; > + > + // > + // Get the the crystal frequency corresponding to the constant > + // frequency timer and the clock used by the timer. > + // > + AsmCpucfg (CPUCFG_REG4_INFO, &CcFreq.Uint32); > + > + // > + // Get the multiplication factor and frequency division factor > + // corresponding to the constant frequency timer and the clock > + // used by the timer. > + // > + AsmCpucfg (CPUCFG_REG5_INFO, &CpucfgReg5Data.Uint32); > + > + BaseFreq =3D CcFreq.Bits.CC_FREQ; > + ClockMultiplier =3D CpucfgReg5Data.Bits.CC_MUL & 0xFFFF; > + ClockDivide =3D CpucfgReg5Data.Bits.CC_DIV & 0xFFFF; > + > + if ((BaseFreq =3D=3D 0x0) || (ClockMultiplier =3D=3D 0x0) || (ClockDiv= ide =3D=3D 0x0)) { > + DEBUG (( > + DEBUG_ERROR, > + "LoongArch Stable Timer is not available in the CPU, hence this > library cannot be used.\n" > + )); > + ASSERT (FALSE); > + CpuDeadLoop (); > + } > + > + StableTimerFreq =3D ((ClockMultiplier * BaseFreq) / ClockDivide); > + > + if (StableTimerFreq =3D=3D 0x0) { > + ASSERT (FALSE); > + } > + > + return StableTimerFreq; > +} > + > +/** > + Stalls the CPU for at least the given number of microseconds. > + > + Stalls the CPU for the number of microseconds specified by MicroSecond= s. > + > + @param MicroSeconds The minimum number of microseconds to > delay. > + > + @return MicroSeconds > + > +**/ > +UINTN > +EFIAPI > +MicroSecondDelay ( > + IN UINTN MicroSeconds > + ) > +{ > + UINT64 CurrentTicks, ExceptedTicks, Remaining; > + RETURN_STATUS Status; > + > + Status =3D SafeUint64Mult (MicroSeconds, CalcConstFreq (), &Remaining)= ; > + ASSERT_RETURN_ERROR(Status); > + > + ExceptedTicks =3D DivU64x32 (Remaining, 1000000U); > + CurrentTicks =3D AsmReadStableCounter (); > + ExceptedTicks +=3D CurrentTicks; > + > + do { > + CurrentTicks =3D AsmReadStableCounter (); > + } while (CurrentTicks < ExceptedTicks); > + > + return MicroSeconds; > +} > + > +/** > + Stalls the CPU for at least the given number of nanoseconds. > + > + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. > + > + @param NanoSeconds The minimum number of nanoseconds to delay. > + > + @return NanoSeconds > + > +**/ > +UINTN > +EFIAPI > +NanoSecondDelay ( > + IN UINTN NanoSeconds > + ) > +{ > + UINTN MicroSeconds; > + > + // Round up to 1us Tick Number > + MicroSeconds =3D NanoSeconds / 1000; > + MicroSeconds +=3D ((NanoSeconds % 1000) =3D=3D 0) ? 0 : 1; > + > + MicroSecondDelay (MicroSeconds); > + > + return NanoSeconds; > +} > + > +/** > + Retrieves the current value of a 64-bit free running Stable Counter. > + > + The LoongArch defines a constant frequency timer, whose main body is a > + 64-bit counter called StableCounter. StableCounter is set to 0 after > + reset, and then increments by 1 every counting clock cycle. When the > + count reaches all 1s, it automatically wraps around to 0 and continues > + to increment. > + The properties of the Stable Counter can be retrieved from > + GetPerformanceCounterProperties(). > + > + @return The current value of the Stable Counter. > + > +**/ > +UINT64 > +EFIAPI > +GetPerformanceCounter ( > + VOID > + ) > +{ > + // > + // Just return the value of Stable Counter. > + // > + return AsmReadStableCounter (); > +} > + > +/** > + Retrieves the 64-bit frequency in Hz and the range of Stable Counter > + values. > + > + If StartValue is not NULL, then the value that the stbale counter star= ts > + with immediately after is it rolls over is returned in StartValue. If > + EndValue is not NULL, then the value that the stable counter end with > + immediately before it rolls over is returned in EndValue. The 64-bit > + frequency of the system frequency in Hz is always returned. > + > + @param StartValue The value the stable counter starts with when it > + rolls over. > + @param EndValue The value that the stable counter ends with > before > + it rolls over. > + > + @return The frequency in Hz. > + > +**/ > +UINT64 > +EFIAPI > +GetPerformanceCounterProperties ( > + OUT UINT64 *StartValue OPTIONAL, > + OUT UINT64 *EndValue OPTIONAL > + ) > +{ > + if (StartValue !=3D NULL) { > + *StartValue =3D 0; > + } > + > + if (EndValue !=3D NULL) { > + *EndValue =3D 0xFFFFFFFFFFFFFFFFULL; > + } > + > + return CalcConstFreq (); > +} > + > +/** > + Converts elapsed ticks of performance counter to time in nanoseconds. > + > + This function converts the elapsed ticks of running performance counte= r to > + time value in unit of nanoseconds. > + > + @param Ticks The number of elapsed ticks of running > performance counter. > + > + @return The elapsed time in nanoseconds. > + > +**/ > +UINT64 > +EFIAPI > +GetTimeInNanoSecond ( > + IN UINT64 Ticks > + ) > +{ > + UINT64 Frequency; > + UINT64 NanoSeconds; > + UINT64 Remainder; > + INTN Shift; > + RETURN_STATUS Status; > + > + Frequency =3D GetPerformanceCounterProperties (NULL, NULL); > + > + // > + // Ticks > + // Time =3D --------- x 1,000,000,000 > + // Frequency > + // > + Status =3D SafeUint64Mult ( > + DivU64x64Remainder (Ticks, Frequency, &Remainder), > + 1000000000u, > + &NanoSeconds > + ); > + > + // > + // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit. > + // Since 2^29 < 1,000,000,000 =3D 0x3B9ACA00 < 2^30, Remainder should = < > 2^(64-30) =3D 2^34, > + // i.e. highest bit set in Remainder should <=3D 33. > + // > + Shift =3D MAX (0, HighBitSet64 (Remainder) - 33); > + Remainder =3D RShiftU64 (Remainder, (UINTN)Shift); > + Frequency =3D RShiftU64 (Frequency, (UINTN)Shift); > + > + Status =3D SafeUint64Add ( > + NanoSeconds, > + DivU64x64Remainder ( > + MultU64x32 (Remainder, 1000000000u), > + Frequency, > + NULL > + ), > + &NanoSeconds > + ); > + ASSERT_RETURN_ERROR(Status); > + > + return NanoSeconds; > +} > diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc > index 074fd77461..8e34a9cd6b 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dsc > +++ b/UefiCpuPkg/UefiCpuPkg.dsc > @@ -205,5 +205,8 @@ > UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf >=20 > +[Components.LOONGARCH64] > + > UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTim > erLib.inf > + > [BuildOptions] > *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES > -- > 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112695): https://edk2.groups.io/g/devel/message/112695 Mute This Topic: https://groups.io/mt/103129089/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/19134562= 12/xyzzy [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-