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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Tan, Dun > Sent: Friday, March 24, 2023 2:00 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Kumar, > Rahul R ; Gerd Hoffmann > Subject: [Patch V5 20/22] UefiCpuPkg/CpuPageTableLib: Enable PAE paging >=20 > Modify CpuPageTableLib code to enable PAE paging. > In PageTableMap() API: > When creating new PAE page table, after creating page table, > set all MustBeZero fields of 4 PDPTE to 0. The MustBeZero > fields are treated as RW and other attributes by the common > map logic. So they might be set to 1. > When updating exsiting PAE page table, the special steps are: > 1.Prepare 4K-aligned 32bytes memory in stack for 4 temp PDPTE. > 2.Copy original 4 PDPTE to the 4 temp PDPTE and set the RW, > UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. > 4.After updating the page table, set the MustBeZero fields of > 4 temp PDPTE to 0. > 5.Copy the temp PDPTE to original PDPTE. >=20 > In PageTableParse() API, also create 4 temp PDPTE in stack. > Copy original 4 PDPTE to the 4 temp PDPTE. Then set the RW, > UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. Finally > use the address of temp PDPTE as the page table address. >=20 > Signed-off-by: Dun Tan > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Tested-by: Gerd Hoffmann > Acked-by: Gerd Hoffmann > --- > UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h | 2 ++ > UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 53 > ++++++++++++++++++++++++++++++++++++++++++++++++----- > UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c | 25 > +++++++++++++++++++++---- > 3 files changed, 71 insertions(+), 9 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h > b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h > index 2c67ecb469..8c4d43be89 100644 > --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h > +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h > @@ -20,6 +20,8 @@ >=20 > #define REGION_LENGTH(l) LShiftU64 (1, (l) * 9 + 3) >=20 > +#define MAX_PAE_PDPTE_NUM 4 > + > typedef enum { > Pte =3D 1, > Pde =3D 2, > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > index 2430f1b37c..7cdba0d77f 100644 > --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > @@ -671,15 +671,17 @@ PageTableMap ( > IA32_PAGE_LEVEL MaxLeafLevel; > IA32_MAP_ATTRIBUTE ParentAttribute; > BOOLEAN LocalIsModified; > + UINTN Index; > + IA32_PAGING_ENTRY *PagingEntry; > + UINT8 BufferInStack[SIZE_4KB - 1 + MAX_PAE_PDPTE_NUM * > sizeof (IA32_PAGING_ENTRY)]; >=20 > if (Length =3D=3D 0) { > return RETURN_SUCCESS; > } >=20 > - if ((PagingMode =3D=3D Paging32bit) || (PagingMode =3D=3D PagingPae) |= | > (PagingMode >=3D PagingModeMax)) { > + if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)= ) { > // > // 32bit paging is never supported. > - // PAE paging will be supported later. > // > return RETURN_UNSUPPORTED; > } > @@ -716,17 +718,32 @@ PageTableMap ( >=20 > MaxLeafLevel =3D (IA32_PAGE_LEVEL)(UINT8)PagingMode; > MaxLevel =3D (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8); > - MaxLinearAddress =3D LShiftU64 (1, 12 + MaxLevel * 9); > + MaxLinearAddress =3D (PagingMode =3D=3D PagingPae) ? LShiftU64 (1, 32)= : > LShiftU64 (1, 12 + MaxLevel * 9); >=20 > if ((LinearAddress > MaxLinearAddress) || (Length > MaxLinearAddress - > LinearAddress)) { > // > - // Maximum linear address is (1 << 48) or (1 << 57) > + // Maximum linear address is (1 << 32), (1 << 48) or (1 << 57) > // > return RETURN_INVALID_PARAMETER; > } >=20 > TopPagingEntry.Uintn =3D *PageTable; > if (TopPagingEntry.Uintn !=3D 0) { > + if (PagingMode =3D=3D PagingPae) { > + // > + // Create 4 temporary PDPTE at a 4k-aligned address. > + // Copy the original PDPTE content and set ReadWrite, UserSupervis= or to > 1, set Nx to 0. > + // > + TopPagingEntry.Uintn =3D ALIGN_VALUE ((UINTN)BufferInStack, > BASE_4KB); > + PagingEntry =3D (IA32_PAGING_ENTRY *)(TopPagingEntry.Uint= n); > + CopyMem (PagingEntry, (VOID *)(*PageTable), MAX_PAE_PDPTE_NUM > * sizeof (IA32_PAGING_ENTRY)); > + for (Index =3D 0; Index < MAX_PAE_PDPTE_NUM; Index++) { > + PagingEntry[Index].Pnle.Bits.ReadWrite =3D 1; > + PagingEntry[Index].Pnle.Bits.UserSupervisor =3D 1; > + PagingEntry[Index].Pnle.Bits.Nx =3D 0; > + } > + } > + > TopPagingEntry.Pce.Present =3D 1; > TopPagingEntry.Pce.ReadWrite =3D 1; > TopPagingEntry.Pce.UserSupervisor =3D 1; > @@ -801,7 +818,33 @@ PageTableMap ( > ); >=20 > if (!RETURN_ERROR (Status)) { > - *PageTable =3D (UINTN)(TopPagingEntry.Uintn & > IA32_PE_BASE_ADDRESS_MASK_40); > + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)(TopPagingEntry.Uintn & > IA32_PE_BASE_ADDRESS_MASK_40); > + > + if (PagingMode =3D=3D PagingPae) { > + // > + // These MustBeZero fields are treated as RW and other attributes = by > the common map logic. So they might be set to 1. > + // > + for (Index =3D 0; Index < MAX_PAE_PDPTE_NUM; Index++) { > + PagingEntry[Index].PdptePae.Bits.MustBeZero =3D 0; > + PagingEntry[Index].PdptePae.Bits.MustBeZero2 =3D 0; > + PagingEntry[Index].PdptePae.Bits.MustBeZero3 =3D 0; > + } > + > + if (*PageTable !=3D 0) { > + // > + // Copy temp PDPTE to original PDPTE. > + // > + CopyMem ((VOID *)(*PageTable), PagingEntry, > MAX_PAE_PDPTE_NUM * sizeof (IA32_PAGING_ENTRY)); > + } > + } > + > + if (*PageTable =3D=3D 0) { > + // > + // Do not assign the *PageTable when it's an existing page table. > + // If it's an existing PAE page table, PagingEntry is the temp buf= fer in > stack. > + // > + *PageTable =3D (UINTN)PagingEntry; > + } > } >=20 > return Status; > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c > b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c > index 65490751ab..f6d7b9bb4c 100644 > --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c > +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableParse.c > @@ -158,6 +158,7 @@ VOID > PageTableLibParsePnle ( > IN UINT64 PageTableBaseAddress, > IN UINTN Level, > + IN UINTN MaxLevel, > IN UINT64 RegionStart, > IN IA32_MAP_ATTRIBUTE *ParentMapAttribute, > IN OUT IA32_MAP_ENTRY *Map, > @@ -171,13 +172,15 @@ PageTableLibParsePnle ( > UINTN Index; > IA32_MAP_ATTRIBUTE MapAttribute; > UINT64 RegionLength; > + UINTN PagingEntryNumber; >=20 > ASSERT (OneEntry !=3D NULL); >=20 > - PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTableBaseAddress; > - RegionLength =3D REGION_LENGTH (Level); > + PagingEntry =3D (IA32_PAGING_ENTRY *)(UINTN)PageTableBaseAddress= ; > + RegionLength =3D REGION_LENGTH (Level); > + PagingEntryNumber =3D ((MaxLevel =3D=3D 3) && (Level =3D=3D 3)) ? > MAX_PAE_PDPTE_NUM : 512; >=20 > - for (Index =3D 0; Index < 512; Index++, RegionStart +=3D RegionLength)= { > + for (Index =3D 0; Index < PagingEntryNumber; Index++, RegionStart +=3D > RegionLength) { > if (PagingEntry[Index].Pce.Present =3D=3D 0) { > continue; > } > @@ -228,6 +231,7 @@ PageTableLibParsePnle ( > PageTableLibParsePnle ( > IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&PagingEntry[Index].Pnle), > Level - 1, > + MaxLevel, > RegionStart, > &MapAttribute, > Map, > @@ -269,6 +273,8 @@ PageTableParse ( > IA32_MAP_ENTRY *LastEntry; > IA32_MAP_ENTRY OneEntry; > UINTN MaxLevel; > + UINTN Index; > + IA32_PAGING_ENTRY BufferInStack[MAX_PAE_PDPTE_NUM]; >=20 > if ((PagingMode =3D=3D Paging32bit) || (PagingMode >=3D PagingModeMax)= ) { > // > @@ -290,6 +296,17 @@ PageTableParse ( > return RETURN_SUCCESS; > } >=20 > + if (PagingMode =3D=3D PagingPae) { > + CopyMem (BufferInStack, (VOID *)PageTable, sizeof (BufferInStack)); > + for (Index =3D 0; Index < MAX_PAE_PDPTE_NUM; Index++) { > + BufferInStack[Index].Pnle.Bits.ReadWrite =3D 1; > + BufferInStack[Index].Pnle.Bits.UserSupervisor =3D 1; > + BufferInStack[Index].Pnle.Bits.Nx =3D 0; > + } > + > + PageTable =3D (UINTN)BufferInStack; > + } > + > // > // Page table layout is as below: > // > @@ -319,7 +336,7 @@ PageTableParse ( > MapCapacity =3D *MapCount; > *MapCount =3D 0; > LastEntry =3D NULL; > - PageTableLibParsePnle ((UINT64)PageTable, MaxLevel, 0, &NopAttribute, > Map, MapCount, MapCapacity, &LastEntry, &OneEntry); > + PageTableLibParsePnle ((UINT64)PageTable, MaxLevel, MaxLevel, 0, > &NopAttribute, Map, MapCount, MapCapacity, &LastEntry, &OneEntry); >=20 > if (*MapCount > MapCapacity) { > return RETURN_BUFFER_TOO_SMALL; > -- > 2.31.1.windows.1