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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Tan, Dun > Sent: Friday, March 24, 2023 4:52 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Kumar, > Rahul R ; Gerd Hoffmann > Subject: [Patch V6 06/22] UefiCpuPkg/CpuPageTableLib: Fix issue when > splitting leaf entry >=20 > When splitting leaf parent entry to smaller granularity, create > child page table before modifing parent entry. In previous code > logic, when splitting a leaf parent entry, parent entry will > point to a null 4k memory before child page table is created in > this 4k memory. When the page table to be modified is the page > table in CR3, if the executed CpuPageTableLib code is in the > range mapped by the modified leaf parent entry, then issue will > happen. >=20 > Signed-off-by: Dun Tan > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Tested-by: Gerd Hoffmann > Acked-by: Gerd Hoffmann > --- > UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 19 > +++++++++++-------- > 1 file changed, 11 insertions(+), 8 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > index 57f1db203b..f09bb63ad1 100644 > --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > @@ -363,21 +363,24 @@ PageTableLibMapInLevel ( > // > // Create 512 child-level entries that map to 2M/4K. > // > - ParentPagingEntry->Uintn =3D (UINTN)Buffer + *BufferSize; > - ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB); > + PagingEntry =3D (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize)= ; > + ZeroMem (PagingEntry, SIZE_4KB); > + > + for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { > + PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffse= t; > + SubOffset +=3D RegionLength; > + } >=20 > // > // Set NOP attributes > // Note: Should NOT inherit the attributes from the original entry= because > a zero RW bit > // will make the entire region read-only even the child entr= ies set the > RW bit. > // > + // Non-leaf entry doesn't have PAT bit. So use > ~IA32_PE_BASE_ADDRESS_MASK_40 is to make sure PAT bit > + // (bit12) in original big-leaf entry is not assigned to > PageTableBaseAddress field of non-leaf entry. > + // > PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, > &AllOneMask); > - > - PagingEntry =3D (IA32_PAGING_ENTRY > *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry- > >Pnle); > - for (SubOffset =3D 0, Index =3D 0; Index < 512; Index++) { > - PagingEntry[Index].Uint64 =3D OneOfPagingEntry.Uint64 + SubOffse= t; > - SubOffset +=3D RegionLength; > - } > + ParentPagingEntry->Uint64 =3D ((UINTN)(VOID *)PagingEntry) | > (ParentPagingEntry->Uint64 & (~IA32_PE_BASE_ADDRESS_MASK_40)); > } > } else { > // > -- > 2.31.1.windows.1