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From: "Ni, Ray" <ray.ni@intel.com>
To: "Xue, Shengfeng" <xueshengfeng@byosoft.com.cn>,
	"devel@edk2.groups.io" <devel@edk2.groups.io>,
	"Dong, Eric" <eric.dong@intel.com>,
	"Kumar, Rahul R" <rahul.r.kumar@intel.com>,
	"kraxel@redhat.com" <kraxel@redhat.com>,
	"De, Debkumar" <debkumar.de@intel.com>,
	"West, Catharine" <catharine.west@intel.com>
Cc: "Wu, MingliangX" <mingliangx.wu@intel.com>
Subject: Re: [edk2-devel] [PATCH V1 1/1] UefiCpuPkg/ResetVector: Cache Disable should not be set by default in CR0
Date: Wed, 26 Jul 2023 09:55:45 +0000	[thread overview]
Message-ID: <MN6PR11MB82446CC5FF1F22468FF781318C00A@MN6PR11MB8244.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20230726094754.171-1-xueshengfeng@byosoft.com.cn>

This patch is not right.

Intel SDM explicitly says the initial CR0 value is 6000_0010. CD bit is set.

So the ResetVector code that still sets CD bit should be good.

If you are facing NEM enable failure, can you change your NEM enable logic to explicitly clear CD bit instead of changing here?

Thanks,
Ray


> -----Original Message-----
> From: xueshengfeng <xueshengfeng@byosoft.com.cn>
> Sent: Wednesday, July 26, 2023 5:48 PM
> To: devel@edk2.groups.io; Dong, Eric <eric.dong@intel.com>; Ni, Ray
> <ray.ni@intel.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>;
> kraxel@redhat.com; De, Debkumar <debkumar.de@intel.com>; West, Catharine
> <catharine.west@intel.com>
> Cc: Wu, MingliangX <mingliangx.wu@intel.com>; Wu
> Subject: [PATCH V1 1/1] UefiCpuPkg/ResetVector: Cache Disable should not be
> set by default in CR0
> 
> From: "Wu, MingliangX" <mingliangx.wu@intel.com>
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4511
> 
> With 64 bit build we are seeing the CD in control register CR 0 set.
> This causes the NEM to disabled for some specific bios profiles.
> 
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Debkumar De <debkumar.de@intel.com>
> Cc: Catharine West <catharine.west@intel.com>
> Signed-off-by: Wu, Mingliang <mingliangx.wu@intel.com>
> ---
>  UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
> b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
> index f59fc6ead4ba..4af2e875c31c 100644
> --- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
> +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
> @@ -7,7 +7,7 @@
>  ;
>  ;------------------------------------------------------------------------------
> 
> -%define SEC_DEFAULT_CR0  0x40000023
> +%define SEC_DEFAULT_CR0  0x00000023
>  %define SEC_DEFAULT_CR4  0x640
> 
>  BITS    16
> --
> 2.26.2.windows.1
> 



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  reply	other threads:[~2023-07-26  9:55 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-26  9:47 [edk2-devel] [PATCH V1 1/1] UefiCpuPkg/ResetVector: Cache Disable should not be set by default in CR0 xueshengfeng via groups.io
2023-07-26  9:55 ` Ni, Ray [this message]
     [not found] ` <177562550EF0534C.27380@groups.io>
2023-08-03  8:14   ` Ni, Ray
2024-01-10  7:51     ` Min Xu
2024-01-10 16:43       ` West, Catharine
2024-01-18 15:46         ` Gerd Hoffmann
2024-01-22 19:11           ` Brian J. Johnson
2024-01-23  5:01             ` Min Xu
2024-01-23 10:52             ` Gerd Hoffmann
2024-01-23 14:13               ` Laszlo Ersek
2024-01-23 16:11                 ` Gerd Hoffmann
2024-01-24  3:06                   ` Min Xu
2024-01-24 12:49                   ` Laszlo Ersek
2024-01-24 13:26                     ` Gerd Hoffmann
2024-01-24 14:45                       ` Laszlo Ersek
2024-01-24 17:11                         ` Gerd Hoffmann

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