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=?us-ascii?Q?38QZvq562fDH5uY0rqE=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN6PR11MB8244.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c9d233d8-fca3-49cd-b967-08db8dbe7b94 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Jul 2023 09:55:45.9395 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pPe8o97ovtdVgRFms/NC9oeNDQI4mhELRfla8zmAsPctBIw4fNxRdImv31jCPWxdY3vIGD+xiKFwAcEedeseNw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR11MB4557 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 3pPJNv8andIeUvqt1jp7nLopx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=HbZsEmD+; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io This patch is not right. Intel SDM explicitly says the initial CR0 value is 6000_0010. CD bit is set= . So the ResetVector code that still sets CD bit should be good. If you are facing NEM enable failure, can you change your NEM enable logic = to explicitly clear CD bit instead of changing here? Thanks, Ray > -----Original Message----- > From: xueshengfeng > Sent: Wednesday, July 26, 2023 5:48 PM > To: devel@edk2.groups.io; Dong, Eric ; Ni, Ray > ; Kumar, Rahul R ; > kraxel@redhat.com; De, Debkumar ; West, Catharine > > Cc: Wu, MingliangX ; Wu > Subject: [PATCH V1 1/1] UefiCpuPkg/ResetVector: Cache Disable should not = be > set by default in CR0 >=20 > From: "Wu, MingliangX" >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4511 >=20 > With 64 bit build we are seeing the CD in control register CR 0 set. > This causes the NEM to disabled for some specific bios profiles. >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Cc: Gerd Hoffmann > Cc: Debkumar De > Cc: Catharine West > Signed-off-by: Wu, Mingliang > --- > UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm > b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm > index f59fc6ead4ba..4af2e875c31c 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm > +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm > @@ -7,7 +7,7 @@ > ; > ;-----------------------------------------------------------------------= ------- >=20 > -%define SEC_DEFAULT_CR0 0x40000023 > +%define SEC_DEFAULT_CR0 0x00000023 > %define SEC_DEFAULT_CR4 0x640 >=20 > BITS 16 > -- > 2.26.2.windows.1 >=20 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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