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=?us-ascii?Q?7evQ1Zy2y0G6cS39+Q0=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN6PR11MB8244.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5e9fc416-33f6-4401-abbd-08dc0e665f65 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Jan 2024 03:20:02.9572 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: CEKYY1HUsch8gz1nFZQqqnXbUuotxMKnGfnESt/+taW/oiccfJt8dgn8wun0eBNLVC0F6VV8ByMDpEv/mlrFWA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR11MB5304 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 969hIrIDlsFH8B4Tp3oYSdg7x7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Xm6ZBquo; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Ray Ni Thanks, Ray > -----Original Message----- > From: Chao Li > Sent: Friday, January 5, 2024 5:44 PM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Kumar, Rahul R ; > Gerd Hoffmann ; Leif Lindholm > ; Ard Biesheuvel ; > Sami Mujawar > Subject: [PATCH v6 18/36] UefiCpuPkg: Add a new CPU IO 2 driver named > CpuMmio2Dxe >=20 > CpuIo2Dxe only supports IO to access to CPU IO. Some ARCHs that do not > implement ports for CPU IO require MMIO to access PCI IO, and they > pretty much put the IO devices under the LPC bus, which is usually under > the PCIe/PCI bus. CpuMmio2Dxe was added to meet these needs. >=20 > CpuMmio2Dxe depends on PcdPciIoTranslation. The code is copied from > ArmPkg. >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4584 >=20 > Cc: Ray Ni > Cc: Rahul Kumar > Cc: Gerd Hoffmann > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Cc: Sami Mujawar > Signed-off-by: Chao Li > --- > UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c | 557 > +++++++++++++++++++++++++ > UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf | 48 +++ > UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni | 18 + > UefiCpuPkg/UefiCpuPkg.dsc | 2 + > 4 files changed, 625 insertions(+) > create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c > create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf > create mode 100644 UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni >=20 > diff --git a/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c > b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c > new file mode 100644 > index 0000000000..32ccac1cc6 > --- /dev/null > +++ b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.c > @@ -0,0 +1,557 @@ > +/** @file > + Produces the CPU I/O 2 Protocol. > + > +Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
> +Copyright (c) 2016, Linaro Ltd. All rights reserved.
> +Copyright (c) 2024 Loongson Technology Corporation Limited. All rights > reserved.
> + > +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > + > +#include > + > +#include > +#include > +#include > +#include > +#include > + > +#define MAX_IO_PORT_ADDRESS 0xFFFF > + > +// > +// Handle for the CPU I/O 2 Protocol > +// > +STATIC EFI_HANDLE mHandle =3D NULL; > + > +// > +// Lookup table for increment values based on transfer widths > +// > +STATIC CONST UINT8 mInStride[] =3D { > + 1, // EfiCpuIoWidthUint8 > + 2, // EfiCpuIoWidthUint16 > + 4, // EfiCpuIoWidthUint32 > + 8, // EfiCpuIoWidthUint64 > + 0, // EfiCpuIoWidthFifoUint8 > + 0, // EfiCpuIoWidthFifoUint16 > + 0, // EfiCpuIoWidthFifoUint32 > + 0, // EfiCpuIoWidthFifoUint64 > + 1, // EfiCpuIoWidthFillUint8 > + 2, // EfiCpuIoWidthFillUint16 > + 4, // EfiCpuIoWidthFillUint32 > + 8 // EfiCpuIoWidthFillUint64 > +}; > + > +// > +// Lookup table for increment values based on transfer widths > +// > +STATIC CONST UINT8 mOutStride[] =3D { > + 1, // EfiCpuIoWidthUint8 > + 2, // EfiCpuIoWidthUint16 > + 4, // EfiCpuIoWidthUint32 > + 8, // EfiCpuIoWidthUint64 > + 1, // EfiCpuIoWidthFifoUint8 > + 2, // EfiCpuIoWidthFifoUint16 > + 4, // EfiCpuIoWidthFifoUint32 > + 8, // EfiCpuIoWidthFifoUint64 > + 0, // EfiCpuIoWidthFillUint8 > + 0, // EfiCpuIoWidthFillUint16 > + 0, // EfiCpuIoWidthFillUint32 > + 0 // EfiCpuIoWidthFillUint64 > +}; > + > +/** > + Check parameters to a CPU I/O 2 Protocol service request. > + > + The I/O operations are carried out exactly as requested. The caller is > responsible > + for satisfying any alignment and I/O width restrictions that a PI Syst= em on a > + platform might require. For example on some platforms, width requests = of > + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand= , > will > + be handled by the driver. > + > + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O > Port operation. > + @param[in] Width Signifies the width of the I/O or Memory ope= ration. > + @param[in] Address The base address of the I/O operation. > + @param[in] Count The number of I/O operations to perform. The > number of > + bytes moved is Width size * Count, starting = at Address. > + @param[in] Buffer For read operations, the destination buffer = to store > the results. > + For write operations, the source buffer from= which to write > data. > + > + @retval EFI_SUCCESS The parameters for this request pass th= e checks. > + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. > + @retval EFI_INVALID_PARAMETER Buffer is NULL. > + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given > Width. > + @retval EFI_UNSUPPORTED The address range specified by Address, > Width, > + and Count is not valid for this PI syst= em. > + > +**/ > +STATIC > +EFI_STATUS > +CpuIoCheckParameter ( > + IN BOOLEAN MmioOperation, > + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, > + IN UINT64 Address, > + IN UINTN Count, > + IN VOID *Buffer > + ) > +{ > + UINT64 MaxCount; > + UINT64 Limit; > + > + // > + // Check to see if Buffer is NULL > + // > + if (Buffer =3D=3D NULL) { > + return EFI_INVALID_PARAMETER; > + } > + > + // > + // Check to see if Width is in the valid range > + // > + if ((UINT32)Width >=3D EfiCpuIoWidthMaximum) { > + return EFI_INVALID_PARAMETER; > + } > + > + // > + // For FIFO type, the target address won't increase during the access, > + // so treat Count as 1 > + // > + if ((Width >=3D EfiCpuIoWidthFifoUint8) && (Width <=3D > EfiCpuIoWidthFifoUint64)) { > + Count =3D 1; > + } > + > + // > + // Check to see if Width is in the valid range for I/O Port operations > + // > + Width =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); > + if (!MmioOperation && (Width =3D=3D EfiCpuIoWidthUint64)) { > + return EFI_INVALID_PARAMETER; > + } > + > + // > + // Check to see if Address is aligned > + // > + if ((Address & (UINT64)(mInStride[Width] - 1)) !=3D 0) { > + return EFI_UNSUPPORTED; > + } > + > + // > + // Check to see if any address associated with this transfer exceeds t= he > maximum > + // allowed address. The maximum address implied by the parameters > passed in is > + // Address + Size * Count. If the following condition is met, then th= e transfer > + // is not supported. > + // > + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : > MAX_IO_PORT_ADDRESS) + 1 > + // > + // Since MAX_ADDRESS can be the maximum integer value supported by the > CPU and Count > + // can also be the maximum integer value supported by the CPU, this ra= nge > + // check must be adjusted to avoid all overflow conditions. > + // > + // The following form of the range check is equivalent but assumes tha= t > + // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1). > + // > + Limit =3D (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); > + if (Count =3D=3D 0) { > + if (Address > Limit) { > + return EFI_UNSUPPORTED; > + } > + } else { > + MaxCount =3D RShiftU64 (Limit, Width); > + if (MaxCount < (Count - 1)) { > + return EFI_UNSUPPORTED; > + } > + > + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { > + return EFI_UNSUPPORTED; > + } > + } > + > + // > + // Check to see if Buffer is aligned > + // > + if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) = !=3D 0) { > + return EFI_UNSUPPORTED; > + } > + > + return EFI_SUCCESS; > +} > + > +/** > + Reads memory-mapped registers. > + > + The I/O operations are carried out exactly as requested. The caller is > responsible > + for satisfying any alignment and I/O width restrictions that a PI Syst= em on a > + platform might require. For example on some platforms, width requests = of > + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand= , > will > + be handled by the driver. > + > + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, > EfiCpuIoWidthUint32, > + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented f= or > + each of the Count operations that is performed. > + > + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, > + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer = is > + incremented for each of the Count operations that is performed. The re= ad or > + write operation is performed Count times on the same Address. > + > + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, > + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address= is > + incremented for each of the Count operations that is performed. The re= ad or > + write operation is performed Count times from the first element of Buf= fer. > + > + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. > + @param[in] Width Signifies the width of the I/O or Memory operatio= n. > + @param[in] Address The base address of the I/O operation. > + @param[in] Count The number of I/O operations to perform. The numb= er > of > + bytes moved is Width size * Count, starting at Ad= dress. > + @param[out] Buffer For read operations, the destination buffer to st= ore > the results. > + For write operations, the source buffer from whic= h to write data. > + > + @retval EFI_SUCCESS The data was read from or written to th= e PI > system. > + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. > + @retval EFI_INVALID_PARAMETER Buffer is NULL. > + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given > Width. > + @retval EFI_UNSUPPORTED The address range specified by Address, > Width, > + and Count is not valid for this PI syst= em. > + > +**/ > +STATIC > +EFI_STATUS > +EFIAPI > +CpuMemoryServiceRead ( > + IN EFI_CPU_IO2_PROTOCOL *This, > + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, > + IN UINT64 Address, > + IN UINTN Count, > + OUT VOID *Buffer > + ) > +{ > + EFI_STATUS Status; > + UINT8 InStride; > + UINT8 OutStride; > + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; > + UINT8 *Uint8Buffer; > + > + Status =3D CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + // > + // Select loop based on the width of the transfer > + // > + InStride =3D mInStride[Width]; > + OutStride =3D mOutStride[Width]; > + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); > + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Bu= ffer +=3D > OutStride, Count--) { > + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { > + *Uint8Buffer =3D MmioRead8 ((UINTN)Address); > + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { > + *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); > + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { > + *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); > + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { > + *((UINT64 *)Uint8Buffer) =3D MmioRead64 ((UINTN)Address); > + } > + } > + > + return EFI_SUCCESS; > +} > + > +/** > + Writes memory-mapped registers. > + > + The I/O operations are carried out exactly as requested. The caller is > responsible > + for satisfying any alignment and I/O width restrictions that a PI Syst= em on a > + platform might require. For example on some platforms, width requests = of > + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand= , > will > + be handled by the driver. > + > + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, > EfiCpuIoWidthUint32, > + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented f= or > + each of the Count operations that is performed. > + > + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, > + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer = is > + incremented for each of the Count operations that is performed. The re= ad or > + write operation is performed Count times on the same Address. > + > + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, > + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address= is > + incremented for each of the Count operations that is performed. The re= ad or > + write operation is performed Count times from the first element of Buf= fer. > + > + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. > + @param[in] Width Signifies the width of the I/O or Memory operatio= n. > + @param[in] Address The base address of the I/O operation. > + @param[in] Count The number of I/O operations to perform. The numb= er > of > + bytes moved is Width size * Count, starting at Ad= dress. > + @param[in] Buffer For read operations, the destination buffer to st= ore the > results. > + For write operations, the source buffer from whic= h to write data. > + > + @retval EFI_SUCCESS The data was read from or written to th= e PI > system. > + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. > + @retval EFI_INVALID_PARAMETER Buffer is NULL. > + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given > Width. > + @retval EFI_UNSUPPORTED The address range specified by Address, > Width, > + and Count is not valid for this PI syst= em. > + > +**/ > +STATIC > +EFI_STATUS > +EFIAPI > +CpuMemoryServiceWrite ( > + IN EFI_CPU_IO2_PROTOCOL *This, > + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, > + IN UINT64 Address, > + IN UINTN Count, > + IN VOID *Buffer > + ) > +{ > + EFI_STATUS Status; > + UINT8 InStride; > + UINT8 OutStride; > + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; > + UINT8 *Uint8Buffer; > + > + Status =3D CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + // > + // Select loop based on the width of the transfer > + // > + InStride =3D mInStride[Width]; > + OutStride =3D mOutStride[Width]; > + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); > + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Bu= ffer +=3D > OutStride, Count--) { > + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { > + MmioWrite8 ((UINTN)Address, *Uint8Buffer); > + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { > + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); > + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { > + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); > + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { > + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); > + } > + } > + > + return EFI_SUCCESS; > +} > + > +/** > + Reads I/O registers. > + > + The I/O operations are carried out exactly as requested. The caller is > responsible > + for satisfying any alignment and I/O width restrictions that a PI Syst= em on a > + platform might require. For example on some platforms, width requests = of > + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand= , > will > + be handled by the driver. > + > + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, > EfiCpuIoWidthUint32, > + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented f= or > + each of the Count operations that is performed. > + > + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, > + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer = is > + incremented for each of the Count operations that is performed. The re= ad or > + write operation is performed Count times on the same Address. > + > + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, > + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address= is > + incremented for each of the Count operations that is performed. The re= ad or > + write operation is performed Count times from the first element of Buf= fer. > + > + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. > + @param[in] Width Signifies the width of the I/O or Memory operatio= n. > + @param[in] Address The base address of the I/O operation. > + @param[in] Count The number of I/O operations to perform. The numb= er > of > + bytes moved is Width size * Count, starting at Ad= dress. > + @param[out] Buffer For read operations, the destination buffer to st= ore > the results. > + For write operations, the source buffer from whic= h to write data. > + > + @retval EFI_SUCCESS The data was read from or written to th= e PI > system. > + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. > + @retval EFI_INVALID_PARAMETER Buffer is NULL. > + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given > Width. > + @retval EFI_UNSUPPORTED The address range specified by Address, > Width, > + and Count is not valid for this PI syst= em. > + > +**/ > +STATIC > +EFI_STATUS > +EFIAPI > +CpuIoServiceRead ( > + IN EFI_CPU_IO2_PROTOCOL *This, > + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, > + IN UINT64 Address, > + IN UINTN Count, > + OUT VOID *Buffer > + ) > +{ > + EFI_STATUS Status; > + UINT8 InStride; > + UINT8 OutStride; > + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; > + UINT8 *Uint8Buffer; > + > + Status =3D CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + Address +=3D PcdGet64 (PcdPciIoTranslation); > + > + // > + // Select loop based on the width of the transfer > + // > + InStride =3D mInStride[Width]; > + OutStride =3D mOutStride[Width]; > + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); > + > + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Bu= ffer +=3D > OutStride, Count--) { > + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { > + *Uint8Buffer =3D MmioRead8 ((UINTN)Address); > + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { > + *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); > + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { > + *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); > + } > + } > + > + return EFI_SUCCESS; > +} > + > +/** > + Write I/O registers. > + > + The I/O operations are carried out exactly as requested. The caller is > responsible > + for satisfying any alignment and I/O width restrictions that a PI Syst= em on a > + platform might require. For example on some platforms, width requests = of > + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand= , > will > + be handled by the driver. > + > + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, > EfiCpuIoWidthUint32, > + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented f= or > + each of the Count operations that is performed. > + > + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, > + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer = is > + incremented for each of the Count operations that is performed. The re= ad or > + write operation is performed Count times on the same Address. > + > + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, > + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address= is > + incremented for each of the Count operations that is performed. The re= ad or > + write operation is performed Count times from the first element of Buf= fer. > + > + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. > + @param[in] Width Signifies the width of the I/O or Memory operatio= n. > + @param[in] Address The base address of the I/O operation. > + @param[in] Count The number of I/O operations to perform. The numb= er > of > + bytes moved is Width size * Count, starting at Ad= dress. > + @param[in] Buffer For read operations, the destination buffer to st= ore the > results. > + For write operations, the source buffer from whic= h to write data. > + > + @retval EFI_SUCCESS The data was read from or written to th= e PI > system. > + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. > + @retval EFI_INVALID_PARAMETER Buffer is NULL. > + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given > Width. > + @retval EFI_UNSUPPORTED The address range specified by Address, > Width, > + and Count is not valid for this PI syst= em. > + > +**/ > +STATIC > +EFI_STATUS > +EFIAPI > +CpuIoServiceWrite ( > + IN EFI_CPU_IO2_PROTOCOL *This, > + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, > + IN UINT64 Address, > + IN UINTN Count, > + IN VOID *Buffer > + ) > +{ > + EFI_STATUS Status; > + UINT8 InStride; > + UINT8 OutStride; > + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; > + UINT8 *Uint8Buffer; > + > + // > + // Make sure the parameters are valid > + // > + Status =3D CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + Address +=3D PcdGet64 (PcdPciIoTranslation); > + > + // > + // Select loop based on the width of the transfer > + // > + InStride =3D mInStride[Width]; > + OutStride =3D mOutStride[Width]; > + OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); > + > + for (Uint8Buffer =3D (UINT8 *)Buffer; Count > 0; Address +=3D InStride= , > Uint8Buffer +=3D OutStride, Count--) { > + if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { > + MmioWrite8 ((UINTN)Address, *Uint8Buffer); > + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { > + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); > + } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { > + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); > + } > + } > + > + return EFI_SUCCESS; > +} > + > +// > +// CPU I/O 2 Protocol instance > +// > +STATIC EFI_CPU_IO2_PROTOCOL mCpuMmio2 =3D { > + { > + CpuMemoryServiceRead, > + CpuMemoryServiceWrite > + }, > + { > + CpuIoServiceRead, > + CpuIoServiceWrite > + } > +}; > + > +/** > + The user Entry Point for module CpuIo2Dxe. The user code starts with t= his > function. > + > + @param[in] ImageHandle The firmware allocated handle for the EFI im= age. > + @param[in] SystemTable A pointer to the EFI System Table. > + > + @retval EFI_SUCCESS The entry point is executed successfully. > + @retval other Some error occurs when executing this entry = point. > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuMmio2Initialize ( > + IN EFI_HANDLE ImageHandle, > + IN EFI_SYSTEM_TABLE *SystemTable > + ) > +{ > + EFI_STATUS Status; > + > + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, > &gEfiCpuIo2ProtocolGuid); > + Status =3D gBS->InstallMultipleProtocolInterfaces ( > + &mHandle, > + &gEfiCpuIo2ProtocolGuid, > + &mCpuMmio2, > + NULL > + ); > + ASSERT_EFI_ERROR (Status); > + > + return Status; > +} > diff --git a/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf > b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf > new file mode 100644 > index 0000000000..32577be7ea > --- /dev/null > +++ b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf > @@ -0,0 +1,48 @@ > +## @file > +# Produces the CPU I/O 2 Protocol by using the services of the I/O Libr= ary. > +# > +# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.
> +# Copyright (c) 2016, Linaro Ltd. All rights reserved.
> +# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights > reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 1.29 > + BASE_NAME =3D CpuMmio2Dxe > + MODULE_UNI_FILE =3D CpuMmio2Dxe.uni > + FILE_GUID =3D FBC36D76-CF22-2584-DBD8-85FF765BAEF= 1 > + MODULE_TYPE =3D DXE_DRIVER > + VERSION_STRING =3D 1.0 > + ENTRY_POINT =3D CpuMmio2Initialize > + > +# > +# The following information is for reference only and not required by th= e build > tools. > +# > +# VALID_ARCHITECTURES =3D ARM AARCH64 LOONGARCH64 RISCV64 > +# > + > +[Sources] > + CpuMmio2Dxe.c > + > +[Packages] > + MdePkg/MdePkg.dec > + > +[LibraryClasses] > + UefiDriverEntryPoint > + BaseLib > + DebugLib > + IoLib > + PcdLib > + UefiBootServicesTableLib > + > +[Pcd] > + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation > + > +[Protocols] > + gEfiCpuIo2ProtocolGuid ## PRODUCES > + > +[Depex] > + TRUE > diff --git a/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni > b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni > new file mode 100644 > index 0000000000..af3b1a656f > --- /dev/null > +++ b/UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.uni > @@ -0,0 +1,18 @@ > +// /** @file > +// Produces the CPU I/O 2 Protocol by using the services of the I/O Libr= ary. > +// > +// Produces the CPU I/O 2 Protocol by using the services of the I/O Libr= ary. > +// > +// Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved. > +// Copyright (c) 2016, Linaro Ltd. All rights reserved.
> +// Copyright (c) 2024 Loongson Technology Corporation Limited. All right= s > reserved.
> +// > +// SPDX-License-Identifier: BSD-2-Clause-Patent > +// > +// **/ > + > + > +#string STR_MODULE_ABSTRACT #language en-US "Produces the CP= U > I/O 2 Protocol by using the services of the I/O Library" > + > +#string STR_MODULE_DESCRIPTION #language en-US "Produces the > CPU I/O 2 Protocol by using the services of the I/O Library." > + > diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc > index 68e36f6a8e..3880017684 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dsc > +++ b/UefiCpuPkg/UefiCpuPkg.dsc > @@ -206,6 +206,7 @@ > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf > + UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf >=20 > [Components.LOONGARCH64] >=20 > UefiCpuPkg/Library/BaseLoongArch64CpuTimerLib/BaseLoongArch64CpuTim > erLib.inf > @@ -216,6 +217,7 @@ > UefiCpuPkg/Library/LoongArch64MpInitLib/PeiMpInitLib.inf > UefiCpuPkg/Library/LoongArch64MpInitLib/DxeMpInitLib.inf > UefiCpuPkg/CpuDxeLoongArch64/CpuDxe.inf > + UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf >=20 > [BuildOptions] > *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES > -- > 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113323): https://edk2.groups.io/g/devel/message/113323 Mute This Topic: https://groups.io/mt/103540111/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/19134562= 12/xyzzy [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-