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charset="us-ascii" Content-Transfer-Encoding: quoted-printable >=20 > But with 5-level paging enabled the reset vector should be able to > fallback to 4-level paging in case the CPU does not support 5-level > paging. The fallback makes sense. Otherwise, forcing to use 5L in an incapable CPU would be a silent failure because IDT and debug log are not enabled at this early stage. Later CpuPei/Dxe module could dump the paging status to tell platform owner that what level is used in this boot. With that, that means a 4L reset vector can save 4K space by excluding the = PML5 page. But a 5L reset vector could set CR3 to PML4 page if CPU is incapable. Thanks, Ray