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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Jiaxin, SDM has following: > 3.3.7.1 Canonical Addressing > In 64-bit mode, an address is considered to be in canonical form if **add= ress bits 63 through to the most-significant implemented bit by the microar= chitecture are set to either all ones or all zeros**. > Intel 64 architecture defines a 64-bit linear address. Implementations ca= n support less. The first implementation of IA-32 processors with Intel 64 = architecture supports a 48-bit linear address. This means a canonical addre= ss must have bits 63 through 48 set to zeros or ones (depending on whether = bit 47 is a zero or one). > Although implementations may not use all 64 bits of the linear address, t= hey should check bits 63 through the most-significant implemented bit to se= e if the address is in canonical form. If a linear-memory reference is not = in canonical form, the implementation should generate an exception. In most= cases, a general-protection exception (#GP) is generated. > -----Original Message----- > From: Wu, Jiaxin > Sent: Wednesday, May 10, 2023 10:00 AM > To: Gerd Hoffmann ; devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Zeng, S= tar > ; Kumar, Rahul R > Subject: RE: [edk2-devel] [PATCH v1 1/3] UefiCpuPkg/SecCore: Migrate page > table to permanent memory >=20 > Hi Gerd, >=20 > Could you share me which document introduce the sign-extended impact the > line address width? >=20 > Thanks, > Jiaxin >=20 > > -----Original Message----- > > From: Gerd Hoffmann > > Sent: Tuesday, May 9, 2023 10:39 PM > > To: devel@edk2.groups.io; Wu, Jiaxin > > Cc: Dong, Eric ; Ni, Ray ; Zeng,= Star > > ; Kumar, Rahul R > > Subject: Re: [edk2-devel] [PATCH v1 1/3] UefiCpuPkg/SecCore: Migrate pa= ge > > table to permanent memory > > > > Hi, > > > > > + if (PagingMode =3D=3D Paging4Level1GB || PagingMode =3D=3D Paging4= Level) { > > > + // > > > + // The max lineaddress bits is 48 for 4 level page table. > > > + // > > > + VirPhyAddressSize.Bits.PhysicalAddressBits =3D MIN > > (VirPhyAddressSize.Bits.PhysicalAddressBits, 48); > > > + } > > > > virtual addresses in long mode are sign-extended. Which means you have > > only 47 bits (or 56 bits with 5-level paging) for identity mappings. > > > > take care, > > Gerd