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Thread-Topic: [edk2-devel] [PATCH v1 3/3] MdeModulePkg/DxeIpl: Align Page table Level setting with previous level. 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Minor comments: IA32 -> 32bit protected mode. X64 -> 64bit long mode. > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Wu, Jiaxin > Sent: Tuesday, May 9, 2023 6:23 PM > To: devel@edk2.groups.io > Cc: Bi, Dandan ; Gao, Liming > ; Dong, Eric ; Ni, Ray > ; Zeng, Star ; Gerd Hoffmann > ; Kumar, Rahul R > Subject: [edk2-devel] [PATCH v1 3/3] MdeModulePkg/DxeIpl: Align Page tabl= e > Level setting with previous level. >=20 > System paging 5 level enabled or not can be checked via CR4.LA57, system > preferred Page table Level (PcdUse5LevelPageTable) must align > with previous level for X64 mode. >=20 > This patch is to do the wise check: > If X64, Page table Level setting in PcdUse5LevelPageTable must align with > previous level. > If IA32, Page table Level is decided by PcdUse5LevelPageTable and feature > capability. >=20 > Change-Id: Ia7f7e365c7354cc49f971209bfcbc5af5aded062 > Cc: Dandan Bi > Cc: Liming Gao > Cc: Eric Dong > Cc: Ray Ni > Cc: Zeng Star > Cc: Gerd Hoffmann > Cc: Rahul Kumar > Signed-off-by: Jiaxin Wu > --- > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 39 > ++++++++++++++++-------- > 1 file changed, 27 insertions(+), 12 deletions(-) >=20 > diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > index 18b121d768..301e200cd8 100644 > --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > @@ -737,22 +737,37 @@ CreateIdentityMappingPageTables ( > } else { > PhysicalAddressBits =3D 36; > } > } >=20 > - Page5LevelSupport =3D FALSE; > - if (PcdGetBool (PcdUse5LevelPageTable)) { > - AsmCpuidEx ( > - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, > - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, > - NULL, > - NULL, > - &EcxFlags.Uint32, > - NULL > - ); > - if (EcxFlags.Bits.FiveLevelPage !=3D 0) { > - Page5LevelSupport =3D TRUE; > + // > + // Check run in X64 or IA32 > + // > + if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { > + // > + // If X64, Page table Level must align with previous level. > + // > + Cr4.UintN =3D AsmReadCr4 (); > + Page5LevelSupport =3D Cr4.Bits.LA57 ? TRUE : FALSE; > + ASSERT (PcdGetBool (PcdUse5LevelPageTable) =3D=3D Page5LevelSupport)= ; > + } else { > + // > + // If IA32, Page table Level is decided by PCD and feature capbility= . > + // > + Page5LevelSupport =3D FALSE; > + if (PcdGetBool (PcdUse5LevelPageTable)) { > + AsmCpuidEx ( > + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, > + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, > + NULL, > + NULL, > + &EcxFlags.Uint32, > + NULL > + ); > + if (EcxFlags.Bits.FiveLevelPage !=3D 0) { > + Page5LevelSupport =3D TRUE; > + } > } > } >=20 > DEBUG ((DEBUG_INFO, "AddressBits=3D%u 5LevelPaging=3D%u 1GPage=3D%u\n"= , > PhysicalAddressBits, Page5LevelSupport, Page1GSupport)); >=20 > -- > 2.16.2.windows.1 >=20 >=20 >=20 >=20 >=20