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reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none) --_000_MN6PR11MB82449A0E04BC605E8B4A52238CE22MN6PR11MB8244namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni Thanks, Ray ________________________________ From: Tan, Dun Sent: Friday, May 10, 2024 18:08 To: devel@edk2.groups.io Cc: Ni, Ray ; Laszlo Ersek ; Kumar, Ra= hul R ; Gerd Hoffmann ; Wu, Jia= xin Subject: [PATCH 14/18] UefiCpuPkg: Remove code to set register table Remove code to set register table in CpuS3.c. In previous commit, PcdCpuFeaturesInitOnS3Resume has been set to TRUE. So that CpuFeaturesPei PEIM will initialize the CPU registers and perform CPU features initialization. Signed-off-by: Dun Tan Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Jiaxin Wu --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 423 ----------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= -------------- 1 file changed, 423 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index 7ac6b62676..9520451d92 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -91,425 +91,6 @@ UINT8 mApHltLoopCodeTemplate[] =3D { 0xEB, 0xFC // jmp $-2 }; -/** - Increment semaphore by 1. - - @param Sem IN: 32-bit unsigned integer - -**/ -VOID -S3ReleaseSemaphore ( - IN OUT volatile UINT32 *Sem - ) -{ - InterlockedIncrement (Sem); -} - -/** - Decrement the semaphore by 1 if it is not zero. - - Performs an atomic decrement operation for semaphore. - The compare exchange operation must be performed using - MP safe mechanisms. - - @param Sem IN: 32-bit unsigned integer - -**/ -VOID -S3WaitForSemaphore ( - IN OUT volatile UINT32 *Sem - ) -{ - UINT32 Value; - - do { - Value =3D *Sem; - } while (Value =3D=3D 0 || - InterlockedCompareExchange32 ( - Sem, - Value, - Value - 1 - ) !=3D Value); -} - -/** - Read / write CR value. - - @param[in] CrIndex The CR index which need to read/write. - @param[in] Read Read or write. TRUE is read. - @param[in,out] CrValue CR value. - - @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPO= RTED. -**/ -UINTN -ReadWriteCr ( - IN UINT32 CrIndex, - IN BOOLEAN Read, - IN OUT UINTN *CrValue - ) -{ - switch (CrIndex) { - case 0: - if (Read) { - *CrValue =3D AsmReadCr0 (); - } else { - AsmWriteCr0 (*CrValue); - } - - break; - case 2: - if (Read) { - *CrValue =3D AsmReadCr2 (); - } else { - AsmWriteCr2 (*CrValue); - } - - break; - case 3: - if (Read) { - *CrValue =3D AsmReadCr3 (); - } else { - AsmWriteCr3 (*CrValue); - } - - break; - case 4: - if (Read) { - *CrValue =3D AsmReadCr4 (); - } else { - AsmWriteCr4 (*CrValue); - } - - break; - default: - return EFI_UNSUPPORTED; - } - - return EFI_SUCCESS; -} - -/** - Initialize the CPU registers from a register table. - - @param[in] RegisterTable The register table for this AP. - @param[in] ApLocation AP location info for this ap. - @param[in] CpuStatus CPU status info for this CPU. - @param[in] CpuFlags Flags data structure used when program= the register. - - @note This service could be called by BSP/APs. -**/ -VOID -ProgramProcessorRegister ( - IN CPU_REGISTER_TABLE *RegisterTable, - IN EFI_CPU_PHYSICAL_LOCATION *ApLocation, - IN CPU_STATUS_INFORMATION *CpuStatus, - IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags - ) -{ - CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; - UINTN Index; - UINTN Value; - CPU_REGISTER_TABLE_ENTRY *RegisterTableEntryHead; - volatile UINT32 *SemaphorePtr; - UINT32 FirstThread; - UINT32 CurrentThread; - UINT32 CurrentCore; - UINTN ProcessorIndex; - UINT32 *ThreadCountPerPackage; - UINT8 *ThreadCountPerCore; - EFI_STATUS Status; - UINT64 CurrentValue; - - // - // Traverse Register Table of this logical processor - // - RegisterTableEntryHead =3D (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTa= ble->RegisterTableEntry; - - for (Index =3D 0; Index < RegisterTable->TableLength; Index++) { - RegisterTableEntry =3D &RegisterTableEntryHead[Index]; - - // - // Check the type of specified register - // - switch (RegisterTableEntry->RegisterType) { - // - // The specified register is Control Register - // - case ControlRegister: - Status =3D ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value); - if (EFI_ERROR (Status)) { - break; - } - - if (RegisterTableEntry->TestThenWrite) { - CurrentValue =3D BitFieldRead64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTab= leEntry->ValidBitLength - 1 - ); - if (CurrentValue =3D=3D RegisterTableEntry->Value) { - break; - } - } - - Value =3D (UINTN)BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTable= Entry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); - break; - // - // The specified register is Model Specific Register - // - case Msr: - if (RegisterTableEntry->TestThenWrite) { - Value =3D (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); - if (RegisterTableEntry->ValidBitLength >=3D 64) { - if (Value =3D=3D RegisterTableEntry->Value) { - break; - } - } else { - CurrentValue =3D BitFieldRead64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterT= ableEntry->ValidBitLength - 1 - ); - if (CurrentValue =3D=3D RegisterTableEntry->Value) { - break; - } - } - } - - // - // If this function is called to restore register setting after IN= IT signal, - // there is no need to restore MSRs in register table. - // - if (RegisterTableEntry->ValidBitLength >=3D 64) { - // - // If length is not less than 64 bits, then directly write witho= ut reading - // - AsmWriteMsr64 ( - RegisterTableEntry->Index, - RegisterTableEntry->Value - ); - } else { - // - // Set the bit section according to bit start and length - // - AsmMsrBitFieldWrite64 ( - RegisterTableEntry->Index, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidB= itLength - 1, - RegisterTableEntry->Value - ); - } - - break; - // - // MemoryMapped operations - // - case MemoryMapped: - AcquireSpinLock (&CpuFlags->MemoryMappedLock); - MmioBitFieldWrite32 ( - (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntr= y->HighIndex, 32)), - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBit= Length - 1, - (UINT32)RegisterTableEntry->Value - ); - ReleaseSpinLock (&CpuFlags->MemoryMappedLock); - break; - // - // Enable or disable cache - // - case CacheControl: - // - // If value of the entry is 0, then disable cache. Otherwise, ena= ble cache. - // - if (RegisterTableEntry->Value =3D=3D 0) { - AsmDisableCache (); - } else { - AsmEnableCache (); - } - - break; - - case Semaphore: - // Semaphore works logic like below: - // - // V(x) =3D LibReleaseSemaphore (Semaphore[FirstThread + x]); - // P(x) =3D LibWaitForSemaphore (Semaphore[FirstThread + x]); - // - // All threads (T0...Tn) waits in P() line and continues running - // together. - // - // - // T0 T1 ... Tn - // - // V(0...n) V(0...n) ... V(0...n) - // n * P(0) n * P(1) ... n * P(n) - // - ASSERT ( - (ApLocation !=3D NULL) && - (CpuStatus->ThreadCountPerPackage !=3D 0) && - (CpuStatus->ThreadCountPerCore !=3D 0) && - (CpuFlags->CoreSemaphoreCount !=3D NULL) && - (CpuFlags->PackageSemaphoreCount !=3D NULL) - ); - switch (RegisterTableEntry->Value) { - case CoreDepType: - SemaphorePtr =3D CpuFlags->CoreSemaphoreCount; - ThreadCountPerCore =3D (UINT8 *)(UINTN)CpuStatus->ThreadCountP= erCore; - - CurrentCore =3D ApLocation->Package * CpuStatus->MaxCoreCount = + ApLocation->Core; - // - // Get Offset info for the first thread in the core which curr= ent thread belongs to. - // - FirstThread =3D CurrentCore * CpuStatus->MaxThreadCount; - CurrentThread =3D FirstThread + ApLocation->Thread; - - // - // Different cores may have different valid threads in them. I= f driver maintail clearly - // thread index in different cores, the logic will be much com= plicated. - // Here driver just simply records the max thread number in al= l cores and use it as expect - // thread number for all cores. - // In below two steps logic, first current thread will Release= semaphore for each thread - // in current core. Maybe some threads are not valid in this c= ore, but driver don't - // care. Second, driver will let current thread wait semaphore= for all valid threads in - // current core. Because only the valid threads will do releas= e semaphore for this - // thread, driver here only need to wait the valid thread coun= t. - // - - // - // First Notify ALL THREADs in current Core that this thread i= s ready. - // - for (ProcessorIndex =3D 0; ProcessorIndex < CpuStatus->MaxThre= adCount; ProcessorIndex++) { - S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorInd= ex]); - } - - // - // Second, check whether all VALID THREADs (not all threads) i= n current core are ready. - // - for (ProcessorIndex =3D 0; ProcessorIndex < ThreadCountPerCore= [CurrentCore]; ProcessorIndex++) { - S3WaitForSemaphore (&SemaphorePtr[CurrentThread]); - } - - break; - - case PackageDepType: - SemaphorePtr =3D CpuFlags->PackageSemaphoreCount; - ThreadCountPerPackage =3D (UINT32 *)(UINTN)CpuStatus->ThreadCo= untPerPackage; - // - // Get Offset info for the first thread in the package which c= urrent thread belongs to. - // - FirstThread =3D ApLocation->Package * CpuStatus->MaxCoreCount = * CpuStatus->MaxThreadCount; - // - // Get the possible threads count for current package. - // - CurrentThread =3D FirstThread + CpuStatus->MaxThreadCount * Ap= Location->Core + ApLocation->Thread; - - // - // Different packages may have different valid threads in them= . If driver maintail clearly - // thread index in different packages, the logic will be much = complicated. - // Here driver just simply records the max thread number in al= l packages and use it as expect - // thread number for all packages. - // In below two steps logic, first current thread will Release= semaphore for each thread - // in current package. Maybe some threads are not valid in thi= s package, but driver don't - // care. Second, driver will let current thread wait semaphore= for all valid threads in - // current package. Because only the valid threads will do rel= ease semaphore for this - // thread, driver here only need to wait the valid thread coun= t. - // - - // - // First Notify ALL THREADS in current package that this threa= d is ready. - // - for (ProcessorIndex =3D 0; ProcessorIndex < CpuStatus->MaxThre= adCount * CpuStatus->MaxCoreCount; ProcessorIndex++) { - S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorInd= ex]); - } - - // - // Second, check whether VALID THREADS (not all threads) in cu= rrent package are ready. - // - for (ProcessorIndex =3D 0; ProcessorIndex < ThreadCountPerPack= age[ApLocation->Package]; ProcessorIndex++) { - S3WaitForSemaphore (&SemaphorePtr[CurrentThread]); - } - - break; - - default: - break; - } - - break; - - default: - break; - } - } -} - -/** - - Set Processor register for one AP. - - @param PreSmmRegisterTable Use pre Smm register table or registe= r table. - -**/ -VOID -SetRegister ( - IN BOOLEAN PreSmmRegisterTable - ) -{ - CPU_FEATURE_INIT_DATA *FeatureInitData; - CPU_REGISTER_TABLE *RegisterTable; - CPU_REGISTER_TABLE *RegisterTables; - UINT32 InitApicId; - UINTN ProcIndex; - UINTN Index; - - FeatureInitData =3D &mAcpiCpuData.CpuFeatureInitData; - - if (PreSmmRegisterTable) { - RegisterTables =3D (CPU_REGISTER_TABLE *)(UINTN)FeatureInitData->PreSm= mInitRegisterTable; - } else { - RegisterTables =3D (CPU_REGISTER_TABLE *)(UINTN)FeatureInitData->Regis= terTable; - } - - if (RegisterTables =3D=3D NULL) { - return; - } - - InitApicId =3D GetInitialApicId (); - RegisterTable =3D NULL; - ProcIndex =3D (UINTN)-1; - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTables[Index].InitialApicId =3D=3D InitApicId) { - RegisterTable =3D &RegisterTables[Index]; - ProcIndex =3D Index; - break; - } - } - - ASSERT (RegisterTable !=3D NULL); - - if (FeatureInitData->ApLocation !=3D 0) { - ProgramProcessorRegister ( - RegisterTable, - (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)FeatureInitData->ApLocation + Pr= ocIndex, - &FeatureInitData->CpuStatus, - &mCpuFlags - ); - } else { - ProgramProcessorRegister ( - RegisterTable, - NULL, - &FeatureInitData->CpuStatus, - &mCpuFlags - ); - } -} - /** The function is invoked before SMBASE relocation in S3 path to restores = CPU status. @@ -524,8 +105,6 @@ InitializeCpuBeforeRebase ( IN BOOLEAN IsBsp ) { - SetRegister (TRUE); - ProgramVirtualWireMode (); if (!IsBsp) { DisableLvtInterrupts (); @@ -563,8 +142,6 @@ InitializeCpuAfterRebase ( UINTN TopOfStack; UINT8 Stack[128]; - SetRegister (FALSE); - if (mSmmS3ResumeState->MpService2Ppi =3D=3D 0) { if (IsBsp) { while (mNumberToFinish > 0) { -- 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#118845): https://edk2.groups.io/g/devel/message/118845 Mute This Topic: https://groups.io/mt/106018140/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_MN6PR11MB82449A0E04BC605E8B4A52238CE22MN6PR11MB8244namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Reviewed-by: Ray Ni <ray.ni@intel.com>

Thanks,
Ray
From: Tan, Dun <dun.tan@= intel.com>
Sent: Friday, May 10, 2024 18:08
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Ni, Ray <ray.ni@intel.com>; Laszlo Ersek <lersek@redhat= .com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; Gerd Hoffmann <= ;kraxel@redhat.com>; Wu, Jiaxin <jiaxin.wu@intel.com>
Subject: [PATCH 14/18] UefiCpuPkg: Remove code to set register table=
 
Remove code to set register table in CpuS3.c.
In previous commit, PcdCpuFeaturesInitOnS3Resume
has been set to TRUE. So that CpuFeaturesPei PEIM
will initialize the CPU registers and perform CPU
features initialization.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 423 -----------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= -------------------
 1 file changed, 423 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c
index 7ac6b62676..9520451d92 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -91,425 +91,6 @@ UINT8  mApHltLoopCodeTemplate[] =3D {
   0xEB, 0xFC        &nbs= p;     // jmp $-2
 };
 
-/**
-  Increment semaphore by 1.
-
-  @param      Sem    &nb= sp;       IN:  32-bit unsigned integer -
-**/
-VOID
-S3ReleaseSemaphore (
-  IN OUT  volatile UINT32  *Sem
-  )
-{
-  InterlockedIncrement (Sem);
-}
-
-/**
-  Decrement the semaphore by 1 if it is not zero.
-
-  Performs an atomic decrement operation for semaphore.
-  The compare exchange operation must be performed using
-  MP safe mechanisms.
-
-  @param      Sem    &nb= sp;       IN:  32-bit unsigned integer -
-**/
-VOID
-S3WaitForSemaphore (
-  IN OUT  volatile UINT32  *Sem
-  )
-{
-  UINT32  Value;
-
-  do {
-    Value =3D *Sem;
-  } while (Value =3D=3D 0 ||
-           InterlockedCo= mpareExchange32 (
-             S= em,
-             V= alue,
-             V= alue - 1
-             )= !=3D Value);
-}
-
-/**
-  Read / write CR value.
-
-  @param[in]      CrIndex   &= nbsp;     The CR index which need to read/write.
-  @param[in]      Read   &nbs= p;        Read or write. TRUE is read. -  @param[in,out]  CrValue      &nb= sp;  CR value.
-
-  @retval    EFI_SUCCESS means read/write success, els= e return EFI_UNSUPPORTED.
-**/
-UINTN
-ReadWriteCr (
-  IN     UINT32   CrIndex,
-  IN     BOOLEAN  Read,
-  IN OUT UINTN    *CrValue
-  )
-{
-  switch (CrIndex) {
-    case 0:
-      if (Read) {
-        *CrValue =3D AsmReadCr0 ();
-      } else {
-        AsmWriteCr0 (*CrValue);
-      }
-
-      break;
-    case 2:
-      if (Read) {
-        *CrValue =3D AsmReadCr2 ();
-      } else {
-        AsmWriteCr2 (*CrValue);
-      }
-
-      break;
-    case 3:
-      if (Read) {
-        *CrValue =3D AsmReadCr3 ();
-      } else {
-        AsmWriteCr3 (*CrValue);
-      }
-
-      break;
-    case 4:
-      if (Read) {
-        *CrValue =3D AsmReadCr4 ();
-      } else {
-        AsmWriteCr4 (*CrValue);
-      }
-
-      break;
-    default:
-      return EFI_UNSUPPORTED;
-  }
-
-  return EFI_SUCCESS;
-}
-
-/**
-  Initialize the CPU registers from a register table.
-
-  @param[in]  RegisterTable      &= nbsp;  The register table for this AP.
-  @param[in]  ApLocation      &nbs= p;     AP location info for this ap.
-  @param[in]  CpuStatus       = ;      CPU status info for this CPU.
-  @param[in]  CpuFlags       =        Flags data structure used when program= the register.
-
-  @note This service could be called by BSP/APs.
-**/
-VOID
-ProgramProcessorRegister (
-  IN CPU_REGISTER_TABLE       &nbs= p;  *RegisterTable,
-  IN EFI_CPU_PHYSICAL_LOCATION   *ApLocation,
-  IN CPU_STATUS_INFORMATION      *CpuStatus,=
-  IN PROGRAM_CPU_REGISTER_FLAGS  *CpuFlags
-  )
-{
-  CPU_REGISTER_TABLE_ENTRY  *RegisterTableEntry;
-  UINTN          &n= bsp;          Index;
-  UINTN          &n= bsp;          Value;
-  CPU_REGISTER_TABLE_ENTRY  *RegisterTableEntryHead;
-  volatile UINT32        &nbs= p;  *SemaphorePtr;
-  UINT32          &= nbsp;         FirstThread;
-  UINT32          &= nbsp;         CurrentThread;
-  UINT32          &= nbsp;         CurrentCore;
-  UINTN          &n= bsp;          ProcessorIndex;<= br> -  UINT32          &= nbsp;         *ThreadCountPerPackag= e;
-  UINT8          &n= bsp;          *ThreadCountPerC= ore;
-  EFI_STATUS         &nb= sp;      Status;
-  UINT64          &= nbsp;         CurrentValue;
-
-  //
-  // Traverse Register Table of this logical processor
-  //
-  RegisterTableEntryHead =3D (CPU_REGISTER_TABLE_ENTRY *)(UINTN)Regis= terTable->RegisterTableEntry;
-
-  for (Index =3D 0; Index < RegisterTable->TableLength; Index++= ) {
-    RegisterTableEntry =3D &RegisterTableEntryHead[Inde= x];
-
-    //
-    // Check the type of specified register
-    //
-    switch (RegisterTableEntry->RegisterType) {
-      //
-      // The specified register is Control Regist= er
-      //
-      case ControlRegister:
-        Status =3D ReadWriteCr (Registe= rTableEntry->Index, TRUE, &Value);
-        if (EFI_ERROR (Status)) {
-          break;
-        }
-
-        if (RegisterTableEntry->Test= ThenWrite) {
-          CurrentValue =3D Bi= tFieldRead64 (
-            &n= bsp;            = ;  Value,
-            &n= bsp;            = ;  RegisterTableEntry->ValidBitStart,
-            &n= bsp;            = ;  RegisterTableEntry->ValidBitStart + RegisterTableEntry->Valid= BitLength - 1
-            &n= bsp;            = ;  );
-          if (CurrentValue = =3D=3D RegisterTableEntry->Value) {
-            break;<= br> -          }
-        }
-
-        Value =3D (UINTN)BitFieldWrite6= 4 (
-            &n= bsp;            Valu= e,
-            &n= bsp;            Regi= sterTableEntry->ValidBitStart,
-            &n= bsp;            Regi= sterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - = 1,
-            &n= bsp;            Regi= sterTableEntry->Value
-            &n= bsp;            ); -        ReadWriteCr (RegisterTableEntry= ->Index, FALSE, &Value);
-        break;
-      //
-      // The specified register is Model Specific= Register
-      //
-      case Msr:
-        if (RegisterTableEntry->Test= ThenWrite) {
-          Value =3D (UINTN)As= mReadMsr64 (RegisterTableEntry->Index);
-          if (RegisterTableEn= try->ValidBitLength >=3D 64) {
-            if (Val= ue =3D=3D RegisterTableEntry->Value) {
-            &n= bsp; break;
-            }
-          } else {
-            Current= Value =3D BitFieldRead64 (
-            &n= bsp;            = ;    Value,
-            &n= bsp;            = ;    RegisterTableEntry->ValidBitStart,
-            &n= bsp;            = ;    RegisterTableEntry->ValidBitStart + RegisterTableEnt= ry->ValidBitLength - 1
-            &n= bsp;            = ;    );
-            if (Cur= rentValue =3D=3D RegisterTableEntry->Value) {
-            &n= bsp; break;
-            }
-          }
-        }
-
-        //
-        // If this function is called t= o restore register setting after INIT signal,
-        // there is no need to restore = MSRs in register table.
-        //
-        if (RegisterTableEntry->Vali= dBitLength >=3D 64) {
-          //
-          // If length is not= less than 64 bits, then directly write without reading
-          //
-          AsmWriteMsr64 (
-            Registe= rTableEntry->Index,
-            Registe= rTableEntry->Value
-            );
-        } else {
-          //
-          // Set the bit sect= ion according to bit start and length
-          //
-          AsmMsrBitFieldWrite= 64 (
-            Registe= rTableEntry->Index,
-            Registe= rTableEntry->ValidBitStart,
-            Registe= rTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,<= br> -            Registe= rTableEntry->Value
-            );
-        }
-
-        break;
-      //
-      // MemoryMapped operations
-      //
-      case MemoryMapped:
-        AcquireSpinLock (&CpuFlags-= >MemoryMappedLock);
-        MmioBitFieldWrite32 (
-          (UINTN)(RegisterTab= leEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),
-          RegisterTableEntry-= >ValidBitStart,
-          RegisterTableEntry-= >ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
-          (UINT32)RegisterTab= leEntry->Value
-          );
-        ReleaseSpinLock (&CpuFlags-= >MemoryMappedLock);
-        break;
-      //
-      // Enable or disable cache
-      //
-      case CacheControl:
-        //
-        // If value of the entry is 0, = then disable cache.  Otherwise, enable cache.
-        //
-        if (RegisterTableEntry->Valu= e =3D=3D 0) {
-          AsmDisableCache ();=
-        } else {
-          AsmEnableCache ();<= br> -        }
-
-        break;
-
-      case Semaphore:
-        // Semaphore works logic like b= elow:
-        //
-        //  V(x) =3D LibReleaseSem= aphore (Semaphore[FirstThread + x]);
-        //  P(x) =3D LibWaitForSem= aphore (Semaphore[FirstThread + x]);
-        //
-        //  All threads (T0...Tn) = waits in P() line and continues running
-        //  together.
-        //
-        //
-        //  T0   &n= bsp;         T1   &n= bsp;        ...    &= nbsp;      Tn
-        //
-        //  V(0...n)  &n= bsp;    V(0...n)      ... &nbs= p;         V(0...n)
-        //  n * P(0)  &n= bsp;    n * P(1)      ... &nbs= p;         n * P(n)
-        //
-        ASSERT (
-          (ApLocation !=3D NU= LL) &&
-          (CpuStatus->Thre= adCountPerPackage !=3D 0) &&
-          (CpuStatus->Thre= adCountPerCore !=3D 0) &&
-          (CpuFlags->CoreS= emaphoreCount !=3D NULL) &&
-          (CpuFlags->Packa= geSemaphoreCount !=3D NULL)
-          );
-        switch (RegisterTableEntry->= Value) {
-          case CoreDepType: -            Semapho= rePtr       =3D CpuFlags->CoreSemaphoreCou= nt;
-            ThreadC= ountPerCore =3D (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore;
-
-            Current= Core =3D ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation-&= gt;Core;
-            //
-            // Get = Offset info for the first thread in the core which current thread belongs t= o.
-            //
-            FirstTh= read   =3D CurrentCore * CpuStatus->MaxThreadCount;
-            Current= Thread =3D FirstThread + ApLocation->Thread;
-
-            //
-            // Diff= erent cores may have different valid threads in them. If driver maintail cl= early
-            // thre= ad index in different cores, the logic will be much complicated.
-            // Here= driver just simply records the max thread number in all cores and use it a= s expect
-            // thre= ad number for all cores.
-            // In b= elow two steps logic, first current thread will Release semaphore for each = thread
-            // in c= urrent core. Maybe some threads are not valid in this core, but driver don'= t
-            // care= . Second, driver will let current thread wait semaphore for all valid threa= ds in
-            // curr= ent core. Because only the valid threads will do release semaphore for this=
-            // thre= ad, driver here only need to wait the valid thread count.
-            //
-
-            //
-            // Firs= t Notify ALL THREADs in current Core that this thread is ready.
-            //
-            for (Pr= ocessorIndex =3D 0; ProcessorIndex < CpuStatus->MaxThreadCount; Proce= ssorIndex++) {
-            &n= bsp; S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);<= br> -            }
-
-            //
-            // Seco= nd, check whether all VALID THREADs (not all threads) in current core are r= eady.
-            //
-            for (Pr= ocessorIndex =3D 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; Pr= ocessorIndex++) {
-            &n= bsp; S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
-            }
-
-            break;<= br> -
-          case PackageDepType= :
-            Semapho= rePtr          =3D CpuFlags-&g= t;PackageSemaphoreCount;
-            ThreadC= ountPerPackage =3D (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage; -            //
-            // Get = Offset info for the first thread in the package which current thread belong= s to.
-            //
-            FirstTh= read =3D ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus-&g= t;MaxThreadCount;
-            //
-            // Get = the possible threads count for current package.
-            //
-            Current= Thread =3D FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core= + ApLocation->Thread;
-
-            //
-            // Diff= erent packages may have different valid threads in them. If driver maintail= clearly
-            // thre= ad index in different packages, the logic will be much complicated.
-            // Here= driver just simply records the max thread number in all packages and use i= t as expect
-            // thre= ad number for all packages.
-            // In b= elow two steps logic, first current thread will Release semaphore for each = thread
-            // in c= urrent package. Maybe some threads are not valid in this package, but drive= r don't
-            // care= . Second, driver will let current thread wait semaphore for all valid threa= ds in
-            // curr= ent package. Because only the valid threads will do release semaphore for t= his
-            // thre= ad, driver here only need to wait the valid thread count.
-            //
-
-            //
-            // Firs= t Notify ALL THREADS in current package that this thread is ready.
-            //
-            for (Pr= ocessorIndex =3D 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuS= tatus->MaxCoreCount; ProcessorIndex++) {
-            &n= bsp; S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);<= br> -            }
-
-            //
-            // Seco= nd, check whether VALID THREADS (not all threads) in current package are re= ady.
-            //
-            for (Pr= ocessorIndex =3D 0; ProcessorIndex < ThreadCountPerPackage[ApLocation-&g= t;Package]; ProcessorIndex++) {
-            &n= bsp; S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
-            }
-
-            break;<= br> -
-          default:
-            break;<= br> -        }
-
-        break;
-
-      default:
-        break;
-    }
-  }
-}
-
-/**
-
-  Set Processor register for one AP.
-
-  @param     PreSmmRegisterTable   = ;  Use pre Smm register table or register table.
-
-**/
-VOID
-SetRegister (
-  IN BOOLEAN  PreSmmRegisterTable
-  )
-{
-  CPU_FEATURE_INIT_DATA  *FeatureInitData;
-  CPU_REGISTER_TABLE     *RegisterTable;
-  CPU_REGISTER_TABLE     *RegisterTables;
-  UINT32          &= nbsp;      InitApicId;
-  UINTN          &n= bsp;       ProcIndex;
-  UINTN          &n= bsp;       Index;
-
-  FeatureInitData =3D &mAcpiCpuData.CpuFeatureInitData;
-
-  if (PreSmmRegisterTable) {
-    RegisterTables =3D (CPU_REGISTER_TABLE *)(UINTN)Feature= InitData->PreSmmInitRegisterTable;
-  } else {
-    RegisterTables =3D (CPU_REGISTER_TABLE *)(UINTN)Feature= InitData->RegisterTable;
-  }
-
-  if (RegisterTables =3D=3D NULL) {
-    return;
-  }
-
-  InitApicId    =3D GetInitialApicId ();
-  RegisterTable =3D NULL;
-  ProcIndex     =3D (UINTN)-1;
-  for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {<= br> -    if (RegisterTables[Index].InitialApicId =3D=3D InitApic= Id) {
-      RegisterTable =3D &RegisterTables[Index= ];
-      ProcIndex     =3D Index= ;
-      break;
-    }
-  }
-
-  ASSERT (RegisterTable !=3D NULL);
-
-  if (FeatureInitData->ApLocation !=3D 0) {
-    ProgramProcessorRegister (
-      RegisterTable,
-      (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)Feature= InitData->ApLocation + ProcIndex,
-      &FeatureInitData->CpuStatus,
-      &mCpuFlags
-      );
-  } else {
-    ProgramProcessorRegister (
-      RegisterTable,
-      NULL,
-      &FeatureInitData->CpuStatus,
-      &mCpuFlags
-      );
-  }
-}
-
 /**
   The function is invoked before SMBASE relocation in S3 path to= restores CPU status.
 
@@ -524,8 +105,6 @@ InitializeCpuBeforeRebase (
   IN BOOLEAN  IsBsp
   )
 {
-  SetRegister (TRUE);
-
   ProgramVirtualWireMode ();
   if (!IsBsp) {
     DisableLvtInterrupts ();
@@ -563,8 +142,6 @@ InitializeCpuAfterRebase (
   UINTN  TopOfStack;
   UINT8  Stack[128];
 
-  SetRegister (FALSE);
-
   if (mSmmS3ResumeState->MpService2Ppi =3D=3D 0) {
     if (IsBsp) {
       while (mNumberToFinish > 0) {
--
2.31.1.windows.1

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