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Thu, 11 Apr 2024 03:19:58 +0000 From: "Ni, Ray" To: "Wu, Jiaxin" , "devel@edk2.groups.io" CC: "Zeng, Star" , Ard Biesheuvel , "Yao, Jiewen" , "Gerd Hoffmann" , "Kumar, Rahul R" Subject: Re: [edk2-devel] [PATCH v1 03/13] UefiCpuPkg/SmmRelocationLib: Add library instance for OVMF Thread-Topic: [PATCH v1 03/13] UefiCpuPkg/SmmRelocationLib: Add library instance for OVMF Thread-Index: AQHai08RFIlHXkFAQ0+HiVjxVR3nL7FiZ3BO Date: Thu, 11 Apr 2024 03:19:58 +0000 Message-ID: References: <20240410135724.15344-1-jiaxin.wu@intel.com> <20240410135724.15344-4-jiaxin.wu@intel.com> In-Reply-To: <20240410135724.15344-4-jiaxin.wu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MN6PR11MB8244:EE_|IA1PR11MB6444:EE_ x-ms-office365-filtering-correlation-id: d25dae46-16d8-4ed1-ffc2-08dc59d64474 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: URcrVyiu+6Ijk/4Z5h8sNl5MBGXlXXozB5PyTUUdHiutbQdob+s94mbSOvQa3iiO3mxe/RBUveR5+ayVbHey38n9uCJdxrx75+BnO3nBqbetvqyhrCljUbnPKOGQNNJMhCUpP96K2DjhOflD0SHwwmpMdygbvzDIW5EuFvFJDR7D4+yFMPIKsNFVF0i+d1foVQq+LkQ1uXFeUqVZr58FfA3wSgQLQBAdDULzoYCpwqWKbsvdUfWleK7EJGVFaokb+J9PQ4xMzrCRLILE67Z5BNs9T6mEjkxc9n10CSoS2Y4wok+HQvUFw3YuUns9myx8TAjs2Au0mBIvVsdM11kdOgF8cr2QNgpHD4c2IdLJdyaEvPHdPZuH4Qy62DVCAOkiB/XrkPG50dvyVmBNRWagnmdhpK3WcX67T91ZghZyeEy7Q7Tifo6XbXnpKavdsVaIBWJsn7ZychYEOrFmRmkv30BXGZpv7g0fxp+w8UU3SiMEYBdosPimbAxU+J7GZfuP/rmNnBXnfvpLewsyIwkz7ajK3Kp5iBF8tCIGtf0zjUf+K9o6I5M4zHTFVG5K1WYNgvyq0VA7KAX/FvxYyvGnHEEULzyMhk42lfdSMpPe2KPCVAU0AOKCmC7kiSMhP9EMBGVUE6uufCW9lL/61PzBUTs2cAM8DgN6JZfE9t+Hsb94p4ggtAXx27O7OC/J21+Gp45TkQ9NivHkth/ncRk7HY9M2JsawIvzCAckl9BgZvs= x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?0cr2Vrez++w5jF1vS2IyjRvoNei0f0cpfPF1xvI/KPWo9lB13+d6xN9h8bXt?= =?us-ascii?Q?X48qq63QKl9Wagii8diVhTJInXCHn5aG0trWUVJDyVPkx0B+sQTYL94X22pT?= =?us-ascii?Q?eHcsZvB2l1LDqs8zlmvNtJ0zz6iWE76EbJEPZZNQNvOD3RyltSh/DbM2+Ssj?= =?us-ascii?Q?2Re82g8xg6Sl5d2TtUm/VDUKOvs4EGLk0Hbf25Fx7e7ng/70hhXgXXj33rM4?= =?us-ascii?Q?VEMh9QBm+PMlj5Uye8TBgX4aGNa7hN3kSCdtitoT5XYn5PDDF/03N3u0R/Nt?= =?us-ascii?Q?MV0KCUJyfzrxNIpn79TucipPbaZiJaTUzlaGS5nx9HFXAmxEjk1apzyH3m1V?= =?us-ascii?Q?JcPIG6XEImsGgDh5c3lmxBmfvASu4A4TisB+m3q3ymvDQyQDSHzdv/eU+A0D?= =?us-ascii?Q?CWohtJOF795Zkv4fDywml9ALBDM6OapE1BsY0YitAMmAaHRcbFP9OxI5ENU/?= =?us-ascii?Q?nxpNPesJDuBmH2UgmBf8N6oOv1BZFLabBXn5tZBN5sgguo3dIw6kxU6jqtZJ?= =?us-ascii?Q?Z+KsqAvz8L1VhrgnLfBfUqGx6mvQ9y2wk6rOoybiwHMOVPMOx5c6Y7tircaO?= =?us-ascii?Q?lWBSsKRYQm6mFwNkbCz6j/Eo+aektWHUke9rLE2Zci4M4PsIbb2v3s6dPEQa?= =?us-ascii?Q?4EV/9jL5rZYrkA/UMUWCAS9WQ73Bw387U3+I6dFhf6BmLImgq66oZWG+qIvj?= =?us-ascii?Q?vPYDLOOYyz7e2iQNspPVGWEFj/Er0/iBhOUcSNXYZdz15ZAwUXfsSHylClVE?= =?us-ascii?Q?7y/XwTPw0TukpgzarTtb1mFp4ynu9IE6Bl0VksBUNOu3IZQGFZXQIJNwGBob?= =?us-ascii?Q?npiLXYlvWSrx0Px4BJvqE+4NAHmeIVjzy4yO1Vdb2dHHUTKn6tQPkCHmI/SR?= =?us-ascii?Q?9mMxRHe57DrmGHRfd00VgMm327A5a4mOocKKXG/8C6wxfsaGqeRYOqt8BOSi?= =?us-ascii?Q?4Cgmmmstik9BiJzW7SqbDBzCU64M0Jx2hGyVkJq5UdtsQec6b95Uwe0X7OVr?= =?us-ascii?Q?6HgAl0GFspt/A4D3LTYoB2mMfNLC3w0QUQBLWBDgFLBdkheZaRfZuuQ4ubmM?= =?us-ascii?Q?giSUhD54Lokef4XOIniXcS6P8jji6Yufi6e7cc8NBsLexT2ibH+e5MZ9bxEz?= =?us-ascii?Q?Acr+RzI4M9VXYYTTO1QNaCQ3n68AkVM8Lg6V/2N9S1RQxUF/YJhICEguTERG?= =?us-ascii?Q?z3kXWj5DHCNsFL57C/eusJbkKYJTWAIfMD2DZoRkqqHx4wZfPtBaFQhWSjDG?= =?us-ascii?Q?lK4uO4UfW+abYJ7K1VhHmaWavtv+n+IU9dVu5zcR3Ezs8qNGmbCrOquy6yNm?= =?us-ascii?Q?QzHnITD5aoFgghQgEWdmiuCwr2EnHqVuifmBhcSAUeFgXDROJxcnk+RiYyRv?= =?us-ascii?Q?ciPbEUwpEQ2me0bw6cTQpeR8fVXzMYy8bzRnU/9T7bCPh335MjHP6j9JiAI0?= =?us-ascii?Q?2V/YkgyrhyC/lyoVE1jCpMgl1N310l34NQo2m3bgJWS1u4y7PV5JIPcAo/iN?= =?us-ascii?Q?nV8QKb04E8MIDSmkjZVnAwOKS4KtiynvLjr1vEJ7B0zm5Yh/Ay7kwNPe1dyn?= =?us-ascii?Q?c5keO3x1SUuL4LRAw0s=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN6PR11MB8244.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d25dae46-16d8-4ed1-ffc2-08dc59d64474 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Apr 2024 03:19:58.5959 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: FYjDK+Ukmry4+KDoLIlzmDCuO8ylYAHz4VBjWf+EfPZ0WsfzOYbq057NCgbzmeGBoAuNgkq5z2EYr7m37hUPgA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR11MB6444 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 10 Apr 2024 20:20:02 -0700 Resent-From: ray.ni@intel.com Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Phy8kZIZmSAWPytdj2KNQDTOx7686176AA= Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN6PR11MB8244A3344B7E69AF92C299FF8C052MN6PR11MB8244namp_" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=tEihbl5g; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.227.220 as permitted sender) smtp.mailfrom=bounce@groups.io --_000_MN6PR11MB8244A3344B7E69AF92C299FF8C052MN6PR11MB8244namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable No. Please do not create a OVMF specific lib instance in UefiCpuPkg. Thanks, Ray ________________________________ From: Wu, Jiaxin Sent: Wednesday, April 10, 2024 21:57 To: devel@edk2.groups.io Cc: Ni, Ray ; Zeng, Star ; Ard Biesh= euvel ; Yao, Jiewen ; Gerd= Hoffmann ; Kumar, Rahul R Subject: [PATCH v1 03/13] UefiCpuPkg/SmmRelocationLib: Add library instance= for OVMF Due to the definition difference of SMRAM Save State, SmmBase config in SMRAM Save State for OVMF is also different. This patch provides the OvmfSmmRelocationLib library instance to handle the SMRAM Save State difference. Cc: Ray Ni Cc: Zeng Star Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- .../SmmRelocationLib/OvmfSmmRelocationLib.inf | 61 ++++++++++++ .../SmmRelocationLib/OvmfSmramSaveStateConfig.c | 107 +++++++++++++++++= ++++ 2 files changed, 168 insertions(+) create mode 100644 UefiCpuPkg/Library/SmmRelocationLib/OvmfSmmRelocationLi= b.inf create mode 100644 UefiCpuPkg/Library/SmmRelocationLib/OvmfSmramSaveStateC= onfig.c diff --git a/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmmRelocationLib.inf b= /UefiCpuPkg/Library/SmmRelocationLib/OvmfSmmRelocationLib.inf new file mode 100644 index 0000000000..eba1129ac2 --- /dev/null +++ b/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmmRelocationLib.inf @@ -0,0 +1,61 @@ +## @file +# SMM Relocation Lib for each processor. +# +# This Lib produces the SMM_BASE_HOB in HOB database which tells +# the PiSmmCpuDxeSmm driver (runs at a later phase) about the new +# SMBASE for each processor. PiSmmCpuDxeSmm driver installs the +# SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for processor +# Index. +# +# Copyright (c) 2024, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SmmRelocationLib + FILE_GUID =3D 51834F51-CCE0-4743-B553-935D0C8A53FF + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SmmRelocationLib + +[Sources] + InternalSmmRelocationLib.h + OvmfSmramSaveStateConfig.c + SmmRelocationLib.c + +[Sources.Ia32] + Ia32/Semaphore.c + Ia32/SmmInit.nasm + +[Sources.X64] + X64/Semaphore.c + X64/SmmInit.nasm + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + CpuExceptionHandlerLib + DebugLib + HobLib + LocalApicLib + MemoryAllocationLib + PcdLib + PeiServicesLib + +[Guids] + gSmmBaseHobGuid ## HOB ALWAYS_PRODUCED + gEfiSmmSmramMemoryGuid ## CONSUMES + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize ## CONS= UMES + +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport ##= CONSUMES diff --git a/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmramSaveStateConfig.c= b/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmramSaveStateConfig.c new file mode 100644 index 0000000000..505b1d694a --- /dev/null +++ b/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmramSaveStateConfig.c @@ -0,0 +1,107 @@ +/** @file + Config SMRAM Save State for SmmBases Relocation. + + Copyright (c) 2024, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include "InternalSmmRelocationLib.h" +#include + +/** + This function configures the SmBase on the currently executing CPU. + + @param[in] CpuIndex The index of the CPU. + @param[in,out] CpuState Pointer to SMRAM Save State Map for = the + currently executing CPU. On out, SmB= ase is + updated to the new value. + +**/ +VOID +EFIAPI +ConfigureSmBase ( + IN UINTN CpuIndex, + IN OUT SMRAM_SAVE_STATE_MAP *CpuState + ) +{ + AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState; + + CpuSaveState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; + + if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { + CpuSaveState->x86.SMBASE =3D (UINT32)mSmBaseForAllCpus[CpuIndex]; + } else { + CpuSaveState->x64.SMBASE =3D (UINT32)mSmBaseForAllCpus[CpuIndex]; + } +} + +/** + This function updates the SMRAM save state on the currently executing CP= U + to resume execution at a specific address after an RSM instruction. Thi= s + function must evaluate the SMRAM save state to determine the execution m= ode + the RSM instruction resumes and update the resume execution address with + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT re= start + flag in the SMRAM save state must always be cleared. This function retu= rns + the value of the instruction pointer from the SMRAM save state that was + replaced. If this function returns 0, then the SMRAM save state was not + modified. + + This function is called during the very first SMI on each CPU after + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mo= de + to signal that the SMBASE of each CPU has been updated before the defaul= t + SMBASE address is used for the first SMI to the next CPU. + + @param[in] CpuIndex The processor index for the curr= ently + executing CPU. + @param[in,out] CpuState Pointer to SMRAM Save State Map = for the + currently executing CPU. + @param[in] NewInstructionPointer32 Instruction pointer to use if re= suming to + 32-bit mode from 64-bit SMM. + @param[in] NewInstructionPointer Instruction pointer to use if re= suming to + same mode as SMM. + + @retval The value of the original instruction pointer before it was hook= ed. + +**/ +UINT64 +EFIAPI +HookReturnFromSmm ( + IN UINTN CpuIndex, + IN OUT SMRAM_SAVE_STATE_MAP *CpuState, + IN UINT64 NewInstructionPointer32, + IN UINT64 NewInstructionPointer + ) +{ + UINT64 OriginalInstructionPointer; + AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState; + + CpuSaveState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; + if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { + OriginalInstructionPointer =3D (UINT64)CpuSaveState->x86._EIP; + CpuSaveState->x86._EIP =3D (UINT32)NewInstructionPointer; + // + // Clear the auto HALT restart flag so the RSM instruction returns + // program control to the instruction following the HLT instruction. + // + if ((CpuSaveState->x86.AutoHALTRestart & BIT0) !=3D 0) { + CpuSaveState->x86.AutoHALTRestart &=3D ~BIT0; + } + } else { + OriginalInstructionPointer =3D CpuSaveState->x64._RIP; + if ((CpuSaveState->x64.EFER & LMA) =3D=3D 0) { + CpuSaveState->x64._RIP =3D (UINT32)NewInstructionPointer32; + } else { + CpuSaveState->x64._RIP =3D (UINT32)NewInstructionPointer; + } + + // + // Clear the auto HALT restart flag so the RSM instruction returns + // program control to the instruction following the HLT instruction. + // + if ((CpuSaveState->x64.AutoHALTRestart & BIT0) !=3D 0) { + CpuSaveState->x64.AutoHALTRestart &=3D ~BIT0; + } + } + + return OriginalInstructionPointer; +} -- 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117611): https://edk2.groups.io/g/devel/message/117611 Mute This Topic: https://groups.io/mt/105441992/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_MN6PR11MB8244A3344B7E69AF92C299FF8C052MN6PR11MB8244namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
No. Please do not create a OVMF specific lib instance in UefiCpuPkg.


Thanks,
Ray
From: Wu, Jiaxin <jiaxin= .wu@intel.com>
Sent: Wednesday, April 10, 2024 21:57
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Ni, Ray <ray.ni@intel.com>; Zeng, Star <star.zeng@intel= .com>; Ard Biesheuvel <ardb+tianocore@kernel.org>; Yao, Jiewen <= ;jiewen.yao@intel.com>; Gerd Hoffmann <kraxel@redhat.com>; Kumar, = Rahul R <rahul.r.kumar@intel.com>
Subject: [PATCH v1 03/13] UefiCpuPkg/SmmRelocationLib: Add library i= nstance for OVMF
 
Due to the definition difference of SMRAM Save Sta= te,
SmmBase config in SMRAM Save State for OVMF is also different.

This patch provides the OvmfSmmRelocationLib library instance
to handle the SMRAM Save State difference.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Zeng Star <star.zeng@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
---
 .../SmmRelocationLib/OvmfSmmRelocationLib.inf    =   |  61 ++++++++++++
 .../SmmRelocationLib/OvmfSmramSaveStateConfig.c    | 1= 07 +++++++++++++++++++++
 2 files changed, 168 insertions(+)
 create mode 100644 UefiCpuPkg/Library/SmmRelocationLib/OvmfSmmRelocat= ionLib.inf
 create mode 100644 UefiCpuPkg/Library/SmmRelocationLib/OvmfSmramSaveS= tateConfig.c

diff --git a/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmmRelocationLib.inf b= /UefiCpuPkg/Library/SmmRelocationLib/OvmfSmmRelocationLib.inf
new file mode 100644
index 0000000000..eba1129ac2
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmmRelocationLib.inf
@@ -0,0 +1,61 @@
+## @file
+# SMM Relocation Lib for each processor.
+#
+# This Lib produces the SMM_BASE_HOB in HOB database which tells
+# the PiSmmCpuDxeSmm driver (runs at a later phase) about the new
+# SMBASE for each processor. PiSmmCpuDxeSmm driver installs the
+# SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for processor
+# Index.
+#
+# Copyright (c) 2024, Intel Corporation. All rights reserved.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION         &n= bsp;          =3D 0x00010005 +  BASE_NAME         &nbs= p;            =3D Sm= mRelocationLib
+  FILE_GUID         &nbs= p;            =3D 51= 834F51-CCE0-4743-B553-935D0C8A53FF
+  MODULE_TYPE         &n= bsp;          =3D PEIM
+  VERSION_STRING         = ;        =3D 1.0
+  LIBRARY_CLASS         =          =3D SmmRelocationLib
+
+[Sources]
+  InternalSmmRelocationLib.h
+  OvmfSmramSaveStateConfig.c
+  SmmRelocationLib.c
+
+[Sources.Ia32]
+  Ia32/Semaphore.c
+  Ia32/SmmInit.nasm
+
+[Sources.X64]
+  X64/Semaphore.c
+  X64/SmmInit.nasm
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  CpuExceptionHandlerLib
+  DebugLib
+  HobLib
+  LocalApicLib
+  MemoryAllocationLib
+  PcdLib
+  PeiServicesLib
+
+[Guids]
+  gSmmBaseHobGuid        &nbs= p;            &= nbsp;         ## HOB ALWAYS_PRODUCE= D
+  gEfiSmmSmramMemoryGuid       &nb= sp;            =     ## CONSUMES
+
+[Pcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize    = ;            &n= bsp;    ## CONSUMES
+
+[FeaturePcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport   &nb= sp;            =         ## CONSUMES
diff --git a/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmramSaveStateConfig.c= b/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmramSaveStateConfig.c
new file mode 100644
index 0000000000..505b1d694a
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmRelocationLib/OvmfSmramSaveStateConfig.c
@@ -0,0 +1,107 @@
+/** @file
+  Config SMRAM Save State for SmmBases Relocation.
+
+  Copyright (c) 2024, Intel Corporation. All rights reserved.<BR&g= t;
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "InternalSmmRelocationLib.h"
+#include <Register/Amd/SmramSaveStateMap.h>
+
+/**
+  This function configures the SmBase on the currently executing CPU.=
+
+  @param[in]     CpuIndex    =          The index of the CPU.
+  @param[in,out] CpuState       &n= bsp;     Pointer to SMRAM Save State Map for the
+            &n= bsp;            = ;             c= urrently executing CPU. On out, SmBase is
+            &n= bsp;            = ;             u= pdated to the new value.
+
+**/
+VOID
+EFIAPI
+ConfigureSmBase (
+  IN     UINTN      = ;           CpuIndex,
+  IN OUT SMRAM_SAVE_STATE_MAP  *CpuState
+  )
+{
+  AMD_SMRAM_SAVE_STATE_MAP  *CpuSaveState;
+
+  CpuSaveState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
+
+  if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) {
+    CpuSaveState->x86.SMBASE =3D (UINT32)mSmBaseForAllCp= us[CpuIndex];
+  } else {
+    CpuSaveState->x64.SMBASE =3D (UINT32)mSmBaseForAllCp= us[CpuIndex];
+  }
+}
+
+/**
+  This function updates the SMRAM save state on the currently executi= ng CPU
+  to resume execution at a specific address after an RSM instruction.=   This
+  function must evaluate the SMRAM save state to determine the execut= ion mode
+  the RSM instruction resumes and update the resume execution address= with
+  either NewInstructionPointer32 or NewInstructionPoint.  The au= to HALT restart
+  flag in the SMRAM save state must always be cleared.  This fun= ction returns
+  the value of the instruction pointer from the SMRAM save state that= was
+  replaced.  If this function returns 0, then the SMRAM save sta= te was not
+  modified.
+
+  This function is called during the very first SMI on each CPU after=
+  SmmCpuFeaturesInitializeProcessor() to set a flag in normal executi= on mode
+  to signal that the SMBASE of each CPU has been updated before the d= efault
+  SMBASE address is used for the first SMI to the next CPU.
+
+  @param[in]     CpuIndex    =              Th= e processor index for the currently
+            &n= bsp;            = ;            &n= bsp;    executing CPU.
+  @param[in,out] CpuState       &n= bsp;         Pointer to SMRAM Save = State Map for the
+            &n= bsp;            = ;            &n= bsp;    currently executing CPU.
+  @param[in]     NewInstructionPointer32  In= struction pointer to use if resuming to
+            &n= bsp;            = ;            &n= bsp;    32-bit mode from 64-bit SMM.
+  @param[in]     NewInstructionPointer  = ;  Instruction pointer to use if resuming to
+            &n= bsp;            = ;            &n= bsp;    same mode as SMM.
+
+  @retval The value of the original instruction pointer before it was= hooked.
+
+**/
+UINT64
+EFIAPI
+HookReturnFromSmm (
+  IN     UINTN      = ;           CpuIndex,
+  IN OUT SMRAM_SAVE_STATE_MAP  *CpuState,
+  IN     UINT64     &nbs= p;          NewInstructionPoin= ter32,
+  IN     UINT64     &nbs= p;          NewInstructionPoin= ter
+  )
+{
+  UINT64          &= nbsp;         OriginalInstructionPo= inter;
+  AMD_SMRAM_SAVE_STATE_MAP  *CpuSaveState;
+
+  CpuSaveState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
+  if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) {
+    OriginalInstructionPointer =3D (UINT64)CpuSaveState->= ;x86._EIP;
+    CpuSaveState->x86._EIP     =3D (= UINT32)NewInstructionPointer;
+    //
+    // Clear the auto HALT restart flag so the RSM instruct= ion returns
+    // program control to the instruction following the HLT= instruction.
+    //
+    if ((CpuSaveState->x86.AutoHALTRestart & BIT0) != =3D 0) {
+      CpuSaveState->x86.AutoHALTRestart &= =3D ~BIT0;
+    }
+  } else {
+    OriginalInstructionPointer =3D CpuSaveState->x64._RI= P;
+    if ((CpuSaveState->x64.EFER & LMA) =3D=3D 0) { +      CpuSaveState->x64._RIP =3D (UINT32)NewIn= structionPointer32;
+    } else {
+      CpuSaveState->x64._RIP =3D (UINT32)NewIn= structionPointer;
+    }
+
+    //
+    // Clear the auto HALT restart flag so the RSM instruct= ion returns
+    // program control to the instruction following the HLT= instruction.
+    //
+    if ((CpuSaveState->x64.AutoHALTRestart & BIT0) != =3D 0) {
+      CpuSaveState->x64.AutoHALTRestart &= =3D ~BIT0;
+    }
+  }
+
+  return OriginalInstructionPointer;
+}
--
2.16.2.windows.1

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