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Thread-Topic: [PATCH v2 3/3] UefiCpuPkg/CpuMpPei: Use CpuPageTableLib to set memory attribute. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: fcb45P8NrD4M3usrLxJHiOIvx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=t8TkHsdf; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Ray Ni Thanks, Ray > -----Original Message----- > From: Liu, Zhiguang > Sent: Thursday, November 30, 2023 2:29 PM > To: devel@edk2.groups.io > Cc: Liu, Zhiguang ; Ni, Ray ; > Kumar, Rahul R ; Gerd Hoffmann > ; Laszlo Ersek > Subject: [PATCH v2 3/3] UefiCpuPkg/CpuMpPei: Use CpuPageTableLib to set > memory attribute. >=20 > Currently, there are code to set memory attribute in CpuMpPei module. > However, the code doesn't handle the case of 5 level paging. > Use the CpuPageTableLib to set memory attribute for two purpose: > 1. Add 5 level paging support > 2. Clean up code >=20 > Cc: Ray Ni > Cc: Rahul Kumar > Cc: Gerd Hoffmann > Cc: Laszlo Ersek > Signed-off-by: Zhiguang Liu > --- > UefiCpuPkg/CpuMpPei/CpuPaging.c | 317 +++++++------------------------- > 1 file changed, 69 insertions(+), 248 deletions(-) >=20 > diff --git a/UefiCpuPkg/CpuMpPei/CpuPaging.c > b/UefiCpuPkg/CpuMpPei/CpuPaging.c > index b7ddb0005b..2dd7237141 100644 > --- a/UefiCpuPkg/CpuMpPei/CpuPaging.c > +++ b/UefiCpuPkg/CpuMpPei/CpuPaging.c > @@ -15,50 +15,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #include >=20 > #include "CpuMpPei.h" > - > -#define IA32_PG_P BIT0 > -#define IA32_PG_RW BIT1 > -#define IA32_PG_U BIT2 > -#define IA32_PG_A BIT5 > -#define IA32_PG_D BIT6 > -#define IA32_PG_PS BIT7 > -#define IA32_PG_NX BIT63 > - > -#define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P) > -#define PAGE_PROGATE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_NX | > IA32_PG_U | \ > - PAGE_ATTRIBUTE_BITS) > - > -#define PAGING_PAE_INDEX_MASK 0x1FF > -#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull > -#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull > -#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull > -#define PAGING_512G_ADDRESS_MASK_64 0x000FFF8000000000ull > - > -typedef enum { > - PageNone =3D 0, > - PageMin =3D 1, > - Page4K =3D PageMin, > - Page2M =3D 2, > - Page1G =3D 3, > - Page512G =3D 4, > - PageMax =3D Page512G > -} PAGE_ATTRIBUTE; > - > -typedef struct { > - PAGE_ATTRIBUTE Attribute; > - UINT64 Length; > - UINT64 AddressMask; > - UINTN AddressBitOffset; > - UINTN AddressBitLength; > -} PAGE_ATTRIBUTE_TABLE; > - > -PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] =3D { > - { PageNone, 0, 0, 0, 0 }, > - { Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64, 12, 9 }, > - { Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64, 21, 9 }, > - { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64, 30, 9 }, > - { Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9 }, > -}; > +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull >=20 > EFI_PEI_NOTIFY_DESCRIPTOR mPostMemNotifyList[] =3D { > { > @@ -117,237 +74,101 @@ AllocatePageTableMemory ( > return Address; > } >=20 > -/** > - Get the type of top level page table. > - > - @retval Page512G PML4 paging. > - @retval Page1G PAE paging. > - > -**/ > -PAGE_ATTRIBUTE > -GetPageTableTopLevelType ( > - VOID > - ) > -{ > - MSR_IA32_EFER_REGISTER MsrEfer; > - > - MsrEfer.Uint64 =3D AsmReadMsr64 (MSR_CORE_IA32_EFER); > - > - return (MsrEfer.Bits.LMA =3D=3D 1) ? Page512G : Page1G; > -} > - > -/** > - Return page table entry matching the address. > - > - @param[in] Address The address to be checked. > - @param[out] PageAttributes The page attribute of the page entry. > - > - @return The page entry. > -**/ > -VOID * > -GetPageTableEntry ( > - IN PHYSICAL_ADDRESS Address, > - OUT PAGE_ATTRIBUTE *PageAttribute > - ) > -{ > - INTN Level; > - UINTN Index; > - UINT64 *PageTable; > - UINT64 AddressEncMask; > - > - AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); > - PageTable =3D (UINT64 *)(UINTN)(AsmReadCr3 () & > PAGING_4K_ADDRESS_MASK_64); > - for (Level =3D (INTN)GetPageTableTopLevelType (); Level > 0; --Level) = { > - Index =3D (UINTN)RShiftU64 (Address, > mPageAttributeTable[Level].AddressBitOffset); > - Index &=3D PAGING_PAE_INDEX_MASK; > - > - // > - // No mapping? > - // > - if (PageTable[Index] =3D=3D 0) { > - *PageAttribute =3D PageNone; > - return NULL; > - } > - > - // > - // Page memory? > - // > - if (((PageTable[Index] & IA32_PG_PS) !=3D 0) || (Level =3D=3D PageMi= n)) { > - *PageAttribute =3D (PAGE_ATTRIBUTE)Level; > - return &PageTable[Index]; > - } > - > - // > - // Page directory or table > - // > - PageTable =3D (UINT64 *)(UINTN)(PageTable[Index] & > - ~AddressEncMask & > - PAGING_4K_ADDRESS_MASK_64); > - } > - > - *PageAttribute =3D PageNone; > - return NULL; > -} > - > -/** > - This function splits one page entry to smaller page entries. > - > - @param[in] PageEntry The page entry to be splitted. > - @param[in] PageAttribute The page attribute of the page entry. > - @param[in] SplitAttribute How to split the page entry. > - @param[in] Recursively Do the split recursively or not. > - > - @retval RETURN_SUCCESS The page entry is splitted. > - @retval RETURN_INVALID_PARAMETER If target page attribute is invalid > - @retval RETURN_OUT_OF_RESOURCES No resource to split page entry. > -**/ > -RETURN_STATUS > -SplitPage ( > - IN UINT64 *PageEntry, > - IN PAGE_ATTRIBUTE PageAttribute, > - IN PAGE_ATTRIBUTE SplitAttribute, > - IN BOOLEAN Recursively > - ) > -{ > - UINT64 BaseAddress; > - UINT64 *NewPageEntry; > - UINTN Index; > - UINT64 AddressEncMask; > - PAGE_ATTRIBUTE SplitTo; > - > - if ((SplitAttribute =3D=3D PageNone) || (SplitAttribute >=3D PageAttri= bute)) { > - ASSERT (SplitAttribute !=3D PageNone); > - ASSERT (SplitAttribute < PageAttribute); > - return RETURN_INVALID_PARAMETER; > - } > - > - NewPageEntry =3D AllocatePageTableMemory (1); > - if (NewPageEntry =3D=3D NULL) { > - ASSERT (NewPageEntry !=3D NULL); > - return RETURN_OUT_OF_RESOURCES; > - } > - > - // > - // One level down each step to achieve more compact page table. > - // > - SplitTo =3D PageAttribute - 1; > - AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & > - mPageAttributeTable[SplitTo].AddressMask; > - BaseAddress =3D *PageEntry & > - ~PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & > - mPageAttributeTable[PageAttribute].AddressMask; > - for (Index =3D 0; Index < SIZE_4KB / sizeof (UINT64); Index++) { > - NewPageEntry[Index] =3D BaseAddress | AddressEncMask | > - ((*PageEntry) & PAGE_PROGATE_BITS); > - > - if (SplitTo !=3D PageMin) { > - NewPageEntry[Index] |=3D IA32_PG_PS; > - } > - > - if (Recursively && (SplitTo > SplitAttribute)) { > - SplitPage (&NewPageEntry[Index], SplitTo, SplitAttribute, Recursiv= ely); > - } > - > - BaseAddress +=3D mPageAttributeTable[SplitTo].Length; > - } > - > - (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | AddressEncMask | > PAGE_ATTRIBUTE_BITS; > - > - return RETURN_SUCCESS; > -} > - > /** > This function modifies the page attributes for the memory region speci= fied > - by BaseAddress and Length from their current attributes to the attribu= tes > - specified by Attributes. > + by BaseAddress and Length to not present. >=20 > Caller should make sure BaseAddress and Length is at page boundary. >=20 > @param[in] BaseAddress Start address of a memory region. > @param[in] Length Size in bytes of the memory region. > - @param[in] Attributes Bit mask of attributes to modify. > - > - @retval RETURN_SUCCESS The attributes were modified for the > memory > - region. > - @retval RETURN_INVALID_PARAMETER Length is zero; or, > - Attributes specified an illegal comb= ination > - of attributes that cannot be set tog= ether; or > - Addressis not 4KB aligned. > + > + @retval RETURN_SUCCESS The memory region is changed to not > present. > @retval RETURN_OUT_OF_RESOURCES There are not enough system > resources to modify > the attributes. > @retval RETURN_UNSUPPORTED Cannot modify the attributes of give= n > memory. >=20 > **/ > RETURN_STATUS > -EFIAPI > -ConvertMemoryPageAttributes ( > +ConvertMemoryPageToNotPresent ( > IN PHYSICAL_ADDRESS BaseAddress, > - IN UINT64 Length, > - IN UINT64 Attributes > + IN UINT64 Length > ) > { > - UINT64 *PageEntry; > - PAGE_ATTRIBUTE PageAttribute; > - RETURN_STATUS Status; > - EFI_PHYSICAL_ADDRESS MaximumAddress; > - > - if ((Length =3D=3D 0) || > - ((BaseAddress & (SIZE_4KB - 1)) !=3D 0) || > - ((Length & (SIZE_4KB - 1)) !=3D 0)) > - { > - ASSERT (Length > 0); > - ASSERT ((BaseAddress & (SIZE_4KB - 1)) =3D=3D 0); > - ASSERT ((Length & (SIZE_4KB - 1)) =3D=3D 0); > - > - return RETURN_INVALID_PARAMETER; > - } > - > - MaximumAddress =3D (EFI_PHYSICAL_ADDRESS)MAX_UINT32; > - if ((BaseAddress > MaximumAddress) || > - (Length > MaximumAddress) || > - (BaseAddress > MaximumAddress - (Length - 1))) > - { > - return RETURN_UNSUPPORTED; > - } > - > - // > - // Below logic is to check 2M/4K page to make sure we do not waste > memory. > - // > - while (Length !=3D 0) { > - PageEntry =3D GetPageTableEntry (BaseAddress, &PageAttribute); > - if (PageEntry =3D=3D NULL) { > - return RETURN_UNSUPPORTED; > - } > + EFI_STATUS Status; > + UINTN PageTable; > + EFI_PHYSICAL_ADDRESS Buffer; > + UINTN BufferSize; > + IA32_MAP_ATTRIBUTE MapAttribute; > + IA32_MAP_ATTRIBUTE MapMask; > + PAGING_MODE PagingMode; > + IA32_CR4 Cr4; > + BOOLEAN Page5LevelSupport; > + UINT32 RegEax; > + BOOLEAN Page1GSupport; > + CPUID_EXTENDED_CPU_SIG_EDX RegEdx; > + > + if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { > + // > + // Check Page5Level Support or not. > + // > + Cr4.UintN =3D AsmReadCr4 (); > + Page5LevelSupport =3D (Cr4.Bits.LA57 ? TRUE : FALSE); >=20 > - if (PageAttribute !=3D Page4K) { > - Status =3D SplitPage (PageEntry, PageAttribute, Page4K, FALSE); > - if (RETURN_ERROR (Status)) { > - return Status; > + // > + // Check Page1G Support or not. > + // > + Page1GSupport =3D FALSE; > + AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); > + if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) { > + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, > &RegEdx.Uint32); > + if (RegEdx.Bits.Page1GB !=3D 0) { > + Page1GSupport =3D TRUE; > } > - > - // > - // Do it again until the page is 4K. > - // > - continue; > } >=20 > // > - // Just take care of 'present' bit for Stack Guard. > + // Decide Paging Mode according Page5LevelSupport & Page1GSupport. > // > - if ((Attributes & IA32_PG_P) !=3D 0) { > - *PageEntry |=3D (UINT64)IA32_PG_P; > + if (Page5LevelSupport) { > + PagingMode =3D Page1GSupport ? Paging5Level1GB : Paging5Level; > } else { > - *PageEntry &=3D ~((UINT64)IA32_PG_P); > + PagingMode =3D Page1GSupport ? Paging4Level1GB : Paging4Level; > } > + } else { > + PagingMode =3D PagingPae; > + } > + > + MapAttribute.Uint64 =3D 0; > + MapMask.Uint64 =3D 0; > + MapMask.Bits.Present =3D 1; > + PageTable =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; > + BufferSize =3D 0; >=20 > + // > + // Get required buffer size for the pagetable that will be created. > + // > + Status =3D PageTableMap (&PageTable, PagingMode, 0, &BufferSize, > BaseAddress, Length, &MapAttribute, &MapMask, NULL); > + if (Status =3D=3D EFI_BUFFER_TOO_SMALL) { > // > - // Convert success, move to next > + // Allocate required Buffer. > // > - BaseAddress +=3D SIZE_4KB; > - Length -=3D SIZE_4KB; > + Status =3D PeiServicesAllocatePages ( > + EfiBootServicesData, > + EFI_SIZE_TO_PAGES (BufferSize), > + &Buffer > + ); > + ASSERT_EFI_ERROR (Status); > + if (EFI_ERROR (Status)) { > + return EFI_OUT_OF_RESOURCES; > + } > + > + Status =3D PageTableMap (&PageTable, PagingMode, (VOID *)(UINTN)Buff= er, > &BufferSize, BaseAddress, Length, &MapAttribute, &MapMask, NULL); > } >=20 > - return RETURN_SUCCESS; > + ASSERT_EFI_ERROR (Status); > + AsmWriteCr3 (PageTable); > + return Status; > } >=20 > /** > @@ -516,7 +337,7 @@ SetupStackGuardPage ( > // > // Set Guard page at stack base address. > // > - ConvertMemoryPageAttributes (StackBase, EFI_PAGE_SIZE, 0); > + ConvertMemoryPageToNotPresent (StackBase, EFI_PAGE_SIZE); > DEBUG (( > DEBUG_INFO, > "Stack Guard set at %lx [cpu%lu]!\n", > @@ -599,7 +420,7 @@ MemoryDiscoveredPpiNotifyCallback ( > // Enable #PF exception, so if the code access SPI after disable NEM= , it will > generate > // the exception to avoid potential vulnerability. > // > - ConvertMemoryPageAttributes (MigratedFvInfo->FvOrgBase, > MigratedFvInfo->FvLength, 0); > + ConvertMemoryPageToNotPresent (MigratedFvInfo->FvOrgBase, > MigratedFvInfo->FvLength); >=20 > Hob.Raw =3D GET_NEXT_HOB (Hob); > Hob.Raw =3D GetNextGuidHob (&gEdkiiMigratedFvInfoGuid, Hob.Raw); > -- > 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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