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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Acked-by: Ray Ni > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Sunil V L > Sent: Friday, February 10, 2023 8:30 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Kumar, > Rahul R ; Daniel Schaefer ; > Abner Chang ; Gerd Hoffmann ; > Warkentin, Andrei > Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 06/19] > UefiCpuPkg: Add BaseRiscV64CpuTimerLib library >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 >=20 > Add the RISC-V instance of the TimerLib. >=20 > This is mostly copied from > edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Cc: Daniel Schaefer > Cc: Abner Chang > Cc: Gerd Hoffmann > Signed-off-by: Sunil V L > Acked-by: Abner Chang > Reviewed-by: Andrei Warkentin > --- > UefiCpuPkg/UefiCpuPkg.dsc | = 1 + > UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf | = 33 > ++++ > UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c | 1= 99 > ++++++++++++++++++++ > UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.uni | > 14 ++ > 4 files changed, 247 insertions(+) >=20 > diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc > index 35e66d93efa6..c511403842b8 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dsc > +++ b/UefiCpuPkg/UefiCpuPkg.dsc > @@ -197,6 +197,7 @@ [Components.X64] >=20 > [Components.RISCV64] >=20 > UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExce > ptionHandlerLib.inf > + UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf >=20 > [BuildOptions] > *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES > diff --git > a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf > b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf > new file mode 100644 > index 000000000000..3d5eaa41716d > --- /dev/null > +++ > b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf > @@ -0,0 +1,33 @@ > +## @file > +# RISC-V Base CPU Timer Library Instance > +# > +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP.= All > rights reserved.
> +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x0001001B > + BASE_NAME =3D BaseRisV64CpuTimerLib > + FILE_GUID =3D B635A600-EA24-4199-88E8-5761EEA96A5= 1 > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D TimerLib > + MODULE_UNI_FILE =3D BaseRisV64CpuTimerLib.uni > + > +[Sources] > + CpuTimerLib.c > + > +[Packages] > + MdePkg/MdePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + > +[LibraryClasses] > + BaseLib > + PcdLib > + DebugLib > + > +[Pcd] > + gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## > CONSUMES > diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c > b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c > new file mode 100644 > index 000000000000..9c8efc0f3530 > --- /dev/null > +++ b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c > @@ -0,0 +1,199 @@ > +/** @file > + RISC-V instance of Timer Library. > + > + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. = All > rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > + > +/** > + Stalls the CPU for at least the given number of ticks. > + > + Stalls the CPU for at least the given number of ticks. It's invoked by > + MicroSecondDelay() and NanoSecondDelay(). > + > + @param Delay A period of time to delay in ticks. > + > +**/ > +VOID > +InternalRiscVTimerDelay ( > + IN UINT32 Delay > + ) > +{ > + UINT32 Ticks; > + UINT32 Times; > + > + Times =3D Delay >> (RISCV_TIMER_COMPARE_BITS - 2); > + Delay &=3D ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1); > + do { > + // > + // The target timer count is calculated here > + // > + Ticks =3D RiscVReadTimer () + Delay; > + Delay =3D 1 << (RISCV_TIMER_COMPARE_BITS - 2); > + while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BIT= S - > 1))) =3D=3D 0) { > + CpuPause (); > + } > + } while (Times-- > 0); > +} > + > +/** > + Stalls the CPU for at least the given number of microseconds. > + > + Stalls the CPU for the number of microseconds specified by MicroSecond= s. > + > + @param MicroSeconds The minimum number of microseconds to delay. > + > + @return MicroSeconds > + > +**/ > +UINTN > +EFIAPI > +MicroSecondDelay ( > + IN UINTN MicroSeconds > + ) > +{ > + InternalRiscVTimerDelay ( > + (UINT32)DivU64x32 ( > + MultU64x32 ( > + MicroSeconds, > + PcdGet64 (PcdCpuCoreCrystalClockFrequency) > + ), > + 1000000u > + ) > + ); > + return MicroSeconds; > +} > + > +/** > + Stalls the CPU for at least the given number of nanoseconds. > + > + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. > + > + @param NanoSeconds The minimum number of nanoseconds to delay. > + > + @return NanoSeconds > + > +**/ > +UINTN > +EFIAPI > +NanoSecondDelay ( > + IN UINTN NanoSeconds > + ) > +{ > + InternalRiscVTimerDelay ( > + (UINT32)DivU64x32 ( > + MultU64x32 ( > + NanoSeconds, > + PcdGet64 (PcdCpuCoreCrystalClockFrequency) > + ), > + 1000000000u > + ) > + ); > + return NanoSeconds; > +} > + > +/** > + Retrieves the current value of a 64-bit free running performance count= er. > + > + Retrieves the current value of a 64-bit free running performance count= er. The > + counter can either count up by 1 or count down by 1. If the physical > + performance counter counts by a larger increment, then the counter val= ues > + must be translated. The properties of the counter can be retrieved fro= m > + GetPerformanceCounterProperties(). > + > + @return The current value of the free running performance counter. > + > +**/ > +UINT64 > +EFIAPI > +GetPerformanceCounter ( > + VOID > + ) > +{ > + return (UINT64)RiscVReadTimer (); > +} > + > +/**return > + Retrieves the 64-bit frequency in Hz and the range of performance coun= ter > + values. > + > + If StartValue is not NULL, then the value that the performance counter= starts > + with immediately after is it rolls over is returned in StartValue. If > + EndValue is not NULL, then the value that the performance counter end = with > + immediately before it rolls over is returned in EndValue. The 64-bit > + frequency of the performance counter in Hz is always returned. If Star= tValue > + is less than EndValue, then the performance counter counts up. If Star= tValue > + is greater than EndValue, then the performance counter counts down. Fo= r > + example, a 64-bit free running counter that counts up would have a Sta= rtValue > + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running coun= ter > + that counts down would have a StartValue of 0xFFFFFF and an EndValue o= f 0. > + > + @param StartValue The value the performance counter starts with when= it > + rolls over. > + @param EndValue The value that the performance counter ends with > before > + it rolls over. > + > + @return The frequency in Hz. > + > +**/ > +UINT64 > +EFIAPI > +GetPerformanceCounterProperties ( > + OUT UINT64 *StartValue, OPTIONAL > + OUT UINT64 *EndValue OPTIONAL > + ) > +{ > + if (StartValue !=3D NULL) { > + *StartValue =3D 0; > + } > + > + if (EndValue !=3D NULL) { > + *EndValue =3D 32 - 1; > + } > + > + return PcdGet64 (PcdCpuCoreCrystalClockFrequency); > +} > + > +/** > + Converts elapsed ticks of performance counter to time in nanoseconds. > + > + This function converts the elapsed ticks of running performance counte= r to > + time value in unit of nanoseconds. > + > + @param Ticks The number of elapsed ticks of running performance c= ounter. > + > + @return The elapsed time in nanoseconds. > + > +**/ > +UINT64 > +EFIAPI > +GetTimeInNanoSecond ( > + IN UINT64 Ticks > + ) > +{ > + UINT64 NanoSeconds; > + UINT32 Remainder; > + > + // > + // Ticks > + // Time =3D --------- x 1,000,000,000 > + // Frequency > + // > + NanoSeconds =3D MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 > (PcdCpuCoreCrystalClockFrequency), &Remainder), 1000000000u); > + > + // > + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainde= r > * 1,000,000,000) > + // will not overflow 64-bit. > + // > + NanoSeconds +=3D DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u= ), > PcdGet64 (PcdCpuCoreCrystalClockFrequency)); > + > + return NanoSeconds; > +} > diff --git > a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.uni > b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.uni > new file mode 100644 > index 000000000000..bb061f9a8ff0 > --- /dev/null > +++ > b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.uni > @@ -0,0 +1,14 @@ > +// /** @file > +// Base CPU Timer Library for RISC-V > +// > +// Copyright (c) 2023, Ventana Micro Systems Inc. All rights reserved. > +// > +// SPDX-License-Identifier: BSD-2-Clause-Patent > +// > +// **/ > + > + > +#string STR_MODULE_ABSTRACT #language en-US "RISC-V CPU Time= r > Library" > + > +#string STR_MODULE_DESCRIPTION #language en-US "Provides basic > timer support for RISC-V." > + > -- > 2.34.1 >=20 >=20 >=20 >=20 >=20