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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: XPExMsT6TR3QmINKMOeWA4Rtx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=o+MaCvDe; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Ray Ni Thanks, Ray > -----Original Message----- > From: Jin, Zhi > Sent: Friday, January 5, 2024 10:54 AM > To: devel@edk2.groups.io > Cc: Jin, Zhi ; Ni, Ray ; Laszlo Erse= k > ; Kumar, Rahul R ; Gerd > Hoffmann ; Wu, Jiaxin > Subject: [PATCH v2 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize > PatchSmmSaveStateMap and FlushTlbForAll >=20 > PatchSmmSaveStateMap patches the SMM entry (code) and SmmSaveState > region (data) for each core, which can be improved to flush TLB once > after all the memory entries have been patched. > FlushTlbForAll flushes TLB for each core in serial, which can be > improved to flush TLB in parrallel. >=20 > v2: > Add the missing FlushTlbForAll() back in PatchSmmSaveStateMap(). >=20 > Cc: Ray Ni > Cc: Laszlo Ersek > Cc: Rahul Kumar > Cc: Gerd Hoffmann > Cc: Jiaxin Wu > Signed-off-by: Zhi Jin > --- > .../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 97 > +++++++++++++------ > 1 file changed, 65 insertions(+), 32 deletions(-) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > index 15f998e501..12f3c0b8e8 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > @@ -547,17 +547,14 @@ FlushTlbForAll ( > VOID > ) > { > - UINTN Index; > - > FlushTlbOnCurrentProcessor (NULL); > - > - for (Index =3D 0; Index < gSmst->NumberOfCpus; Index++) { > - if (Index !=3D gSmst->CurrentlyExecutingCpu) { > - // Force to start up AP in blocking mode, > - SmmBlockingStartupThisAp (FlushTlbOnCurrentProcessor, Index, NULL)= ; > - // Do not check return status, because AP might not be present in = some > corner cases. > - } > - } > + InternalSmmStartupAllAPs ( > + (EFI_AP_PROCEDURE2)FlushTlbOnCurrentProcessor, > + 0, > + NULL, > + NULL, > + NULL > + ); > } >=20 > /** > @@ -799,72 +796,108 @@ PatchSmmSaveStateMap ( > UINTN TileCodeSize; > UINTN TileDataSize; > UINTN TileSize; > + UINTN PageTableBase; >=20 > - TileCodeSize =3D GetSmiHandlerSize (); > - TileCodeSize =3D ALIGN_VALUE (TileCodeSize, SIZE_4KB); > - TileDataSize =3D (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + > sizeof (SMRAM_SAVE_STATE_MAP); > - TileDataSize =3D ALIGN_VALUE (TileDataSize, SIZE_4KB); > - TileSize =3D TileDataSize + TileCodeSize - 1; > - TileSize =3D 2 * GetPowerOfTwo32 ((UINT32)TileSize); > + TileCodeSize =3D GetSmiHandlerSize (); > + TileCodeSize =3D ALIGN_VALUE (TileCodeSize, SIZE_4KB); > + TileDataSize =3D (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + > sizeof (SMRAM_SAVE_STATE_MAP); > + TileDataSize =3D ALIGN_VALUE (TileDataSize, SIZE_4KB); > + TileSize =3D TileDataSize + TileCodeSize - 1; > + TileSize =3D 2 * GetPowerOfTwo32 ((UINT32)TileSize); > + PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; >=20 > DEBUG ((DEBUG_INFO, "PatchSmmSaveStateMap:\n")); > for (Index =3D 0; Index < mMaxNumberOfCpus - 1; Index++) { > // > // Code > // > - SmmSetMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET, > TileCodeSize, > - EFI_MEMORY_RO > + EFI_MEMORY_RO, > + TRUE, > + NULL > ); > - SmmClearMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET, > TileCodeSize, > - EFI_MEMORY_XP > + EFI_MEMORY_XP, > + FALSE, > + NULL > ); >=20 > // > // Data > // > - SmmClearMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET + > TileCodeSize, > TileSize - TileCodeSize, > - EFI_MEMORY_RO > + EFI_MEMORY_RO, > + FALSE, > + NULL > ); > - SmmSetMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET + > TileCodeSize, > TileSize - TileCodeSize, > - EFI_MEMORY_XP > + EFI_MEMORY_XP, > + TRUE, > + NULL > ); > } >=20 > // > // Code > // > - SmmSetMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + > SMM_HANDLER_OFFSET, > TileCodeSize, > - EFI_MEMORY_RO > + EFI_MEMORY_RO, > + TRUE, > + NULL > ); > - SmmClearMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + > SMM_HANDLER_OFFSET, > TileCodeSize, > - EFI_MEMORY_XP > + EFI_MEMORY_XP, > + FALSE, > + NULL > ); >=20 > // > // Data > // > - SmmClearMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + > SMM_HANDLER_OFFSET + TileCodeSize, > SIZE_32KB - TileCodeSize, > - EFI_MEMORY_RO > + EFI_MEMORY_RO, > + FALSE, > + NULL > ); > - SmmSetMemoryAttributes ( > + ConvertMemoryPageAttributes ( > + PageTableBase, > + mPagingMode, > mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + > SMM_HANDLER_OFFSET + TileCodeSize, > SIZE_32KB - TileCodeSize, > - EFI_MEMORY_XP > + EFI_MEMORY_XP, > + TRUE, > + NULL > ); > + > + FlushTlbForAll (); > } >=20 > /** > -- > 2.39.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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