Re: [edk2-devel] [PATCH 3/3] UefiCpuPkg/PiSmmCpuDxeSmm:Map SMRAM in 4K page granularity

["Ni, Ray" <ray.ni@intel.com>]

> +
> +  GenPageTable (&PageTable, PagingMode, 0, mCpuHotPlugData.SmrrBase);
> +
> +  //
> +  // Map smram range in 4K page granularity to avoid subsequent page split
> when smm ready to lock.
> +  // If BSP are splitting the 1G/2M paging entries to 512 2M/4K paging
> entries, and all APs are
> +  // still running in SMI at the same time, which might access the affected
> linear-address range
> +  // between the time of modification and the time of invalidation access.
> That will be a potential
> +  // problem leading exception happen.
> +  //
> +  ASSERT (mCpuHotPlugData.SmrrBase % SIZE_4KB == 0);
> +  ASSERT (mCpuHotPlugData.SmrrSize % SIZE_4KB == 0);

Can you please move the above 2 assertions in front of the
first call of GenPageTable() because SmrrBase is used there?

With that, Reviewed-by: Ray Ni <ray.ni@intel.com>

> +  GenPageTable (&PageTable, SmramPagingMode,
> mCpuHotPlugData.SmrrBase, mCpuHotPlugData.SmrrSize);
> +
> +  GenPageTable (&PageTable, PagingMode, mCpuHotPlugData.SmrrBase +
> mCpuHotPlugData.SmrrSize, Length - mCpuHotPlugData.SmrrBase -
> mCpuHotPlugData.SmrrSize);
> 
>    if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
>      //
> @@ -1698,6 +1764,7 @@ GenSmmPageTable (
>      for (Index = 0; Index < gSmmCpuPrivate-
> >SmmCoreEntryContext.NumberOfCpus; Index++) {
>        GuardPage = mSmmStackArrayBase + EFI_PAGE_SIZE + Index *
> (mSmmStackSize + mSmmShadowStackSize);
>        Status    = ConvertMemoryPageAttributes (PageTable, PagingMode,
> GuardPage, SIZE_4KB, EFI_MEMORY_RP, TRUE, NULL);
> +      ASSERT (Status == RETURN_SUCCESS);
>      }
>    }
> 
> @@ -1706,6 +1773,7 @@ GenSmmPageTable (
>      // Mark [0, 4k] as non-present
>      //
>      Status = ConvertMemoryPageAttributes (PageTable, PagingMode, 0,
> SIZE_4KB, EFI_MEMORY_RP, TRUE, NULL);
> +    ASSERT (Status == RETURN_SUCCESS);
>    }
> 
>    return (UINTN)PageTable;
> --
> 2.31.1.windows.1



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