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Internal X-MS-Exchange-CrossTenant-AuthSource: MN6PR11MB8244.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c3d11073-0aca-4b9a-4add-08dc64eba8f0 X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Apr 2024 05:50:49.3995 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: lVopYxrHl4Q5mB9qnN6zuIEC52iiYmucctguUIEQYyVm3znsmzlOpasB1O7/TMymQJjmtNlYnq3hpT+5v4qn9g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR11MB8365 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 24 Apr 2024 22:50:55 -0700 Resent-From: ray.ni@intel.com Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Y3CifJWVLrHzL2tEsZK1otSVx7686176AA= Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN6PR11MB8244BC511F9259F8E287FD448C172MN6PR11MB8244namp_" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=xva5Yzsg; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io --_000_MN6PR11MB8244BC511F9259F8E287FD448C172MN6PR11MB8244namp_ Content-Type: text/plain; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable I checked the AMD64 Architecture Programmer's Manual and it says below: --- AMD64 manual --- SMM-revision Level=97Bits 15:0. Specifies the version of SMM supported by t= he processor. The SMM-revision level is of the form 0_xx64h, where xx start= s with 00 and is incremented for later revisions to the SMM mechanism. --- That means the SMMRevId is 0_xx64h for AMD64 processor. But I am not sure w= hat the value is for AMD32 processor. Maybe 0 according to the OVMF logic. --- OVMF's logic --- AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState; CpuSaveState =3D (AMD_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE += SMRAM_SAVE_STATE_MAP_OFFSET); if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { CpuSaveState->x86.SMBASE =3D (UINT32)SmBase; } else { CpuSaveState->x64.SMBASE =3D (UINT32)SmBase; } ------ But, I am very suspicious about the logic in AMD's version as below: --- AMD's version SmmSaveStateRegisterLma =3D (UINT8)EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT; LMAValue =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; if (LMAValue) { SmmSaveStateRegisterLma =3D (UINT8)EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT= ; } --- The above logic detects the current CPU mode and 64bit save state area layo= ut is used if it's running in 64bit. But if a AMD64 CPU runs in 32bit mode, the above logic causes the 32bit sav= e state area layout is used. It's not right! The save state area layout does not depend on the CPU running mode, but whe= ther it's a legacy CPU or a 64-capable CPU. Jiaxin, I agree that the confusion should be cleaned up by AMD experts. Let= 's not change any existing behavior. Thanks, Ray ________________________________ From: Wu, Jiaxin Sent: Thursday, April 25, 2024 8:54 To: Gerd Hoffmann Cc: devel@edk2.groups.io ; Ni, Ray = ; Zeng, Star ; Kumar, Rahul R ; Dong, Guo ; Rhodes, Sean ; Lu= , James ; Guo, Gua ; Ard Biesheuvel = ; Yao, Jiewen ; Abdul Late= ef Attar ; Abner Chang ; To= m Lendacky Subject: RE: [edk2-devel] [PATCH v3 00/13] Add SmmRelocationLib > > > > AMD version is not work for IA32X64 ovmf. > > > > I checked the detailed: CpuSaveState->x64 is always used for OVMF no > matter IA32 or X64, while AMD is not, which is decided by the MSR > EFER_ADDRESS LMA bit check. > > Hmm, probably because only PEI runs in 32-bit mode whereas DXE and SMM > run in 64-bit mode, so 32-bit PEI has to prepare things for the 64-bit > SMM. > > > There is a potential issue/open in OVMF why need use the X64 > > CpuSaveState for IA32. Before this open resolved, I still prefer to > > keep use the ovmf specific lib instance. > > Yes, lets stick to the ovmf version for now, and maybe remove it later > when fixing the ia32 ovmf builds. > Ok, no problem. -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#118266): https://edk2.groups.io/g/devel/message/118266 Mute This Topic: https://groups.io/mt/105593568/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_MN6PR11MB8244BC511F9259F8E287FD448C172MN6PR11MB8244namp_ Content-Type: text/html; charset="Windows-1252" Content-Transfer-Encoding: quoted-printable
I checked the AMD64 Architecture Programmer's Manual and it says below:
--- AMD64 manual ---
SMM-revision Level=97Bits 15:0. Specifies the version of SMM supported by t= he processor. The SMM-revision level is of the form 0_xx64h, where xx start= s with 00 and is incremented for later revisions to the SMM mechanism.
---

That means the SMMRevId is 0_xx64h for AMD64 processor. But I am not sure w= hat the value is for AMD32 processor. Maybe 0 according to the OVMF logic.<= /div>
--- OVMF's logic ---
  AMD_SMRAM_SAVE_STATE_MAP  *CpuSaveState;

  CpuSaveState =3D (AMD_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMB= ASE + SMRAM_SAVE_STATE_MAP_OFFSET);

  if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) {
    CpuSaveState->x86.SMBASE =3D (UINT32)SmBase;
  } else {
    CpuSaveState->x64.SMBASE =3D (UINT32)SmBase;
  }
------


But, I am very suspicious about the logic in AMD's version as below:
--- AMD's version
  SmmSaveStateRegisterLma =3D (UINT8)EFI_MM_SAVE_STATE_REGISTER_LMA_32= BIT;

  LMAValue =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
  if (LMAValue) {
    SmmSaveStateRegisterLma =3D (UINT8)EFI_MM_SAVE_STATE_REGISTER= _LMA_64BIT;
  }
---
The above logic detects the current CPU mode and 64bit save state area layo= ut is used if it's running in 64bit.

But if a AMD64 CPU runs in 32bit mode, the above logic causes the 32bit sav= e state area layout is used. It's not right!
The save state area layout does not depend on the CPU running mode, but whe= ther it's a legacy CPU or a 64-capable CPU.

Jiaxin, I agree that the confusion should be cleaned up by AMD experts. Let= 's not change any existing behavior.

Thanks,
Ray
From: Wu, Jiaxin <jiaxin= .wu@intel.com>
Sent: Thursday, April 25, 2024 8:54
To: Gerd Hoffmann <kraxel@redhat.com>
Cc: devel@edk2.groups.io <devel@edk2.groups.io>; Ni, Ray <r= ay.ni@intel.com>; Zeng, Star <star.zeng@intel.com>; Kumar, Rahul R= <rahul.r.kumar@intel.com>; Dong, Guo <guo.dong@intel.com>; Rho= des, Sean <sean@starlabs.systems>; Lu, James <james.lu@intel.com&g= t;; Guo, Gua <gua.guo@intel.com>; Ard Biesheuvel <ardb+tianocore@kern= el.org>; Yao, Jiewen <jiewen.yao@intel.com>; Abdul Lateef Attar &l= t;AbdulLateef.Attar@amd.com>; Abner Chang <abner.chang@amd.com>; T= om Lendacky <thomas.lendacky@amd.com>
Subject: RE: [edk2-devel] [PATCH v3 00/13] Add SmmRelocationLib
 
> >
> > AMD version is not work for IA32X64 ovmf.
> >
> > I checked the detailed: CpuSaveState->x64 is always used for O= VMF no
> matter IA32 or X64, while AMD is not, which is decided by the MSR
> EFER_ADDRESS LMA bit check.
>
> Hmm, probably because only PEI runs in 32-bit mode whereas DXE and SMM=
> run in 64-bit mode, so 32-bit PEI has to prepare things for the 64-bit=
> SMM.
>
> > There is a potential issue/open in OVMF why need use the X64
> > CpuSaveState for IA32. Before this open resolved, I still prefer = to
> > keep use the ovmf specific lib instance.
>
> Yes, lets stick to the ovmf version for now, and maybe remove it later=
> when fixing the ia32 ovmf builds.
>

Ok, no problem.


_._,_._,_
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