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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni =0A= =0A= ________________________________________=0A= From: Wu, Jiaxin =0A= Sent: Monday, May 15, 2023 10:15=0A= To: devel@edk2.groups.io=0A= Cc: Dong, Eric; Ni, Ray; Zeng, Star; Gerd Hoffmann; Kumar, Rahul R=0A= Subject: [PATCH v3 1/5] UefiCpuPkg/SecCore: Migrate page table to permanent= memory=0A= =0A= Background:=0A= For arch X64, system will enable the page table in SPI to cover 0-512G=0A= range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting (see ResetVector code).= =0A= Existing code doesn't cover the higher address access above 512G before=0A= memory-discovered callback. That will be potential problem if system=0A= access the higher address after the transition from temporary RAM to=0A= permanent MEM RAM.=0A= =0A= Solution:=0A= This patch is to migrate page table to permanent memory to map entire physi= cal=0A= address space if CR0.PG is set during temporary RAM Done.=0A= =0A= Cc: Eric Dong =0A= Cc: Ray Ni =0A= Cc: Zeng Star =0A= Cc: Gerd Hoffmann =0A= Cc: Rahul Kumar =0A= Signed-off-by: Jiaxin Wu =0A= ---=0A= UefiCpuPkg/SecCore/SecCore.inf | 1 +=0A= UefiCpuPkg/SecCore/SecCoreNative.inf | 1 +=0A= UefiCpuPkg/SecCore/SecMain.c | 147 +++++++++++++++++++++++++++++++= ++++=0A= UefiCpuPkg/SecCore/SecMain.h | 4 +=0A= 4 files changed, 153 insertions(+)=0A= =0A= diff --git a/UefiCpuPkg/SecCore/SecCore.inf b/UefiCpuPkg/SecCore/SecCore.in= f=0A= index 3758aded3b..cab69b8b97 100644=0A= --- a/UefiCpuPkg/SecCore/SecCore.inf=0A= +++ b/UefiCpuPkg/SecCore/SecCore.inf=0A= @@ -53,10 +53,11 @@=0A= CpuExceptionHandlerLib=0A= ReportStatusCodeLib=0A= PeiServicesLib=0A= PeiServicesTablePointerLib=0A= HobLib=0A= + CpuPageTableLib=0A= =0A= [Ppis]=0A= ## SOMETIMES_CONSUMES=0A= ## PRODUCES=0A= gEfiSecPlatformInformationPpiGuid=0A= diff --git a/UefiCpuPkg/SecCore/SecCoreNative.inf b/UefiCpuPkg/SecCore/SecC= oreNative.inf=0A= index 1ee6ff7d88..fa241cca94 100644=0A= --- a/UefiCpuPkg/SecCore/SecCoreNative.inf=0A= +++ b/UefiCpuPkg/SecCore/SecCoreNative.inf=0A= @@ -50,10 +50,11 @@=0A= CpuExceptionHandlerLib=0A= ReportStatusCodeLib=0A= PeiServicesLib=0A= PeiServicesTablePointerLib=0A= HobLib=0A= + CpuPageTableLib=0A= =0A= [Ppis]=0A= ## SOMETIMES_CONSUMES=0A= ## PRODUCES=0A= gEfiSecPlatformInformationPpiGuid=0A= diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c=0A= index 95375850ec..b0ab6cdae4 100644=0A= --- a/UefiCpuPkg/SecCore/SecMain.c=0A= +++ b/UefiCpuPkg/SecCore/SecMain.c=0A= @@ -70,10 +70,139 @@ MigrateGdt (=0A= AsmWriteGdtr (&Gdtr);=0A= =0A= return EFI_SUCCESS;=0A= }=0A= =0A= +/**=0A= + Migrate page table to permanent memory mapping entire physical address s= pace.=0A= +=0A= + @retval EFI_SUCCESS The PageTable was migrated successfully.= =0A= + @retval EFI_UNSUPPORTED Unsupport to migrate page table to perma= nent memory if IA-32e Mode not actived.=0A= + @retval EFI_OUT_OF_RESOURCES The PageTable could not be migrated due = to lack of available memory.=0A= +=0A= +**/=0A= +EFI_STATUS=0A= +MigratePageTable (=0A= + VOID=0A= + )=0A= +{=0A= + EFI_STATUS Status;=0A= + IA32_CR4 Cr4;=0A= + BOOLEAN Page5LevelSupport;=0A= + UINT32 RegEax;=0A= + CPUID_EXTENDED_CPU_SIG_EDX RegEdx;=0A= + BOOLEAN Page1GSupport;=0A= + PAGING_MODE PagingMode;=0A= + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;=0A= + UINT32 MaxExtendedFunctionId;=0A= + UINTN PageTable;=0A= + EFI_PHYSICAL_ADDRESS Buffer;=0A= + UINTN BufferSize;=0A= + IA32_MAP_ATTRIBUTE MapAttribute;=0A= + IA32_MAP_ATTRIBUTE MapMask;=0A= +=0A= + VirPhyAddressSize.Uint32 =3D 0;=0A= + PageTable =3D 0;=0A= + BufferSize =3D 0;=0A= + MapAttribute.Uint64 =3D 0;=0A= + MapMask.Uint64 =3D MAX_UINT64;=0A= + MapAttribute.Bits.Present =3D 1;=0A= + MapAttribute.Bits.ReadWrite =3D 1;=0A= +=0A= + //=0A= + // Check Page5Level Support or not.=0A= + //=0A= + Cr4.UintN =3D AsmReadCr4 ();=0A= + Page5LevelSupport =3D (Cr4.Bits.LA57 ? TRUE : FALSE);=0A= +=0A= + //=0A= + // Check Page1G Support or not.=0A= + //=0A= + Page1GSupport =3D FALSE;=0A= + AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);=0A= + if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) {=0A= + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx.Uint32);= =0A= + if (RegEdx.Bits.Page1GB !=3D 0) {=0A= + Page1GSupport =3D TRUE;=0A= + }=0A= + }=0A= +=0A= + //=0A= + // Decide Paging Mode according Page5LevelSupport & Page1GSupport.=0A= + //=0A= + if (Page5LevelSupport) {=0A= + PagingMode =3D Page1GSupport ? Paging5Level1GB : Paging5Level;=0A= + } else {=0A= + PagingMode =3D Page1GSupport ? Paging4Level1GB : Paging4Level;=0A= + }=0A= +=0A= + //=0A= + // Get Maximum Physical Address Bits=0A= + // Get the number of address lines; Maximum Physical Address is 2^Physic= alAddressBits - 1.=0A= + // If CPUID does not supported, then use a max value of 36 as per SDM 3A= , 4.1.4.=0A= + //=0A= + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunctionId, NULL, NULL, N= ULL);=0A= + if (MaxExtendedFunctionId >=3D CPUID_VIR_PHY_ADDRESS_SIZE) {=0A= + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL,= NULL, NULL);=0A= + } else {=0A= + VirPhyAddressSize.Bits.PhysicalAddressBits =3D 36;=0A= + }=0A= +=0A= + if ((PagingMode =3D=3D Paging4Level1GB) || (PagingMode =3D=3D Paging4Lev= el)) {=0A= + //=0A= + // The max lineaddress bits is 48 for 4 level page table.=0A= + //=0A= + VirPhyAddressSize.Bits.PhysicalAddressBits =3D MIN (VirPhyAddressSize.= Bits.PhysicalAddressBits, 48);=0A= + }=0A= +=0A= + //=0A= + // Get required buffer size for the pagetable that will be created.=0A= + //=0A= + Status =3D PageTableMap (&PageTable, PagingMode, 0, &BufferSize, 0, LShi= ftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits), &MapAttribute, &MapM= ask, NULL);=0A= + ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL);=0A= + if (Status !=3D EFI_BUFFER_TOO_SMALL) {=0A= + return Status;=0A= + }=0A= +=0A= + //=0A= + // Allocate required Buffer.=0A= + //=0A= + Status =3D PeiServicesAllocatePages (=0A= + EfiBootServicesData,=0A= + EFI_SIZE_TO_PAGES (BufferSize),=0A= + &Buffer=0A= + );=0A= + if (EFI_ERROR (Status)) {=0A= + return EFI_OUT_OF_RESOURCES;=0A= + }=0A= +=0A= + //=0A= + // Create PageTable in permanent memory.=0A= + //=0A= + Status =3D PageTableMap (&PageTable, PagingMode, (VOID *)(UINTN)Buffer, = &BufferSize, 0, LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits), = &MapAttribute, &MapMask, NULL);=0A= + ASSERT_EFI_ERROR (Status);=0A= + if (EFI_ERROR (Status) || (PageTable =3D=3D 0)) {=0A= + return EFI_OUT_OF_RESOURCES;=0A= + }=0A= +=0A= + //=0A= + // Write the Pagetable to CR3.=0A= + //=0A= + AsmWriteCr3 (PageTable);=0A= +=0A= + DEBUG ((=0A= + DEBUG_INFO,=0A= + "MigratePageTable: Created PageTable =3D 0x%lx, BufferSize =3D %x, Pag= ingMode =3D 0x%lx, Support Max Physical Address Bits =3D %d\n",=0A= + PageTable,=0A= + BufferSize,=0A= + (UINTN)PagingMode,=0A= + VirPhyAddressSize.Bits.PhysicalAddressBits=0A= + ));=0A= +=0A= + return Status;=0A= +}=0A= +=0A= //=0A= // These are IDT entries pointing to 10:FFFFFFE4h.=0A= //=0A= UINT64 mIdtEntryTemplate =3D 0xffff8e000010ffe4ULL;=0A= =0A= @@ -451,10 +580,11 @@ SecTemporaryRamDone (=0A= EFI_STATUS Status2;=0A= UINTN Index;=0A= BOOLEAN State;=0A= EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor;=0A= REPUBLISH_SEC_PPI_PPI *RepublishSecPpiPpi;=0A= + IA32_CR0 Cr0;=0A= =0A= //=0A= // Republish Sec Platform Information(2) PPI=0A= //=0A= RepublishSecPlatformInformationPpi ();=0A= @@ -492,10 +622,27 @@ SecTemporaryRamDone (=0A= if (PcdGetBool (PcdMigrateTemporaryRamFirmwareVolumes)) {=0A= Status =3D MigrateGdt ();=0A= ASSERT_EFI_ERROR (Status);=0A= }=0A= =0A= + //=0A= + // Migrate page table to permanent memory mapping entire physical addres= s space if CR0.PG is set.=0A= + //=0A= + Cr0.UintN =3D AsmReadCr0 ();=0A= + if (Cr0.Bits.PG !=3D 0) {=0A= + //=0A= + // Assume CPU runs in 64bit mode if paging is enabled.=0A= + //=0A= + ASSERT (sizeof (UINTN) =3D=3D sizeof (UINT64));=0A= +=0A= + Status =3D MigratePageTable ();=0A= + if (EFI_ERROR (Status)) {=0A= + DEBUG ((DEBUG_ERROR, "SecTemporaryRamDone: Failed to migrate page ta= ble to permanent memory: %r.\n", Status));=0A= + CpuDeadLoop ();=0A= + }=0A= + }=0A= +=0A= //=0A= // Disable Temporary RAM after Stack and Heap have been migrated at this= point.=0A= //=0A= SecPlatformDisableTemporaryMemory ();=0A= =0A= diff --git a/UefiCpuPkg/SecCore/SecMain.h b/UefiCpuPkg/SecCore/SecMain.h=0A= index 880e6cd1b8..b50d96e45b 100644=0A= --- a/UefiCpuPkg/SecCore/SecMain.h=0A= +++ b/UefiCpuPkg/SecCore/SecMain.h=0A= @@ -17,10 +17,11 @@=0A= #include =0A= #include =0A= =0A= #include =0A= =0A= +#include =0A= #include =0A= #include =0A= #include =0A= #include =0A= #include =0A= @@ -30,10 +31,13 @@=0A= #include =0A= #include =0A= #include =0A= #include =0A= #include =0A= +#include =0A= +#include =0A= +#include =0A= =0A= #define SEC_IDT_ENTRY_COUNT 34=0A= =0A= typedef struct _SEC_IDT_TABLE {=0A= //=0A= --=0A= 2.16.2.windows.1=0A= =0A=