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Wed, 10 Apr 2024 07:56:42 +0000 From: "Ni, Ray" To: "Liu, Zhiguang" , "devel@edk2.groups.io" CC: "Chiu, Chasel" , "Desimone, Nathaniel L" , "Duggapu, Chinni B" , "Zeng, Star" , "Kuo, Ted" , "S, Ashraf Ali" , "Susovan Mohapatra" Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Optional Plugin for FSP SecCore/PeiCore Rebasing Thread-Topic: [PATCH v2] IntelFsp2Pkg: Optional Plugin for FSP SecCore/PeiCore Rebasing Thread-Index: AQHaixXktLsFixDs40mPg1UQ5r9K57FhIv1i Date: Wed, 10 Apr 2024 07:56:42 +0000 Message-ID: References: <20240410070808.3995-1-zhiguang.liu@intel.com> In-Reply-To: <20240410070808.3995-1-zhiguang.liu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MN6PR11MB8244:EE_|DS0PR11MB8084:EE_ x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: C7UOgbefGRuzguKKUbi1HWbVTMocFY5SprwlwUK2XS6JMaNs82yHlAdznyt3+U+kVrndUEallNf7fvb612GOhA+Kl6V3rMUa8fm53yDXrQiroVfwiyctCZQ4QepZjlh+rCeudzze75HDUiBhls5vs35gD3OcwkVt85bqgrxv+OsyeDXxRoJ1GOI9hPasb37lZPZw98Mzg/wj2SKpsEIVecMT0bLtQpjNPL3GgmHjk7GcCLdWFXjfAS6T9YcykPkjdDjW2kygevgXNO+W0hrP7Xy4/LmuJp/JafxcCJFlwqH6wxWFCo8IQW9x3fLqXC0rsLHOsp5sadxrokzJamcFc/oiqYvyvm84jN6G8Q5be85uit7YxX32jPsh2bwbWDtNneV2Q2JEgb/iXzb60hVTIv6Tn/BNvPgUC340c4p32hFZHJX51I/oazs9ku44fhSEiCTQQCUGN/Q81OmIfXQ/wC4FwYIlfEkMPMrAxu6ovXbtFu/EfW2f93QNUTtfJLUo3rDPhsKMQ9DmTSMdeq/+Ic0mXZWrNnfs6zrCzrT1YgZff0EKjXHTixtHlsetTC3uo3J089PmUQdzzyp0TQ6k8qRfFU0t5YGZfFUbYL7DtfbPHCao47PNkT3/8cd3denQgjv19V1Zn34fWFxyJhy4NBKjPAmmMmlzD9uQ37BWmZM= x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?pxt8gYCZnRrwzYm3dnHGtkr3IIESArTIBPAZwStKsCFC3BcAVSX78mCauxut?= =?us-ascii?Q?tQNUkZd8uF+zSe8ogPIfOMWlkXiAwhqgIkCUcFfB/oRb5GccbU0TNomkN+sE?= =?us-ascii?Q?YOeCHBUnST742eQ/JBokKMNZQcURgFvtW2K3UKS8FGHqwGy2mzaKd/uJTUgy?= =?us-ascii?Q?dPAtPbzFcdro3tQxgV+7bKPfd09Yxt2FqeQKrPio+y4cDVzJVOqC3t1a1o5z?= =?us-ascii?Q?pc/CZY8J85wfQNR5noAjlnupQsRiMw7lJlLl7aOMWHH0WpsGj4ikOG2KHjWp?= =?us-ascii?Q?3eSlweyXqxy4zRpu3isS5Dm7uYrppCKx3doFn1Oqf5xrOCcQkaMSwDL5U4ra?= =?us-ascii?Q?cklSUemfZNNJbJzhHSxzAit7G+rI+w9la6YOpO1rB7IiiTvEU5u6hIWJ+GmI?= =?us-ascii?Q?5MT7AWBBgaiQXTn+3wgYT5B0djGotHLxgvTuL2+58R2jKVNrpUiJu0V19iZh?= =?us-ascii?Q?kJB/59QOjQDA9Z8/NgDU2/xlGxJ6gR2ouzAH47053hCAwBeMcraFVx49o5n2?= =?us-ascii?Q?XD6pXel5TdKMHhk5vlJdZBWNnr3Cn1WlXIU2EBRB6EMIIa2Orwdxor0qlyah?= =?us-ascii?Q?FX4LHzBTL3gez8oSJWUUi/oolHYBhqn6Iv/EMMUMKutIZssg1hJp+BwpTwdb?= =?us-ascii?Q?jQy/5wYI0Qurw5GtaE54aUU4sn1wPtb43y0xcGTw9Moe4rQr1IJV3LW00V9Y?= =?us-ascii?Q?3dYdIqrR4cjYJ7nTWVapddedFTizdFBMBSUiAXPnhupSyEXM/sABmEHpa7ja?= =?us-ascii?Q?jSVmEBP6KHJj9EpqHAffu0vhgqQD3g4ho1/OdvJb24jyT+7BsuVtVE8a5je/?= =?us-ascii?Q?Xn/LLJxUKS0vwzFFc5bPjC/JIvUp6hYuRihT2a/vr9kUrDQS0p0gN0reD49t?= =?us-ascii?Q?DQdxnvEdtbswTw05wKgnXbhcuLWZwBQNVDCrmAtkuYYclAZPVmcZLftcF5Mx?= =?us-ascii?Q?Lb6bidB5x6ZH/9/vq+wtsj6FW5c68ZWdrZ2guOmHw/1hZf/sbVodjeIwUUVo?= =?us-ascii?Q?HNw6/2bUl3bzk+/lcCOAXVTq4DdBaCw6z+V0SFZnnY6UiuFpE2exI53y/mri?= =?us-ascii?Q?Nn+RC9G+O3M7nHS75eR6lyvBCxrinYDHRftuFxD6alqqh3AvJvB59Xy/vI8T?= =?us-ascii?Q?yJc2zQsf5YFyc76HHsW+KH66GR1rDMFrdvmV2Glc2W28dgONMI69/3TfZAZ9?= =?us-ascii?Q?fL1AQAvMBSh/eUWZ4Vp79i1xUxHnsg37Tq6X0Igqx1sk/frRGlmpDk04L9F9?= =?us-ascii?Q?4DCH9N0DKsJo+sHvbb9FUPa8rHz39RI5ZwSPs1PnzP1iqKFs0hAW2V8mcfQN?= =?us-ascii?Q?PRoz60aZ6EwEXQ+SC7KvMLTlBlCEfoVGzQyvxfOKVUAgQtivx47aRj2GeXQz?= =?us-ascii?Q?PCFlft9qT3Se9PLCjy+bTtuVDsxB4PyWtpDcmh5NaF8D8viPfChcWsm1K1MZ?= =?us-ascii?Q?0hpeqctlJ5/JxtaS39yjytO2tCF70ErhxJUWMVlFy48V/QGXLWy8Ui2m22B4?= =?us-ascii?Q?4TNSC3H7LkVMfSFkzdEtYCbFt6nrgqQFt4LnsmiaMGFeeySTRkAKHzSOwbuo?= =?us-ascii?Q?aB9CqmOQGE9CaI36CqI=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN6PR11MB8244.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: b838fe5a-d59b-4494-501b-08dc5933c290 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Apr 2024 07:56:42.1938 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: n4VFIIiAwqXjA0h/CcwXiG1fT3ZcxdCCN5ec+1dX+D1iV7y+OaP5R9xok2vkrIG/5zfjK9BoFdEl9KBftU+O/Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR11MB8084 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 10 Apr 2024 00:56:47 -0700 Resent-From: ray.ni@intel.com Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 5Xc3CTCokjeWavdHpanBZbwQx7686176AA= Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN6PR11MB8244C2E8F891653016486B8C8C062MN6PR11MB8244namp_" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=Ax3ccfyc; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io --_000_MN6PR11MB8244C2E8F891653016486B8C8C062MN6PR11MB8244namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni Thanks, Ray ________________________________ From: Liu, Zhiguang Sent: Wednesday, April 10, 2024 15:08 To: devel@edk2.groups.io Cc: Liu, Zhiguang ; Chiu, Chasel ; Desimone, Nathaniel L ; Duggapu, Chi= nni B ; Zeng, Star ; Kuo, = Ted ; S, Ashraf Ali ; Susovan Mo= hapatra ; Ni, Ray Subject: [PATCH v2] IntelFsp2Pkg: Optional Plugin for FSP SecCore/PeiCore R= ebasing Note this plugin only applies to 64-bit PSP This optional plugin is designed to execute before the FSP SecCore to rebase SecCore and PeiCore during runtime. If the FSP binary requires rebasing at runtime, this module should be included within the FSP binary. Additionally, specific patches must be applied to ensure proper functionality. In the absence of this module, manual patching of API offsets within the FSP header is necessary. To illustrate, let's consider a scenario within FSP-S where 'FspSiliconInitEntry' is the initial API to be executed post-rebase. Rather than directly inputting the 'FspSiliconInit' offset into the 'FspSiliconInitEntryOffset' field of the FSP header, the entry point of this module should be used. Furthermore, the 'FspSiliconInit' offset should be placed into 'AsmGetFspOriginalEntry', which signifies the address to which this module will jump. It is also essential to patch the image bases of SecCore and PeiCore to enable the rebasing functionality of this module. The following is an example of how to apply the necessary patches: Patch Address Patch Value PreFspSec:_ModuleEntryPoint - [0x0000] PreFspSec:SecCoreRelativeOff PreFspSec:AsmGetFspSecCoreImageBase - Fsp24SecCoreS:BASE PreFspSec:PeiCoreRelativeOff PreFspSec:AsmGetFspPeiCoreImageBase - PeiCore:BASE PreFspSec:SecEntryRelativeOff PreFspSec:AsmGetFspOriginalEntry - Fsp24SecCoreS:FspSiliconInitApi Cc: Chasel Chiu Cc: Nate DeSimone Cc: Duggapu Chinni B Cc: Star Zeng Cc: Ted Kuo Cc: Ashraf Ali S Cc: Susovan Mohapatra Cc: Ray Ni Signed-off-by: Zhiguang Liu --- IntelFsp2Pkg/IntelFsp2Pkg.dsc | 5 + IntelFsp2Pkg/PreFspSec/PreFspSec.c | 115 ++++++++++++++++++ IntelFsp2Pkg/PreFspSec/PreFspSec.inf | 62 ++++++++++ .../PreFspSec/X64/PreFspSecCommon.nasm | 94 ++++++++++++++ 4 files changed, 276 insertions(+) create mode 100644 IntelFsp2Pkg/PreFspSec/PreFspSec.c create mode 100644 IntelFsp2Pkg/PreFspSec/PreFspSec.inf create mode 100644 IntelFsp2Pkg/PreFspSec/X64/PreFspSecCommon.nasm diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index f236a7010b..a2cc29c940 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -33,6 +33,8 @@ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf DebugDeviceLib|IntelFsp2Pkg/Library/BaseDebugDeviceLibNull/BaseDebugDevi= ceLibNull.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf # FSP override DebugLib|IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/BaseFspDebugLibS= erialPort.inf @@ -75,6 +77,9 @@ IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf +[Components.X64] + IntelFsp2Pkg/PreFspSec/PreFspSec.inf + [PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x1f gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046 diff --git a/IntelFsp2Pkg/PreFspSec/PreFspSec.c b/IntelFsp2Pkg/PreFspSec/Pr= eFspSec.c new file mode 100644 index 0000000000..b3b52b8064 --- /dev/null +++ b/IntelFsp2Pkg/PreFspSec/PreFspSec.c @@ -0,0 +1,115 @@ +/** @file + + Copyright (c) 2024, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include "Guid/FspHeaderFile.h" +#include +#include +#include +#include + +/** + This fuction gets SecCore image base + + @return SecCore image base, or zero if no patch in nasm code + +**/ +UINTN +EFIAPI +AsmGetFspSecCoreImageBase ( + VOID + ); + +/** + This fuction gets PeiCore image base + + @return PeiCore image base, or zero if no patch in nasm code + +**/ +UINTN +EFIAPI +AsmGetFspPeiCoreImageBase ( + VOID + ); + +/** + Relocate Pe/Te Image + + @param[in] ImageBaseAddress Image base address + + @retval EFI_SUCCESS Image is relocated successfully + @retval Others Image is not relocated successfully +**/ +EFI_STATUS +RelocatePeTeImage ( + UINT64 ImageBaseAddress + ) +{ + RETURN_STATUS Status; + PE_COFF_LOADER_IMAGE_CONTEXT ImageContext; + + ZeroMem (&ImageContext, sizeof (ImageContext)); + + ImageContext.Handle =3D (VOID *)ImageBaseAddress; + ImageContext.ImageRead =3D PeCoffLoaderImageReadFromMemory; + + Status =3D PeCoffLoaderGetImageInfo (&ImageContext); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + ImageContext.ImageAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)ImageBaseAddr= ess; + + // + // rebase the image + // + Status =3D PeCoffLoaderRelocateImage (&ImageContext); + + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This function will patch the Sec Core and Pei Core in current FSP. +**/ +VOID +EFIAPI +FspRelocateSecAndPeiCore ( + VOID + ) +{ + UINT64 SecCoreImageBase; + UINT64 PeiCoreImageBase; + EFI_STATUS Status; + + // + // Get SecCore image, and rebase it + // + SecCoreImageBase =3D AsmGetFspSecCoreImageBase (); + if (SecCoreImageBase !=3D 0) { + Status =3D RelocatePeTeImage (SecCoreImageBase); + if (!EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "Sec Core is relocated successfully\n")); + } else { + DEBUG ((DEBUG_WARN, "Sec Core is not relocated. May have issue later= \n")); + } + } + + // + // Get PeiCore image, and rebase it + // + PeiCoreImageBase =3D AsmGetFspPeiCoreImageBase (); + if (PeiCoreImageBase !=3D 0) { + Status =3D RelocatePeTeImage (PeiCoreImageBase); + if (!EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "Pei Core is relocated successfully\n")); + } else { + DEBUG ((DEBUG_INFO, "Pei Core is not relocated. May have issue later= \n")); + } + } +} diff --git a/IntelFsp2Pkg/PreFspSec/PreFspSec.inf b/IntelFsp2Pkg/PreFspSec/= PreFspSec.inf new file mode 100644 index 0000000000..1f19ef85eb --- /dev/null +++ b/IntelFsp2Pkg/PreFspSec/PreFspSec.inf @@ -0,0 +1,62 @@ +## @file +# Optional Plugin for FSP SecCore/PeiCore Rebasing. +# Note this plugin only applies to 64-bit PSP +# +# This optional plugin is designed to execute before the FSP SecCore to r= ebase +# SecCore and PeiCore during runtime. If the FSP binary requires rebasing= at runtime, +# this module should be included within the FSP binary. +# Additionally, specific patches must be applied to ensure proper functio= nality. +# +# In the absence of this module, manual patching of API offsets within th= e FSP header +# is necessary. To illustrate, let's consider a scenario within FSP-S whe= re +# 'FspSiliconInitEntry' is the initial API to be executed post-rebase. +# Rather than directly inputting the 'FspSiliconInit' offset into the +# 'FspSiliconInitEntryOffset' field of the FSP header, the entry point of= this module +# should be used. Furthermore, the 'FspSiliconInit' offset should be plac= ed +# into 'AsmGetFspOriginalEntry', which signifies the address to which thi= s module will jump. +# It is also essential to patch the image bases of SecCore and PeiCore to= enable the +# rebasing functionality of this module. +# The following is an example of how to apply the necessary patches: +# Patch Address Patch Value +# PreFspSec:_ModuleEntryPoint - [0x0000] +# PreFspSec:SecCoreRelativeOff PreFspSec:AsmGetFspSecCoreImageBase - = Fsp24SecCoreS:BASE +# PreFspSec:PeiCoreRelativeOff PreFspSec:AsmGetFspPeiCoreImageBase - P= eiCore:BASE +# PreFspSec:SecEntryRelativeOff PreFspSec:AsmGetFspOriginalEntry - Fsp2= 4SecCoreS:FspSiliconInitApi +# +# Copyright (c) 2024, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PreFspSec + FILE_GUID =3D ef13ad51-2bab-4333-bd96-e01c79f2d313 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D X64 +# + +[Sources] + PreFspSec.c + +[Sources.X64] + + X64/PreFspSecCommon.nasm + +[Packages] + MdePkg/MdePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + BaseLib + CpuLib + PeCoffLib diff --git a/IntelFsp2Pkg/PreFspSec/X64/PreFspSecCommon.nasm b/IntelFsp2Pkg= /PreFspSec/X64/PreFspSecCommon.nasm new file mode 100644 index 0000000000..f1386edb3f --- /dev/null +++ b/IntelFsp2Pkg/PreFspSec/X64/PreFspSecCommon.nasm @@ -0,0 +1,94 @@ +;; @file +; Run before FSP SecCore to rebase SecCore and PeiCore +; +; Copyright (c) 2024, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + DEFAULT REL + SECTION .text + +%include "PushPopRegsNasm.inc" + +; +; Following functions will be provided in C +; +extern ASM_PFX(FspRelocateSecAndPeiCore) + +;-------------------------------------------------------------------------= --- +; _ModuleEntryPoint API +; +; This is the PreFspSec entry point to rebase and resume the FSP execution +; Only rax register is modified. +; +;-------------------------------------------------------------------------= --- +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + PUSHA_64 + call ASM_PFX(FspRelocateSecAndPeiCore) + POPA_64 + call ASM_PFX(AsmGetFspOriginalEntry) + jmp rax + + +;-------------------------------------------------------------------------= --- +; This fuction gets SecCore image base +; +; UINTN +; EFIAPI +; AsmGetFspSecCoreImageBase ( +; VOID +; ) +;-------------------------------------------------------------------------= --- +global ASM_PFX(AsmGetFspSecCoreImageBase ) +ASM_PFX(AsmGetFspSecCoreImageBase ): + lea rax, [ASM_PFX(AsmGetFspSecCoreImageBase )] + mov rcx, rax + xor rdx, rdx + DB 0x48, 0x2d ; sub rax, 0x???????? +global ASM_PFX(SecCoreRelativeOff) +ASM_PFX(SecCoreRelativeOff): + DD 0 ; This value can be patched by the build= script if need to rebase SecCore + xchg rax, rcx ; Before exchange, RAX =3D SecCore image= base at runtime, RCX =3D AsmGetFspSecCoreImageBase runtime address + ; After exchange, RCX =3D SecCore image= base at runtime, RAX =3D AsmGetFspSecCoreImageBase runtime address. + ; If SecCoreRelativeOff is not patched, = RCX =3D RAX =3D AsmGetFspSecCoreImageBase runtime address. This happens whe= n there is no SecCore in the binary. + CMPXCHG rcx, rdx ; if (rcx =3D=3D rax) {rcx =3D rdx} else= {rax =3D rcx} + mov rax, rcx + ret + +;-------------------------------------------------------------------------= --- +; This fuction gets PeiCore Image Base +; +; UINTN +; EFIAPI +; AsmGetFspPeiCoreImageBase ( +; VOID +; ) +;-------------------------------------------------------------------------= --- +global ASM_PFX(AsmGetFspPeiCoreImageBase) +ASM_PFX(AsmGetFspPeiCoreImageBase): + lea rax, [ASM_PFX(AsmGetFspPeiCoreImageBase)] + mov rcx, rax + xor rdx, rdx + DB 0x48, 0x2d ; sub rax, 0x???????? +global ASM_PFX(PeiCoreRelativeOff) +ASM_PFX(PeiCoreRelativeOff): + DD 0 ; This value can be patched by the build= script if need to rebase PeiCore + xchg rax, rcx ; Before exchange, RAX =3D PeiCore image= base at runtime, RCX =3D AsmGetFspPeiCoreImageBase runtime address + ; After exchange, RCX =3D PeiCore image= base at runtime, RAX =3D AsmGetFspPeiCoreImageBase runtime address. + ; If PeiCoreRelativeOff is not patched, = RCX =3D RAX =3D AsmGetFspPeiCoreImageBase runtime address. This happens whe= n there is no SecCore in the binary. + CMPXCHG rcx, rdx ; if (rcx =3D=3D rax) {rcx =3D rdx} else= {rax =3D rcx} + mov rax, rcx + ret + +;-------------------------------------------------------------------------= --- +; This fuction gets Fsp Original entry +; Only Rax register is used +;-------------------------------------------------------------------------= --- +global ASM_PFX(AsmGetFspOriginalEntry) +ASM_PFX(AsmGetFspOriginalEntry): + lea rax, [ASM_PFX(AsmGetFspOriginalEntry)] + DB 0x48, 0x2d ; sub rax, 0x???????? +global ASM_PFX(SecEntryRelativeOff) +ASM_PFX(SecEntryRelativeOff): + DD 0x12345678 ; This value must be patched by the buil= d script + ret -- 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117579): https://edk2.groups.io/g/devel/message/117579 Mute This Topic: https://groups.io/mt/105437669/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_MN6PR11MB8244C2E8F891653016486B8C8C062MN6PR11MB8244namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Reviewed-by: Ray Ni <ray.ni@intel.com>

Thanks,
Ray
From: Liu, Zhiguang <zhi= guang.liu@intel.com>
Sent: Wednesday, April 10, 2024 15:08
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Liu, Zhiguang <zhiguang.liu@intel.com>; Chiu, Chasel <c= hasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@in= tel.com>; Duggapu, Chinni B <chinni.b.duggapu@intel.com>; Zeng, St= ar <star.zeng@intel.com>; Kuo, Ted <ted.kuo@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com>; Susovan Mohapatra <susova= n.mohapatra@intel.com>; Ni, Ray <ray.ni@intel.com>
Subject: [PATCH v2] IntelFsp2Pkg: Optional Plugin for FSP SecCore/Pe= iCore Rebasing
 
Note this plugin only applies to 64-bit PSP
This optional plugin is designed to execute before the FSP SecCore to
rebase SecCore and PeiCore during runtime. If the FSP binary requires
rebasing at runtime, this module should be included within the FSP
binary. Additionally, specific patches must be applied to ensure proper
functionality. In the absence of this module, manual patching of API
offsets within the FSP header is necessary. To illustrate, let's
consider a scenario within FSP-S where 'FspSiliconInitEntry' is the
initial API to be executed post-rebase. Rather than directly inputting
the 'FspSiliconInit' offset into the 'FspSiliconInitEntryOffset' field
of the FSP header, the entry point of this module should be used.
Furthermore, the 'FspSiliconInit' offset should be placed into
'AsmGetFspOriginalEntry', which signifies the address to which this
module will jump.
It is also essential to patch the image bases of SecCore and PeiCore
to enable the rebasing functionality of this module.
The following is an example of how to apply the necessary patches:
Patch Address          &n= bsp;        Patch Value
<FspSiliconInitEntryOffset>     PreFspSec:_Module= EntryPoint - [0x0000]
PreFspSec:SecCoreRelativeOff    PreFspSec:AsmGetFspSecCoreIm= ageBase
            &nb= sp;            =             - Fsp24S= ecCoreS:BASE
PreFspSec:PeiCoreRelativeOff    PreFspSec:AsmGetFspPeiCoreIm= ageBase
            &nb= sp;            =             - PeiCor= e:BASE
PreFspSec:SecEntryRelativeOff   PreFspSec:AsmGetFspOriginalEntry<= br>             &nb= sp;            =             - Fsp24S= ecCoreS:FspSiliconInitApi

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ted Kuo <ted.kuo@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Cc: Susovan Mohapatra <susovan.mohapatra@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
 IntelFsp2Pkg/IntelFsp2Pkg.dsc      &nbs= p;          |   5 +<= br>  IntelFsp2Pkg/PreFspSec/PreFspSec.c      = ;      | 115 ++++++++++++++++++
 IntelFsp2Pkg/PreFspSec/PreFspSec.inf     &nb= sp;    |  62 ++++++++++
 .../PreFspSec/X64/PreFspSecCommon.nasm     &= nbsp;  |  94 ++++++++++++++
 4 files changed, 276 insertions(+)
 create mode 100644 IntelFsp2Pkg/PreFspSec/PreFspSec.c
 create mode 100644 IntelFsp2Pkg/PreFspSec/PreFspSec.inf
 create mode 100644 IntelFsp2Pkg/PreFspSec/X64/PreFspSecCommon.nasm
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc<= br> index f236a7010b..a2cc29c940 100644
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc
@@ -33,6 +33,8 @@
   SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialP= ortLibNull.inf
   ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull= /BaseReportStatusCodeLibNull.inf
   DebugDeviceLib|IntelFsp2Pkg/Library/BaseDebugDeviceLibNull/Bas= eDebugDeviceLibNull.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/Ba= sePeCoffExtraActionLibNull.inf
 
   # FSP override
   DebugLib|IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/BaseFs= pDebugLibSerialPort.inf
@@ -75,6 +77,9 @@
   IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf
   IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf
 
+[Components.X64]
+  IntelFsp2Pkg/PreFspSec/PreFspSec.inf
+
 [PcdsFixedAtBuild.common]
   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x1f
   gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046 diff --git a/IntelFsp2Pkg/PreFspSec/PreFspSec.c b/IntelFsp2Pkg/PreFspSec/Pr= eFspSec.c
new file mode 100644
index 0000000000..b3b52b8064
--- /dev/null
+++ b/IntelFsp2Pkg/PreFspSec/PreFspSec.c
@@ -0,0 +1,115 @@
+/** @file
+
+  Copyright (c) 2024, Intel Corporation. All rights reserved.<BR&g= t;
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseLib.h>
+#include "Guid/FspHeaderFile.h"
+#include <Library/PeCoffLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+
+/**
+  This fuction gets SecCore image base
+
+  @return   SecCore image base, or zero if no patch in nasm= code
+
+**/
+UINTN
+EFIAPI
+AsmGetFspSecCoreImageBase  (
+  VOID
+  );
+
+/**
+  This fuction gets PeiCore image base
+
+  @return   PeiCore image base, or zero if no patch in nasm= code
+
+**/
+UINTN
+EFIAPI
+AsmGetFspPeiCoreImageBase (
+  VOID
+  );
+
+/**
+  Relocate Pe/Te Image
+
+  @param[in] ImageBaseAddress   Image base address
+
+  @retval EFI_SUCCESS        =    Image is relocated successfully
+  @retval Others         = ;       Image is not relocated successfully +**/
+EFI_STATUS
+RelocatePeTeImage (
+  UINT64  ImageBaseAddress
+  )
+{
+  RETURN_STATUS         =         Status;
+  PE_COFF_LOADER_IMAGE_CONTEXT  ImageContext;
+
+  ZeroMem (&ImageContext, sizeof (ImageContext));
+
+  ImageContext.Handle    =3D (VOID *)ImageBaseAddress;=
+  ImageContext.ImageRead =3D PeCoffLoaderImageReadFromMemory;
+
+  Status =3D PeCoffLoaderGetImageInfo (&ImageContext);
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+  }
+
+  ImageContext.ImageAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)ImageBas= eAddress;
+
+  //
+  // rebase the image
+  //
+  Status =3D PeCoffLoaderRelocateImage (&ImageContext);
+
+  ASSERT_EFI_ERROR (Status);
+  return Status;
+}
+
+/**
+  This function will patch the Sec Core and Pei Core in current FSP.<= br> +**/
+VOID
+EFIAPI
+FspRelocateSecAndPeiCore (
+  VOID
+  )
+{
+  UINT64      SecCoreImageBase;
+  UINT64      PeiCoreImageBase;
+  EFI_STATUS  Status;
+
+  //
+  // Get SecCore image, and rebase it
+  //
+  SecCoreImageBase =3D AsmGetFspSecCoreImageBase  ();
+  if (SecCoreImageBase !=3D 0) {
+    Status =3D RelocatePeTeImage (SecCoreImageBase);
+    if (!EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_INFO, "Sec Core is reloc= ated successfully\n"));
+    } else {
+      DEBUG ((DEBUG_WARN, "Sec Core is not r= elocated. May have issue later\n"));
+    }
+  }
+
+  //
+  // Get PeiCore image, and rebase it
+  //
+  PeiCoreImageBase =3D AsmGetFspPeiCoreImageBase ();
+  if (PeiCoreImageBase !=3D 0) {
+    Status =3D RelocatePeTeImage (PeiCoreImageBase);
+    if (!EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_INFO, "Pei Core is reloc= ated successfully\n"));
+    } else {
+      DEBUG ((DEBUG_INFO, "Pei Core is not r= elocated. May have issue later\n"));
+    }
+  }
+}
diff --git a/IntelFsp2Pkg/PreFspSec/PreFspSec.inf b/IntelFsp2Pkg/PreFspSec/= PreFspSec.inf
new file mode 100644
index 0000000000..1f19ef85eb
--- /dev/null
+++ b/IntelFsp2Pkg/PreFspSec/PreFspSec.inf
@@ -0,0 +1,62 @@
+## @file
+#  Optional Plugin for FSP SecCore/PeiCore Rebasing.
+#  Note this plugin only applies to 64-bit PSP
+#
+#  This optional plugin is designed to execute before the FSP SecCore= to rebase
+#  SecCore and PeiCore during runtime. If the FSP binary requires reb= asing at runtime,
+#  this module should be included within the FSP binary.
+#  Additionally, specific patches must be applied to ensure proper fu= nctionality.
+#
+#  In the absence of this module, manual patching of API offsets with= in the FSP header
+#  is necessary. To illustrate, let's consider a scenario within FSP-= S where
+#  'FspSiliconInitEntry' is the initial API to be executed post-rebas= e.
+#  Rather than directly inputting the 'FspSiliconInit' offset into th= e
+#  'FspSiliconInitEntryOffset' field of the FSP header, the entry poi= nt of this module
+#  should be used. Furthermore, the 'FspSiliconInit' offset should be= placed
+#  into 'AsmGetFspOriginalEntry', which signifies the address to whic= h this module will jump.
+#  It is also essential to patch the image bases of SecCore and PeiCo= re to enable the
+#  rebasing functionality of this module.
+#  The following is an example of how to apply the necessary patches:=
+#  Patch Address         = ;          Patch Value
+#  <FspSiliconInitEntryOffset>     PreFspSe= c:_ModuleEntryPoint - [0x0000]
+#  PreFspSec:SecCoreRelativeOff    PreFspSec:AsmGetFsp= SecCoreImageBase  - Fsp24SecCoreS:BASE
+#  PreFspSec:PeiCoreRelativeOff    PreFspSec:AsmGetFsp= PeiCoreImageBase - PeiCore:BASE
+#  PreFspSec:SecEntryRelativeOff   PreFspSec:AsmGetFspOrigi= nalEntry - Fsp24SecCoreS:FspSiliconInitApi
+#
+#  Copyright (c) 2024, Intel Corporation. All rights reserved.<BR&= gt;
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION         &n= bsp;          =3D 0x00010005 +  BASE_NAME         &nbs= p;            =3D Pr= eFspSec
+  FILE_GUID         &nbs= p;            =3D ef= 13ad51-2bab-4333-bd96-e01c79f2d313
+  MODULE_TYPE         &n= bsp;          =3D SEC
+  VERSION_STRING         = ;        =3D 1.0
+
+#
+# The following information is for reference only and not required by the = build tools.
+#
+#  VALID_ARCHITECTURES        = ;   =3D X64
+#
+
+[Sources]
+  PreFspSec.c
+
+[Sources.X64]
+
+  X64/PreFspSecCommon.nasm
+
+[Packages]
+  MdePkg/MdePkg.dec
+  IntelFsp2Pkg/IntelFsp2Pkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseMemoryLib
+  DebugLib
+  BaseLib
+  CpuLib
+  PeCoffLib
diff --git a/IntelFsp2Pkg/PreFspSec/X64/PreFspSecCommon.nasm b/IntelFsp2Pkg= /PreFspSec/X64/PreFspSecCommon.nasm
new file mode 100644
index 0000000000..f1386edb3f
--- /dev/null
+++ b/IntelFsp2Pkg/PreFspSec/X64/PreFspSecCommon.nasm
@@ -0,0 +1,94 @@
+;; @file
+;  Run before FSP SecCore to rebase SecCore and PeiCore
+;
+; Copyright (c) 2024, Intel Corporation. All rights reserved.<BR> +; SPDX-License-Identifier: BSD-2-Clause-Patent
+;;
+    DEFAULT  REL
+    SECTION .text
+
+%include    "PushPopRegsNasm.inc"
+
+;
+; Following functions will be provided in C
+;
+extern ASM_PFX(FspRelocateSecAndPeiCore)
+
+;-------------------------------------------------------------------------= ---
+; _ModuleEntryPoint API
+;
+; This is the PreFspSec entry point to rebase and resume the FSP execution=
+; Only rax register is modified.
+;
+;-------------------------------------------------------------------------= ---
+global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+  PUSHA_64
+  call   ASM_PFX(FspRelocateSecAndPeiCore)
+  POPA_64
+  call   ASM_PFX(AsmGetFspOriginalEntry)
+  jmp    rax
+
+
+;-------------------------------------------------------------------------= ---
+; This fuction gets SecCore image base
+;
+; UINTN
+; EFIAPI
+; AsmGetFspSecCoreImageBase (
+;   VOID
+;   )
+;-------------------------------------------------------------------------= ---
+global ASM_PFX(AsmGetFspSecCoreImageBase )
+ASM_PFX(AsmGetFspSecCoreImageBase ):
+   lea   rax, [ASM_PFX(AsmGetFspSecCoreImageBase )] +   mov   rcx, rax
+   xor   rdx, rdx
+   DB    0x48, 0x2d     =           ; sub rax, 0x???????= ?
+global ASM_PFX(SecCoreRelativeOff)
+ASM_PFX(SecCoreRelativeOff):
+   DD    0      &nb= sp;            =      ; This value can be patched by the build script if= need to rebase SecCore
+   xchg    rax, rcx     =           ; Before exchange, R= AX =3D SecCore image base at runtime, RCX =3D AsmGetFspSecCoreImageBase run= time address          &nb= sp;  
+            &n= bsp;            = ;         ; After exchange,  R= CX =3D SecCore image base at runtime, RAX =3D AsmGetFspSecCoreImageBase run= time address.
+            &n= bsp;            = ;         ; If SecCoreRelativeOff i= s not patched, RCX =3D RAX =3D AsmGetFspSecCoreImageBase runtime address. T= his happens when there is no SecCore in the binary.
+   CMPXCHG rcx, rdx       &nb= sp;       ; if (rcx =3D=3D rax) {rcx =3D rdx}= else {rax =3D rcx}
+   mov     rax, rcx
+   ret
+
+;-------------------------------------------------------------------------= ---
+; This fuction gets PeiCore Image Base
+;
+; UINTN
+; EFIAPI
+; AsmGetFspPeiCoreImageBase (
+;   VOID
+;   )
+;-------------------------------------------------------------------------= ---
+global ASM_PFX(AsmGetFspPeiCoreImageBase)
+ASM_PFX(AsmGetFspPeiCoreImageBase):
+   lea   rax, [ASM_PFX(AsmGetFspPeiCoreImageBase)]
+   mov   rcx, rax
+   xor   rdx, rdx
+   DB    0x48, 0x2d     =           ; sub rax, 0x???????= ?
+global ASM_PFX(PeiCoreRelativeOff)
+ASM_PFX(PeiCoreRelativeOff):
+   DD    0      &nb= sp;            =      ; This value can be patched by the build script if= need to rebase PeiCore
+   xchg    rax, rcx     =           ; Before exchange, R= AX =3D PeiCore image base at runtime, RCX =3D AsmGetFspPeiCoreImageBase run= time address          &nb= sp;  
+            &n= bsp;            = ;         ; After exchange,  R= CX =3D PeiCore image base at runtime, RAX =3D AsmGetFspPeiCoreImageBase run= time address.
+            &n= bsp;            = ;         ; If PeiCoreRelativeOff i= s not patched, RCX =3D RAX =3D AsmGetFspPeiCoreImageBase runtime address. T= his happens when there is no SecCore in the binary.
+   CMPXCHG rcx, rdx       &nb= sp;       ; if (rcx =3D=3D rax) {rcx =3D rdx}= else {rax =3D rcx}
+   mov     rax, rcx
+   ret
+
+;-------------------------------------------------------------------------= ---
+; This fuction gets Fsp Original entry
+; Only Rax register is used
+;-------------------------------------------------------------------------= ---
+global ASM_PFX(AsmGetFspOriginalEntry)
+ASM_PFX(AsmGetFspOriginalEntry):
+   lea   rax, [ASM_PFX(AsmGetFspOriginalEntry)]
+   DB    0x48, 0x2d     =           ; sub rax, 0x???????= ?
+global ASM_PFX(SecEntryRelativeOff)
+ASM_PFX(SecEntryRelativeOff):
+   DD    0x12345678     =           ; This value must be= patched by the build script
+   ret
--
2.31.1.windows.1

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