RDTSC is not a serializing instruction

RDTSC is not a serializing instruction

[Ni, Ray]

All,
According to below Intel SDM content:
> The RDTSC instruction is not a serializing instruction. It does not necessarily wait until all previous instructions have been executed before reading the counter.
> Similarly, subsequent instructions may begin execution before the read operation is performed. The following items may guide software seeking to order executions of RDTSC:
> If software requires RDTSC to be executed only after all previous instructions have executed and all previous
>       loads are globally visible,1 it can execute LFENCE immediately before RDTSC.
> If software requires RDTSC to be executed only after all previous instructions have executed and all previous
>       loads and stores are globally visible, it can execute the sequence MFENCE;LFENCE immediately before RDTSC.
> If software requires RDTSC to be executed prior to execution of any subsequent instruction (including any
>       memory accesses), it can execute the sequence LFENCE immediately after RDTSC.

RDTSC might not return the accurate "current" tick.
A robust implementation could be "lfence" then "rdtsc". Otherwise, the edk2 perf-logging infra might generate incorrect data if using UefiCpuPkg/CpuTimerLib.

Lots of code polling for registers within a certain timeout is also impacted. I am curious why "timeout" doesn't happen. Or maybe "timeout" did happen that resulted in a longer "timeout" value was used?

Comments?

Thanks,
Ray

Re: RDTSC is not a serializing instruction

[Wu, Jiaxin]

It does has the impact, I have observed the phenomenon due to speculation execution.

Thanks,
Jiaxin

> -----Original Message-----
> From: Ni, Ray <ray.ni@intel.com>
> Sent: Thursday, May 25, 2023 2:11 PM
> To: devel@edk2.groups.io
> Cc: Ni, Ray <ray.ni@intel.com>; Wu, Jiaxin <jiaxin.wu@intel.com>; Wu, Hao A
> <hao.a.wu@intel.com>
> Subject: RDTSC is not a serializing instruction
> 
> All,
> According to below Intel SDM content:
> > The RDTSC instruction is not a serializing instruction. It does not necessarily
> wait until all previous instructions have been executed before reading the
> counter.
> > Similarly, subsequent instructions may begin execution before the read
> operation is performed. The following items may guide software seeking to
> order executions of RDTSC:
> > If software requires RDTSC to be executed only after all previous
> instructions have executed and all previous
> >       loads are globally visible,1 it can execute LFENCE immediately before
> RDTSC.
> > If software requires RDTSC to be executed only after all previous
> instructions have executed and all previous
> >       loads and stores are globally visible, it can execute the sequence
> MFENCE;LFENCE immediately before RDTSC.
> > If software requires RDTSC to be executed prior to execution of any
> subsequent instruction (including any
> >       memory accesses), it can execute the sequence LFENCE immediately
> after RDTSC.
> 
> RDTSC might not return the accurate "current" tick.
> A robust implementation could be "lfence" then "rdtsc". Otherwise, the edk2
> perf-logging infra might generate incorrect data if using
> UefiCpuPkg/CpuTimerLib.
> 
> Lots of code polling for registers within a certain timeout is also impacted. I
> am curious why "timeout" doesn't happen. Or maybe "timeout" did happen
> that resulted in a longer "timeout" value was used?
> 
> Comments?
> 
> Thanks,
> Ray