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Thread-Topic: [PATCH v6 5/6] UefiCpuPkg: Backup and Restore MSR IA32_U_CET in SMI handler. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: rSeMOZD0C6OGPrz8vHO7JHzux7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="nOq/H7Hj"; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Ray Ni Thanks, Ray > -----Original Message----- > From: Sheng, W > Sent: Tuesday, November 21, 2023 3:03 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Laszlo > Ersek ; Wu, Jiaxin ; Tan, Dun > > Subject: [PATCH v6 5/6] UefiCpuPkg: Backup and Restore MSR IA32_U_CET in > SMI handler. >=20 > OS may enable CET-IBT feature by set MSR IA32_U_CET.bit2. > If IA32_U_CET.bit2 is set, CPU is in WAIT_FOR_ENDBRANCH state and > the next assemble code is not ENDBR, it will trigger #CP exception > when set CR4.CET bit. > SMI handler needs to backup MSR IA32_U_CET and clear MSR IA32_U_CET > before set CR4.CET bit, > And SMI handler needs to restore MSR IA32_U_CET when exit SMI handler. >=20 > Signed-off-by: Sheng Wei > Cc: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > Cc: Wu Jiaxin > Cc: Tan Dun > Reviewed-by: Laszlo Ersek > --- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 15 > +++++++++++++++ > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 15 > +++++++++++++++ > 2 files changed, 30 insertions(+) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm > b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm > index 1da9afab97..9e1155dee6 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm > @@ -202,11 +202,21 @@ ASM_PFX(mPatchCetSupported): > push edx >=20 > push eax >=20 >=20 >=20 > + mov ecx, MSR_IA32_U_CET >=20 > + rdmsr >=20 > + push edx >=20 > + push eax >=20 > + >=20 > mov ecx, MSR_IA32_PL0_SSP >=20 > rdmsr >=20 > push edx >=20 > push eax >=20 >=20 >=20 > + mov ecx, MSR_IA32_U_CET >=20 > + xor eax, eax >=20 > + xor edx, edx >=20 > + wrmsr >=20 > + >=20 > mov ecx, MSR_IA32_S_CET >=20 > mov eax, MSR_IA32_CET_SH_STK_EN >=20 > xor edx, edx >=20 > @@ -276,6 +286,11 @@ CetDone: > pop edx >=20 > wrmsr >=20 >=20 >=20 > + mov ecx, MSR_IA32_U_CET >=20 > + pop eax >=20 > + pop edx >=20 > + wrmsr >=20 > + >=20 > mov ecx, MSR_IA32_S_CET >=20 > pop eax >=20 > pop edx >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm > b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm > index abf9f1a90a..881d3177f7 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm > @@ -217,6 +217,11 @@ ASM_PFX(mPatchCetSupported): > push rdx >=20 > push rax >=20 >=20 >=20 > + mov ecx, MSR_IA32_U_CET >=20 > + rdmsr >=20 > + push rdx >=20 > + push rax >=20 > + >=20 > mov ecx, MSR_IA32_PL0_SSP >=20 > rdmsr >=20 > push rdx >=20 > @@ -227,6 +232,11 @@ ASM_PFX(mPatchCetSupported): > push rdx >=20 > push rax >=20 >=20 >=20 > + mov ecx, MSR_IA32_U_CET >=20 > + xor eax, eax >=20 > + xor edx, edx >=20 > + wrmsr >=20 > + >=20 > mov ecx, MSR_IA32_S_CET >=20 > mov eax, MSR_IA32_CET_SH_STK_EN >=20 > xor edx, edx >=20 > @@ -325,6 +335,11 @@ mCetSupportedAbsAddr: > pop rdx >=20 > wrmsr >=20 >=20 >=20 > + mov ecx, MSR_IA32_U_CET >=20 > + pop rax >=20 > + pop rdx >=20 > + wrmsr >=20 > + >=20 > mov ecx, MSR_IA32_S_CET >=20 > pop rax >=20 > pop rdx >=20 > -- > 2.26.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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