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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 5Qoc2r4KiYhxYjVyVTusdjy9x7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="AAh6zn/M"; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Reviewed-by: Ray Ni Thanks, Ray > -----Original Message----- > From: Wu, Jiaxin > Sent: Friday, December 15, 2023 5:55 PM > To: devel@edk2.groups.io > Cc: Laszlo Ersek ; Dong, Eric ; N= i, > Ray ; Zeng, Star ; Gerd Hoffmann > ; Kumar, Rahul R > Subject: [PATCH v4 8/8] UefiCpuPkg/PiSmmCpuDxeSmm: Consume > SmmCpuSyncLib >=20 > There is the SmmCpuSyncLib Library class define the SMM CPU sync > flow, which is aligned with existing SMM CPU driver sync behavior. > This patch is to consume SmmCpuSyncLib instance directly. >=20 > With this change, SMM CPU Sync flow/logic can be customized > with different implementation no matter for any purpose, e.g. > performance tuning, handle specific register, etc. >=20 > Cc: Laszlo Ersek > Cc: Eric Dong > Cc: Ray Ni > Cc: Zeng Star > Cc: Gerd Hoffmann > Cc: Rahul Kumar > Signed-off-by: Jiaxin Wu > --- > UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 274 > +++++++-------------------- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 6 +- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + > 3 files changed, 68 insertions(+), 213 deletions(-) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c > index 9b477b6695..4fbb0bba87 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c > @@ -27,122 +27,10 @@ MM_COMPLETION > mSmmStartupThisApToken; > // > // Processor specified by mPackageFirstThreadIndex[PackageIndex] will do > the package-scope register check. > // > UINT32 *mPackageFirstThreadIndex =3D NULL; >=20 > -/** > - Performs an atomic compare exchange operation to get semaphore. > - The compare exchange operation must be performed using > - MP safe mechanisms. > - > - @param Sem IN: 32-bit unsigned integer > - OUT: original integer - 1 > - @return Original integer - 1 > - > -**/ > -UINT32 > -WaitForSemaphore ( > - IN OUT volatile UINT32 *Sem > - ) > -{ > - UINT32 Value; > - > - for ( ; ;) { > - Value =3D *Sem; > - if ((Value !=3D 0) && > - (InterlockedCompareExchange32 ( > - (UINT32 *)Sem, > - Value, > - Value - 1 > - ) =3D=3D Value)) > - { > - break; > - } > - > - CpuPause (); > - } > - > - return Value - 1; > -} > - > -/** > - Performs an atomic compare exchange operation to release semaphore. > - The compare exchange operation must be performed using > - MP safe mechanisms. > - > - @param Sem IN: 32-bit unsigned integer > - OUT: original integer + 1 > - @return Original integer + 1 > - > -**/ > -UINT32 > -ReleaseSemaphore ( > - IN OUT volatile UINT32 *Sem > - ) > -{ > - UINT32 Value; > - > - do { > - Value =3D *Sem; > - } while (Value + 1 !=3D 0 && > - InterlockedCompareExchange32 ( > - (UINT32 *)Sem, > - Value, > - Value + 1 > - ) !=3D Value); > - > - return Value + 1; > -} > - > -/** > - Performs an atomic compare exchange operation to lock semaphore. > - The compare exchange operation must be performed using > - MP safe mechanisms. > - > - @param Sem IN: 32-bit unsigned integer > - OUT: -1 > - @return Original integer > - > -**/ > -UINT32 > -LockdownSemaphore ( > - IN OUT volatile UINT32 *Sem > - ) > -{ > - UINT32 Value; > - > - do { > - Value =3D *Sem; > - } while (InterlockedCompareExchange32 ( > - (UINT32 *)Sem, > - Value, > - (UINT32)-1 > - ) !=3D Value); > - > - return Value; > -} > - > -/** > - Used for BSP to wait all APs. > - Wait all APs to performs an atomic compare exchange operation to relea= se > semaphore. > - > - @param NumberOfAPs AP number > - > -**/ > -VOID > -WaitForAllAPs ( > - IN UINTN NumberOfAPs > - ) > -{ > - UINTN BspIndex; > - > - BspIndex =3D mSmmMpSyncData->BspIndex; > - while (NumberOfAPs-- > 0) { > - WaitForSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); > - } > -} > - > /** > Used for BSP to release all APs. > Performs an atomic compare exchange operation to release semaphore > for each AP. >=20 > @@ -154,57 +42,15 @@ ReleaseAllAPs ( > { > UINTN Index; >=20 > for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { > if (IsPresentAp (Index)) { > - ReleaseSemaphore (mSmmMpSyncData->CpuData[Index].Run); > + SmmCpuSyncReleaseOneAp (mSmmMpSyncData->SyncContext, > Index, gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu); > } > } > } >=20 > -/** > - Used for BSP to release one AP. > - > - @param ApSem IN: 32-bit unsigned integer > - OUT: original integer + 1 > -**/ > -VOID > -ReleaseOneAp ( > - IN OUT volatile UINT32 *ApSem > - ) > -{ > - ReleaseSemaphore (ApSem); > -} > - > -/** > - Used for AP to wait BSP. > - > - @param ApSem IN: 32-bit unsigned integer > - OUT: original integer - 1 > -**/ > -VOID > -WaitForBsp ( > - IN OUT volatile UINT32 *ApSem > - ) > -{ > - WaitForSemaphore (ApSem); > -} > - > -/** > - Used for AP to release BSP. > - > - @param BspSem IN: 32-bit unsigned integer > - OUT: original integer + 1 > -**/ > -VOID > -ReleaseBsp ( > - IN OUT volatile UINT32 *BspSem > - ) > -{ > - ReleaseSemaphore (BspSem); > -} > - > /** > Check whether the index of CPU perform the package level register > programming during System Management Mode initialization. >=20 > The index of Processor specified by > mPackageFirstThreadIndex[PackageIndex] > @@ -292,35 +138,35 @@ AllCpusInSmmExceptBlockedDisabled ( >=20 > BlockedCount =3D 0; > DisabledCount =3D 0; >=20 > // > - // Check to make sure mSmmMpSyncData->Counter is valid and not > locked. > + // Check to make sure the CPU arrival count is valid and not locked. > // > - ASSERT (*mSmmMpSyncData->Counter <=3D mNumberOfCpus); > + ASSERT (SmmCpuSyncGetArrivedCpuCount > (mSmmMpSyncData->SyncContext) <=3D mNumberOfCpus); >=20 > // > // Check whether all CPUs in SMM. > // > - if (*mSmmMpSyncData->Counter =3D=3D mNumberOfCpus) { > + if (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SyncContext) > =3D=3D mNumberOfCpus) { > return TRUE; > } >=20 > // > // Check for the Blocked & Disabled Exceptions Case. > // > GetSmmDelayedBlockedDisabledCount (NULL, &BlockedCount, > &DisabledCount); >=20 > // > - // *mSmmMpSyncData->Counter might be updated by all APs concurrently. > The value > + // The CPU arrival count might be updated by all APs concurrently. The > value > // can be dynamic changed. If some Aps enter the SMI after the > BlockedCount & > - // DisabledCount check, then the *mSmmMpSyncData->Counter will be > increased, thus > - // leading the *mSmmMpSyncData->Counter + BlockedCount + > DisabledCount > mNumberOfCpus. > + // DisabledCount check, then the CPU arrival count will be increased, = thus > + // leading the retrieved CPU arrival count + BlockedCount + > DisabledCount > mNumberOfCpus. > // since the BlockedCount & DisabledCount are local variable, it's ok = here > only for > // the checking of all CPUs In Smm. > // > - if (*mSmmMpSyncData->Counter + BlockedCount + DisabledCount >=3D > mNumberOfCpus) { > + if (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SyncContext) > + BlockedCount + DisabledCount >=3D mNumberOfCpus) { > return TRUE; > } >=20 > return FALSE; > } > @@ -396,11 +242,11 @@ SmmWaitForApArrival ( > PERF_FUNCTION_BEGIN (); >=20 > DelayedCount =3D 0; > BlockedCount =3D 0; >=20 > - ASSERT (*mSmmMpSyncData->Counter <=3D mNumberOfCpus); > + ASSERT (SmmCpuSyncGetArrivedCpuCount > (mSmmMpSyncData->SyncContext) <=3D mNumberOfCpus); >=20 > LmceEn =3D FALSE; > LmceSignal =3D FALSE; > if (mMachineCheckSupported) { > LmceEn =3D IsLmceOsEnabled (); > @@ -447,11 +293,11 @@ SmmWaitForApArrival ( > // d) We don't add code to check SMI disabling status to skip sending = IPI to > SMI disabled APs, because: > // - In traditional flow, SMI disabling is discouraged. > // - In relaxed flow, CheckApArrival() will check SMI disabling sta= tus > before calling this function. > // In both cases, adding SMI-disabling checking code increases > overhead. > // > - if (*mSmmMpSyncData->Counter < mNumberOfCpus) { > + if (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SyncContext) > < mNumberOfCpus) { > // > // Send SMI IPIs to bring outside processors in > // > for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { > if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && > (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId !=3D INVALID_APIC_ID)) = { > @@ -610,18 +456,20 @@ VOID > BSPHandler ( > IN UINTN CpuIndex, > IN SMM_CPU_SYNC_MODE SyncMode > ) > { > + UINTN CpuCount; > UINTN Index; > MTRR_SETTINGS Mtrrs; > UINTN ApCount; > BOOLEAN ClearTopLevelSmiResult; > UINTN PresentCount; >=20 > ASSERT (CpuIndex =3D=3D mSmmMpSyncData->BspIndex); > - ApCount =3D 0; > + CpuCount =3D 0; > + ApCount =3D 0; >=20 > PERF_FUNCTION_BEGIN (); >=20 > // > // Flag BSP's presence > @@ -659,28 +507,31 @@ BSPHandler ( > // Wait for APs to arrive > // > SmmWaitForApArrival (); >=20 > // > - // Lock the counter down and retrieve the number of APs > + // Lock door for late coming CPU checkin and retrieve the Arrived > number of APs > // > *mSmmMpSyncData->AllCpusInSync =3D TRUE; > - ApCount =3D LockdownSemaphore > (mSmmMpSyncData->Counter) - 1; > + > + SmmCpuSyncLockDoor (mSmmMpSyncData->SyncContext, CpuIndex, > &CpuCount); > + > + ApCount =3D CpuCount - 1; >=20 > // > // Wait for all APs to get ready for programming MTRRs > // > - WaitForAllAPs (ApCount); > + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, > CpuIndex); >=20 > if (SmmCpuFeaturesNeedConfigureMtrrs ()) { > // > // Signal all APs it's time for backup MTRRs > // > ReleaseAllAPs (); >=20 > // > - // WaitForAllAPs() may wait for ever if an AP happens to enter SMM > at > + // SmmCpuSyncWaitForAPs() may wait for ever if an AP happens to > enter SMM at > // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops > has been set > // to a large enough value to avoid this situation. > // Note: For HT capable CPUs, threads within a core share the same > set of MTRRs. > // We do the backup first and then set MTRR to avoid race conditio= n > for threads > // in the same core. > @@ -688,28 +539,28 @@ BSPHandler ( > MtrrGetAllMtrrs (&Mtrrs); >=20 > // > // Wait for all APs to complete their MTRR saving > // > - WaitForAllAPs (ApCount); > + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, > ApCount, CpuIndex); >=20 > // > // Let all processors program SMM MTRRs together > // > ReleaseAllAPs (); >=20 > // > - // WaitForAllAPs() may wait for ever if an AP happens to enter SMM > at > + // SmmCpuSyncWaitForAPs() may wait for ever if an AP happens to > enter SMM at > // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops > has been set > // to a large enough value to avoid this situation. > // > ReplaceOSMtrrs (CpuIndex); >=20 > // > // Wait for all APs to complete their MTRR programming > // > - WaitForAllAPs (ApCount); > + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, > ApCount, CpuIndex); > } > } >=20 > // > // The BUSY lock is initialized to Acquired state > @@ -741,14 +592,18 @@ BSPHandler ( > // make those APs to exit SMI synchronously. APs which arrive later wi= ll > be excluded and > // will run through freely. > // > if ((SyncMode !=3D SmmCpuSyncModeTradition) > && !SmmCpuFeaturesNeedConfigureMtrrs ()) { > // > - // Lock the counter down and retrieve the number of APs > + // Lock door for late coming CPU checkin and retrieve the Arrived > number of APs > // > *mSmmMpSyncData->AllCpusInSync =3D TRUE; > - ApCount =3D LockdownSemaphore > (mSmmMpSyncData->Counter) - 1; > + > + SmmCpuSyncLockDoor (mSmmMpSyncData->SyncContext, CpuIndex, > &CpuCount); > + > + ApCount =3D CpuCount - 1; > + > // > // Make sure all APs have their Present flag set > // > while (TRUE) { > PresentCount =3D 0; > @@ -771,11 +626,11 @@ BSPHandler ( > ReleaseAllAPs (); >=20 > // > // Wait for all APs to complete their pending tasks > // > - WaitForAllAPs (ApCount); > + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, > CpuIndex); >=20 > if (SmmCpuFeaturesNeedConfigureMtrrs ()) { > // > // Signal APs to restore MTRRs > // > @@ -788,11 +643,11 @@ BSPHandler ( > MtrrSetAllMtrrs (&Mtrrs); >=20 > // > // Wait for all APs to complete MTRR programming > // > - WaitForAllAPs (ApCount); > + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, > CpuIndex); > } >=20 > // > // Stop source level debug in BSP handler, the code below will not be > // debugged. > @@ -816,11 +671,11 @@ BSPHandler ( >=20 > // > // Gather APs to exit SMM synchronously. Note the Present flag is clea= red > by now but > // WaitForAllAps does not depend on the Present flag. > // > - WaitForAllAPs (ApCount); > + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, > CpuIndex); >=20 > // > // At this point, all APs should have exited from APHandler(). > // Migrate the SMM MP performance logging to standard SMM > performance logging. > // Any SMM MP performance logging after this point will be migrated in > next SMI. > @@ -842,11 +697,11 @@ BSPHandler ( > } >=20 > // > // Allow APs to check in from this point on > // > - *mSmmMpSyncData->Counter =3D 0; > + SmmCpuSyncContextReset (mSmmMpSyncData->SyncContext); > *mSmmMpSyncData->AllCpusInSync =3D FALSE; > mSmmMpSyncData->AllApArrivedWithException =3D FALSE; >=20 > PERF_FUNCTION_END (); > } > @@ -912,21 +767,21 @@ APHandler ( >=20 > if (!(*mSmmMpSyncData->InsideSmm)) { > // > // Give up since BSP is unable to enter SMM > // and signal the completion of this AP > - // Reduce the mSmmMpSyncData->Counter! > + // Reduce the CPU arrival count! > // > - WaitForSemaphore (mSmmMpSyncData->Counter); > + SmmCpuSyncCheckOutCpu (mSmmMpSyncData->SyncContext, > CpuIndex); > return; > } > } else { > // > // Don't know BSP index. Give up without sending IPI to BSP. > - // Reduce the mSmmMpSyncData->Counter! > + // Reduce the CPU arrival count! > // > - WaitForSemaphore (mSmmMpSyncData->Counter); > + SmmCpuSyncCheckOutCpu (mSmmMpSyncData->SyncContext, > CpuIndex); > return; > } > } >=20 > // > @@ -942,50 +797,50 @@ APHandler ( >=20 > if ((SyncMode =3D=3D SmmCpuSyncModeTradition) || > SmmCpuFeaturesNeedConfigureMtrrs ()) { > // > // Notify BSP of arrival at this point > // > - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); > + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SyncContext, CpuIndex, > BspIndex); > } >=20 > if (SmmCpuFeaturesNeedConfigureMtrrs ()) { > // > // Wait for the signal from BSP to backup MTRRs > // > - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); > + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SyncContext, CpuIndex, > BspIndex); >=20 > // > // Backup OS MTRRs > // > MtrrGetAllMtrrs (&Mtrrs); >=20 > // > // Signal BSP the completion of this AP > // > - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); > + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SyncContext, CpuIndex, > BspIndex); >=20 > // > // Wait for BSP's signal to program MTRRs > // > - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); > + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SyncContext, CpuIndex, > BspIndex); >=20 > // > // Replace OS MTRRs with SMI MTRRs > // > ReplaceOSMtrrs (CpuIndex); >=20 > // > // Signal BSP the completion of this AP > // > - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); > + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SyncContext, CpuIndex, > BspIndex); > } >=20 > while (TRUE) { > // > // Wait for something to happen > // > - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); > + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SyncContext, CpuIndex, > BspIndex); >=20 > // > // Check if BSP wants to exit SMM > // > if (!(*mSmmMpSyncData->InsideSmm)) { > @@ -1021,16 +876,16 @@ APHandler ( >=20 > if (SmmCpuFeaturesNeedConfigureMtrrs ()) { > // > // Notify BSP the readiness of this AP to program MTRRs > // > - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); > + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SyncContext, CpuIndex, > BspIndex); >=20 > // > // Wait for the signal from BSP to program MTRRs > // > - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); > + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SyncContext, CpuIndex, > BspIndex); >=20 > // > // Restore OS MTRRs > // > SmmCpuFeaturesReenableSmrr (); > @@ -1038,26 +893,26 @@ APHandler ( > } >=20 > // > // Notify BSP the readiness of this AP to Reset states/semaphore for t= his > processor > // > - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); > + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SyncContext, CpuIndex, > BspIndex); >=20 > // > // Wait for the signal from BSP to Reset states/semaphore for this > processor > // > - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); > + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SyncContext, CpuIndex, > BspIndex); >=20 > // > // Reset states/semaphore for this processor > // > *(mSmmMpSyncData->CpuData[CpuIndex].Present) =3D FALSE; >=20 > // > // Notify BSP the readiness of this AP to exit SMM > // > - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); > + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SyncContext, CpuIndex, > BspIndex); > } >=20 > /** > Checks whether the input token is the current used token. >=20 > @@ -1321,11 +1176,11 @@ InternalSmmStartupThisAp ( > mSmmMpSyncData->CpuData[CpuIndex].Status =3D CpuStatus; > if (mSmmMpSyncData->CpuData[CpuIndex].Status !=3D NULL) { > *mSmmMpSyncData->CpuData[CpuIndex].Status =3D EFI_NOT_READY; > } >=20 > - ReleaseOneAp (mSmmMpSyncData->CpuData[CpuIndex].Run); > + SmmCpuSyncReleaseOneAp (mSmmMpSyncData->SyncContext, CpuIndex, > gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu); >=20 > if (Token =3D=3D NULL) { > AcquireSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); > ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); > } > @@ -1725,14 +1580,15 @@ SmiRendezvous ( > // > goto Exit; > } else { > // > // Signal presence of this processor > - // mSmmMpSyncData->Counter is increased here! > - // "ReleaseSemaphore (mSmmMpSyncData->Counter) =3D=3D 0" means BSP > has already ended the synchronization. > + // CPU check in here! > + // "SmmCpuSyncCheckInCpu (mSmmMpSyncData->SyncContext, > CpuIndex)" return error means failed > + // to check in CPU. BSP has already ended the synchronization. > // > - if (ReleaseSemaphore (mSmmMpSyncData->Counter) =3D=3D 0) { > + if (RETURN_ERROR (SmmCpuSyncCheckInCpu > (mSmmMpSyncData->SyncContext, CpuIndex))) { > // > // BSP has already ended the synchronization, so QUIT!!! > // Existing AP is too late now to enter SMI since BSP has already > ended the synchronization!!! > // >=20 > @@ -1824,12 +1680,10 @@ SmiRendezvous ( > } else { > APHandler (CpuIndex, ValidSmi, > mSmmMpSyncData->EffectiveSyncMode); > } > } >=20 > - ASSERT (*mSmmMpSyncData->CpuData[CpuIndex].Run =3D=3D 0); > - > // > // Wait for BSP's signal to exit SMI > // > while (*mSmmMpSyncData->AllCpusInSync) { > CpuPause (); > @@ -1945,12 +1799,10 @@ InitializeSmmCpuSemaphores ( > SemaphoreBlock =3D AllocatePages (Pages); > ASSERT (SemaphoreBlock !=3D NULL); > ZeroMem (SemaphoreBlock, TotalSize); >=20 > SemaphoreAddr =3D > (UINTN)SemaphoreBlock; > - mSmmCpuSemaphores.SemaphoreGlobal.Counter =3D (UINT32 > *)SemaphoreAddr; > - SemaphoreAddr +=3D > SemaphoreSize; > mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm =3D (BOOLEAN > *)SemaphoreAddr; > SemaphoreAddr +=3D > SemaphoreSize; > mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync =3D (BOOLEAN > *)SemaphoreAddr; > SemaphoreAddr +=3D > SemaphoreSize; > mSmmCpuSemaphores.SemaphoreGlobal.PFLock =3D (SPIN_LOCK > *)SemaphoreAddr; > @@ -1960,12 +1812,10 @@ InitializeSmmCpuSemaphores ( > SemaphoreAddr +=3D SemaphoreSize; >=20 > SemaphoreAddr =3D > (UINTN)SemaphoreBlock + GlobalSemaphoresSize; > mSmmCpuSemaphores.SemaphoreCpu.Busy =3D (SPIN_LOCK > *)SemaphoreAddr; > SemaphoreAddr +=3D ProcessorCount * > SemaphoreSize; > - mSmmCpuSemaphores.SemaphoreCpu.Run =3D (UINT32 > *)SemaphoreAddr; > - SemaphoreAddr +=3D ProcessorCount * > SemaphoreSize; > mSmmCpuSemaphores.SemaphoreCpu.Present =3D (BOOLEAN > *)SemaphoreAddr; >=20 > mPFLock =3D > mSmmCpuSemaphores.SemaphoreGlobal.PFLock; > mConfigSmmCodeAccessCheckLock =3D > mSmmCpuSemaphores.SemaphoreGlobal.CodeAccessCheckLock; >=20 > @@ -1980,10 +1830,12 @@ VOID > EFIAPI > InitializeMpSyncData ( > VOID > ) > { > + RETURN_STATUS Status; > + > UINTN CpuIndex; >=20 > if (mSmmMpSyncData !=3D NULL) { > // > // mSmmMpSyncDataSize includes one structure of > SMM_DISPATCHER_MP_SYNC_DATA, one > @@ -2009,32 +1861,36 @@ InitializeMpSyncData ( > } > } >=20 > mSmmMpSyncData->EffectiveSyncMode =3D mCpuSmmSyncMode; >=20 > - mSmmMpSyncData->Counter =3D > mSmmCpuSemaphores.SemaphoreGlobal.Counter; > + Status =3D SmmCpuSyncContextInit > (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus, > &mSmmMpSyncData->SyncContext); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "InitializeMpSyncData: > SmmCpuSyncContextInit return error %r!\n", Status)); > + CpuDeadLoop (); > + return; > + } > + > + ASSERT (mSmmMpSyncData->SyncContext !=3D NULL); > + > mSmmMpSyncData->InsideSmm =3D > mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm; > mSmmMpSyncData->AllCpusInSync =3D > mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync; > ASSERT ( > - mSmmMpSyncData->Counter !=3D NULL && > mSmmMpSyncData->InsideSmm !=3D NULL && > + mSmmMpSyncData->InsideSmm !=3D NULL && > mSmmMpSyncData->AllCpusInSync !=3D NULL > ); > - *mSmmMpSyncData->Counter =3D 0; > *mSmmMpSyncData->InsideSmm =3D FALSE; > *mSmmMpSyncData->AllCpusInSync =3D FALSE; >=20 > mSmmMpSyncData->AllApArrivedWithException =3D FALSE; >=20 > for (CpuIndex =3D 0; CpuIndex < > gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; CpuIndex++) { > mSmmMpSyncData->CpuData[CpuIndex].Busy =3D > (SPIN_LOCK > *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Busy + mSemaphoreSize * > CpuIndex); > - mSmmMpSyncData->CpuData[CpuIndex].Run =3D > - (UINT32 *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Run + > mSemaphoreSize * CpuIndex); > mSmmMpSyncData->CpuData[CpuIndex].Present =3D > (BOOLEAN > *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Present + > mSemaphoreSize * CpuIndex); > *(mSmmMpSyncData->CpuData[CpuIndex].Busy) =3D 0; > - *(mSmmMpSyncData->CpuData[CpuIndex].Run) =3D 0; > *(mSmmMpSyncData->CpuData[CpuIndex].Present) =3D FALSE; > } > } > } >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > index f18345881b..a2fa4f6734 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > @@ -52,10 +52,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #include > #include > #include > #include > #include > +#include >=20 > #include > #include >=20 > #include > @@ -403,11 +404,10 @@ SmmRelocationSemaphoreComplete ( > /// > typedef struct { > SPIN_LOCK *Busy; > volatile EFI_AP_PROCEDURE2 Procedure; > volatile VOID *Parameter; > - volatile UINT32 *Run; > volatile BOOLEAN *Present; > PROCEDURE_TOKEN *Token; > EFI_STATUS *Status; > } SMM_CPU_DATA_BLOCK; >=20 > @@ -421,29 +421,28 @@ typedef struct { > // > // Pointer to an array. The array should be located immediately after = this > structure > // so that UC cache-ability can be set together. > // > SMM_CPU_DATA_BLOCK *CpuData; > - volatile UINT32 *Counter; > volatile UINT32 BspIndex; > volatile BOOLEAN *InsideSmm; > volatile BOOLEAN *AllCpusInSync; > volatile SMM_CPU_SYNC_MODE EffectiveSyncMode; > volatile BOOLEAN SwitchBsp; > volatile BOOLEAN *CandidateBsp; > volatile BOOLEAN AllApArrivedWithException; > EFI_AP_PROCEDURE StartupProcedure; > VOID *StartupProcArgs; > + SMM_CPU_SYNC_CONTEXT *SyncContext; > } SMM_DISPATCHER_MP_SYNC_DATA; >=20 > #define SMM_PSD_OFFSET 0xfb00 >=20 > /// > /// All global semaphores' pointer > /// > typedef struct { > - volatile UINT32 *Counter; > volatile BOOLEAN *InsideSmm; > volatile BOOLEAN *AllCpusInSync; > SPIN_LOCK *PFLock; > SPIN_LOCK *CodeAccessCheckLock; > } SMM_CPU_SEMAPHORE_GLOBAL; > @@ -451,11 +450,10 @@ typedef struct { > /// > /// All semaphores for each processor > /// > typedef struct { > SPIN_LOCK *Busy; > - volatile UINT32 *Run; > volatile BOOLEAN *Present; > SPIN_LOCK *Token; > } SMM_CPU_SEMAPHORE_CPU; >=20 > /// > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > index 372596f24c..793220aba3 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > @@ -101,10 +101,11 @@ > SmmCpuFeaturesLib > PeCoffGetEntryPointLib > PerformanceLib > CpuPageTableLib > MmSaveStateLib > + SmmCpuSyncLib >=20 > [Protocols] > gEfiSmmAccess2ProtocolGuid ## CONSUMES > gEfiSmmConfigurationProtocolGuid ## PRODUCES > gEfiSmmCpuProtocolGuid ## PRODUCES > -- > 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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