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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Is this event signaled regardless of FSP API/Dispatch mode? > -----Original Message----- > From: Chang, Hunter > Sent: Tuesday, June 13, 2023 8:40 PM > To: devel@edk2.groups.io > Cc: Chang, Hunter ; Ni, Ray ; > Chaganty, Rangasai V ; Oram, Isaac W > ; S, Ashraf Ali ; Chen, T= ina > ; Chen, Arthur G > Subject: [PATCH v1] IntelSiliconPkg: Add gEndOfSiInitPpiGuid definition i= n DEC > file >=20 > From: Hunter Chang >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4371 >=20 > Add gEndOfSiInitPpiGuid definition in IntelSiliconPkg.dec > gEndOfSiInitPpiGuid indicates the end of all of the silicon init. > Add it to IntellSiliconPkg for AFP improvement. >=20 > Signed-off-by: Hunter Chang >=20 > Cc: Ray Ni > Cc: Rangasai V Chaganty > Cc: Isaac Oram > Cc: Ashraf Ali S > Cc: Tina Chen > Cc: Arthur Chen > --- > Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 1 + > 1 file changed, 1 insertion(+) >=20 > diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > index ec8690a8d6..c540ef40ad 100644 > --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > @@ -113,6 +113,7 @@ > gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0= x67, > 0xaf, 0x2b, 0x25, 0x68, 0x4a } } >=20 > gEdkiiVTdNullRootEntryTableGuid =3D { 0x3de0593f, 0x6e3e, 0x4542, { 0x= a1, > 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } } >=20 > gIntelDieInfoPpiGuid =3D { 0xF9E45CBF, 0x1E21, 0x434A, { 0x90, 0x88, 0= x1D, > 0x10, 0x38, 0xF3, 0x68, 0xF2 }} >=20 > + gEndOfSiInitPpiGuid =3D { 0xE2E3D5D1, 0x8356, 0x4F96, { 0x9C, 0x9E, 0= x2E, > 0xC3, 0x48, 0x1D, 0xEA, 0x88 }} >=20 >=20 >=20 > [Protocols] >=20 > ## Protocols that provide services for the Intel(R) PCH SPI Host Contr= oller > Compatibility Interface >=20 > -- > 2.26.2.windows.1