Re: [Patch V4 17/21] UefiCpuPkg/CpuPageTableLib: Add check for page table creation

["Ni, Ray" <ray.ni@intel.com>]

Reviewed-by: Ray Ni <ray.ni@Intel.com>

> -----Original Message-----
> From: Tan, Dun <dun.tan@intel.com>
> Sent: Thursday, March 23, 2023 3:41 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar,
> Rahul R <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>
> Subject: [Patch V4 17/21] UefiCpuPkg/CpuPageTableLib: Add check for page
> table creation
> 
> Add code to compare ParentPagingEntry Attribute&Mask and input
> Attribute&Mask to decide if new next level page table is needed
> in non-present ParentPagingEntry condition. This can help avoid
> unneccessary page table creation.
> 
> For example, there is a page table in which [0, 1G] is mapped(Lv4[0]
> ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry).And we
> only want to map [1G, 1G+2M] linear address still as non-present.
> The expected behaviour should be nothing happens in the process.
> However, previous code logic doesn't check if ParentPagingEntry
> Attribute&Mask and input Attribute&Mask are the same in non-present
> ParentPagingEntry condition. Then a new 4K memory is allocated for
> Lv2 since 1G+2M is not 1G-aligned.
> So when ParentPagingEntry is non-present, before allocate 4K memory
> for next level paging, we also check if ParentPagingEntry Attribute&
> Mask and input Attribute&Mask are the same.
> 
> Signed-off-by: Dun Tan <dun.tan@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> ---
>  UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 10
> ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> index 982652b58b..55a756ad90 100644
> --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> @@ -358,6 +358,16 @@ PageTableLibMapInLevel (
>        return Status;
>      }
> 
> +    //
> +    // Check the attribute in ParentPagingEntry is equal to attribute calculated
> by input Attribue and Mask.
> +    //
> +    PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute
> (&ParentPagingEntry->PleB, ParentAttribute);
> +    if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) &
> IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))
> +        == (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) &
> IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))
> +    {
> +      return RETURN_SUCCESS;
> +    }
> +
>      //
>      // The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE.
>      // It does NOT point to an existing page directory.
> --
> 2.31.1.windows.1