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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Ard, https://github.com/tianocore/edk2/blob/8314a85893f5b75baa0031a5138028188a62= 6243/UefiCpuPkg/SecCore/SecMain.c#L637 is changed by @Wu, Jiaxin to create = page table in permanent memory. (I didn't check your patch in detail. But it sounds like you try to do the = same thing that above code has already done.) Thanks, Ray > -----Original Message----- > From: Ard Biesheuvel > Sent: Friday, June 9, 2023 1:23 AM > To: devel@edk2.groups.io > Cc: Ard Biesheuvel ; Ni, Ray ; Yao, > Jiewen ; Gerd Hoffmann ; Taylor > Beebe ; Oliver Smith-Denny ; > Bi, Dandan ; Tan, Dun ; Gao, > Liming ; Kinney, Michael D > ; Michael Kubacki > ; Dong, Eric ; Kumar, > Rahul R ; Kun Qin > Subject: [PATCH 2/2] UefiCpuPkg/CpuMpPei X64: Reallocate page tables in > permanent DRAM >=20 > Currently, we rely on the logic in DXE IPL to create new page tables > from scratch when executing in X64 mode, which means that we run with > the initial page tables all throughout PEI, and never enable protections > such as the CPU stack guard, even though the logic is already in place > for IA32. >=20 > So let's enable the existing logic for X64 as well. This will permit us > to apply stricter memory permissions to code and data allocations, as > well as the stack, when executing in PEI. It also makes the DxeIpl logic > redundant, and should allow us to make the PcdDxeIplBuildPageTables > feature PCD limited to IA32 DxeIpl loading the x64 DXE core. >=20 > When running in long mode, use the same logic that DxeIpl uses to > determine the size of the address space, whether or not to use 1 GB leaf > entries and whether or not to use 5 level paging. Note that in long > mode, PEI is entered with paging enabled, and given that switching > between 4 and 5 levels of paging is not currently supported without > dropping out of 64-bit mode temporarily, all we can do is carry on > without changing the number of levels. >=20 > Signed-off-by: Ard Biesheuvel > --- > UefiCpuPkg/CpuMpPei/CpuMpPei.inf | 2 + > UefiCpuPkg/CpuMpPei/CpuPaging.c | 163 ++++++++++++++++---- > 2 files changed, 139 insertions(+), 26 deletions(-) >=20 > diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.inf > b/UefiCpuPkg/CpuMpPei/CpuMpPei.inf > index 865be5627e8551ee..77eecaa0ea035b38 100644 > --- a/UefiCpuPkg/CpuMpPei/CpuMpPei.inf > +++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.inf > @@ -65,6 +65,8 @@ [Ppis] > [Pcd] >=20 >=20 > gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMas > k ## CONSUMES >=20 > gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard = ## > CONSUMES >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable = ## > SOMETIMES_CONSUMES >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable = ## > SOMETIMES_CONSUMES >=20 > gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList = ## > SOMETIMES_CONSUMES >=20 > gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize = ## > SOMETIMES_CONSUMES >=20 > gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize = ## > SOMETIMES_CONSUMES >=20 > diff --git a/UefiCpuPkg/CpuMpPei/CpuPaging.c > b/UefiCpuPkg/CpuMpPei/CpuPaging.c > index 175e47ccd737a0c1..2a901e44253434c2 100644 > --- a/UefiCpuPkg/CpuMpPei/CpuPaging.c > +++ b/UefiCpuPkg/CpuMpPei/CpuPaging.c > @@ -302,7 +302,7 @@ ConvertMemoryPageAttributes ( > return RETURN_INVALID_PARAMETER; >=20 > } >=20 >=20 >=20 > - MaximumAddress =3D (EFI_PHYSICAL_ADDRESS)MAX_UINT32; >=20 > + MaximumAddress =3D (EFI_PHYSICAL_ADDRESS)MAX_ADDRESS; >=20 > if ((BaseAddress > MaximumAddress) || >=20 > (Length > MaximumAddress) || >=20 > (BaseAddress > MaximumAddress - (Length - 1))) >=20 > @@ -350,16 +350,91 @@ ConvertMemoryPageAttributes ( > return RETURN_SUCCESS; >=20 > } >=20 >=20 >=20 > +/* >=20 > + * Get physical address bits supported. >=20 > + * >=20 > + * @return The number of supported physical address bits. >=20 > + */ >=20 > +STATIC >=20 > +UINT8 >=20 > +GetPhysicalAddressBits ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_HOB_CPU *Hob; >=20 > + UINT32 RegEax; >=20 > + >=20 > + Hob =3D GetFirstHob (EFI_HOB_TYPE_CPU); >=20 > + if (Hob !=3D NULL) { >=20 > + return Hob->SizeOfMemorySpace; >=20 > + } >=20 > + >=20 > + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); >=20 > + if (RegEax >=3D 0x80000008) { >=20 > + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); >=20 > + return (UINT8)RegEax; >=20 > + } >=20 > + >=20 > + return 36; >=20 > +} >=20 > + >=20 > +/* >=20 > + * Determine and return the paging mode to be used in long mode, based o= n > PCD >=20 > + * configuration and CPU support for 1G leaf descriptors and 5 level pag= ing. >=20 > + * >=20 > + * @return The paging mode >=20 > + */ >=20 > +STATIC >=20 > +PAGING_MODE >=20 > +GetPagingMode ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + BOOLEAN Page5LevelSupport; >=20 > + BOOLEAN Page1GSupport; >=20 > + UINT32 RegEax; >=20 > + UINT32 RegEdx; >=20 > + IA32_CR4 Cr4; >=20 > + >=20 > + Cr4.UintN =3D AsmReadCr4 (); >=20 > + Page5LevelSupport =3D (Cr4.Bits.LA57 !=3D 0); >=20 > + ASSERT (PcdGetBool (PcdUse5LevelPageTable) =3D=3D Page5LevelSupport); >=20 > + >=20 > + Page1GSupport =3D FALSE; >=20 > + if (PcdGetBool (PcdUse1GPageTable)) { >=20 > + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); >=20 > + if (RegEax >=3D 0x80000001) { >=20 > + AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx); >=20 > + if ((RegEdx & BIT26) !=3D 0) { >=20 > + Page1GSupport =3D TRUE; >=20 > + } >=20 > + } >=20 > + } >=20 > + >=20 > + if (Page5LevelSupport && Page1GSupport) { >=20 > + return Paging5Level1GB; >=20 > + } else if (Page5LevelSupport) { >=20 > + return Paging5Level; >=20 > + } else if (Page1GSupport) { >=20 > + return Paging4Level1GB; >=20 > + } else { >=20 > + return Paging4Level; >=20 > + } >=20 > +} >=20 > + >=20 > /** >=20 > - Enable PAE Page Table. >=20 > + Enable Page Table. >=20 >=20 >=20 > - @retval EFI_SUCCESS The PAE Page Table was enabled success= fully. >=20 > - @retval EFI_OUT_OF_RESOURCES The PAE Page Table could not be enable= d > due to lack of available memory. >=20 > + @param LongMode Whether the execution mode is 64 bit >=20 > + >=20 > + @retval EFI_SUCCESS The Page Table was enabled successfull= y. >=20 > + @retval EFI_OUT_OF_RESOURCES The Page Table could not be enabled > due to lack of available memory. >=20 >=20 >=20 > **/ >=20 > +STATIC >=20 > EFI_STATUS >=20 > -EnablePaePageTable ( >=20 > - VOID >=20 > +EnablePageTable ( >=20 > + IN BOOLEAN LongMode >=20 > ) >=20 > { >=20 > EFI_STATUS Status; >=20 > @@ -369,6 +444,8 @@ EnablePaePageTable ( > UINTN BufferSize; >=20 > IA32_MAP_ATTRIBUTE MapAttribute; >=20 > IA32_MAP_ATTRIBUTE MapMask; >=20 > + PAGING_MODE PagingMode; >=20 > + UINT64 Length; >=20 >=20 >=20 > PageTable =3D 0; >=20 > Buffer =3D NULL; >=20 > @@ -378,10 +455,28 @@ EnablePaePageTable ( > MapAttribute.Bits.Present =3D 1; >=20 > MapAttribute.Bits.ReadWrite =3D 1; >=20 >=20 >=20 > - // >=20 > - // 1:1 map 4GB in 32bit mode >=20 > - // >=20 > - Status =3D PageTableMap (&PageTable, PagingPae, 0, &BufferSize, 0, SIZ= E_4GB, > &MapAttribute, &MapMask, NULL); >=20 > + if (!LongMode) { >=20 > + // >=20 > + // 1:1 map 4GB in 32bit mode >=20 > + // >=20 > + PagingMode =3D PagingPae; >=20 > + Length =3D SIZE_4GB; >=20 > + } else { >=20 > + PagingMode =3D GetPagingMode (); >=20 > + Length =3D LShiftU64 (1, GetPhysicalAddressBits ()); >=20 > + } >=20 > + >=20 > + Status =3D PageTableMap ( >=20 > + &PageTable, >=20 > + PagingMode, >=20 > + 0, >=20 > + &BufferSize, >=20 > + 0, >=20 > + Length, >=20 > + &MapAttribute, >=20 > + &MapMask, >=20 > + NULL >=20 > + ); >=20 > ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); >=20 > if (Status !=3D EFI_BUFFER_TOO_SMALL) { >=20 > return Status; >=20 > @@ -398,12 +493,23 @@ EnablePaePageTable ( >=20 >=20 > DEBUG (( >=20 > DEBUG_INFO, >=20 > - "EnablePaePageTable: Created PageTable =3D 0x%x, BufferSize =3D %x\n= ", >=20 > + "%a: Created PageTable =3D 0x%x, BufferSize =3D %x\n", >=20 > + __func__, >=20 > PageTable, >=20 > BufferSize >=20 > )); >=20 >=20 >=20 > - Status =3D PageTableMap (&PageTable, PagingPae, Buffer, &BufferSize, 0= , > SIZE_4GB, &MapAttribute, &MapMask, NULL); >=20 > + Status =3D PageTableMap ( >=20 > + &PageTable, >=20 > + PagingMode, >=20 > + Buffer, >=20 > + &BufferSize, >=20 > + 0, >=20 > + Length, >=20 > + &MapAttribute, >=20 > + &MapMask, >=20 > + NULL >=20 > + ); >=20 > ASSERT_EFI_ERROR (Status); >=20 > if (EFI_ERROR (Status) || (PageTable =3D=3D 0)) { >=20 > return EFI_OUT_OF_RESOURCES; >=20 > @@ -414,15 +520,17 @@ EnablePaePageTable ( > // >=20 > AsmWriteCr3 (PageTable); >=20 >=20 >=20 > - // >=20 > - // Enable CR4.PAE >=20 > - // >=20 > - AsmWriteCr4 (AsmReadCr4 () | BIT5); >=20 > + if (!LongMode) { >=20 > + // >=20 > + // Enable CR4.PAE >=20 > + // >=20 > + AsmWriteCr4 (AsmReadCr4 () | BIT5); >=20 >=20 >=20 > - // >=20 > - // Enable CR0.PG >=20 > - // >=20 > - AsmWriteCr0 (AsmReadCr0 () | BIT31); >=20 > + // >=20 > + // Enable CR0.PG >=20 > + // >=20 > + AsmWriteCr0 (AsmReadCr0 () | BIT31); >=20 > + } >=20 >=20 >=20 > return Status; >=20 > } >=20 > @@ -557,6 +665,9 @@ MemoryDiscoveredPpiNotifyCallback ( > EDKII_MIGRATED_FV_INFO *MigratedFvInfo; >=20 > EFI_PEI_HOB_POINTERS Hob; >=20 > IA32_CR0 Cr0; >=20 > + BOOLEAN LongMode; >=20 > + >=20 > + LongMode =3D (sizeof (UINTN) =3D=3D sizeof (UINT64)); >=20 >=20 >=20 > // >=20 > // Paging must be setup first. Otherwise the exception TSS setup durin= g MP >=20 > @@ -565,7 +676,7 @@ MemoryDiscoveredPpiNotifyCallback ( > // >=20 > InitStackGuard =3D FALSE; >=20 > Hob.Raw =3D NULL; >=20 > - if (IsIa32PaeSupported ()) { >=20 > + if (LongMode || IsIa32PaeSupported ()) { >=20 > Hob.Raw =3D GetFirstGuidHob (&gEdkiiMigratedFvInfoGuid); >=20 > InitStackGuard =3D PcdGetBool (PcdCpuStackGuard); >=20 > } >=20 > @@ -575,12 +686,12 @@ MemoryDiscoveredPpiNotifyCallback ( > // is to enable paging if it is not enabled (only in 32bit mode). >=20 > // >=20 > Cr0.UintN =3D AsmReadCr0 (); >=20 > - if ((Cr0.Bits.PG =3D=3D 0) && (InitStackGuard || (Hob.Raw !=3D NULL)))= { >=20 > - ASSERT (sizeof (UINTN) =3D=3D sizeof (UINT32)); >=20 > - >=20 > - Status =3D EnablePaePageTable (); >=20 > + if (LongMode || >=20 > + ((Cr0.Bits.PG =3D=3D 0) && (InitStackGuard || (Hob.Raw !=3D NULL))= )) >=20 > + { >=20 > + Status =3D EnablePageTable (LongMode); >=20 > if (EFI_ERROR (Status)) { >=20 > - DEBUG ((DEBUG_ERROR, "MemoryDiscoveredPpiNotifyCallback: Failed to > enable PAE page table: %r.\n", Status)); >=20 > + DEBUG ((DEBUG_ERROR, "%a: Failed to enable page table: %r.\n", > __func__, Status)); >=20 > CpuDeadLoop (); >=20 > } >=20 > } >=20 > -- > 2.39.2