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Content-Transfer-Encoding: quoted-printable Gerd, I agree that the logic might be duplicated in multi places. But even CPU supports 1G paging, caller can decide whether to use 1G paging= or 2M paging, or 4K paging. Using a single API to encapsulate the entire logic may not seem flexible. Maybe, a lib API to detect 1G paging capability can be added to CpuLib. Thanks, Ray ________________________________ From: Gerd Hoffmann Sent: Monday, May 13, 2024 19:07 To: Tan, Dun Cc: devel@edk2.groups.io ; Ni, Ray = ; Laszlo Ersek ; Kumar, Rahul R ; Wu, Jiaxin Subject: Re: [PATCH 10/18] UefiCpuPkg:Relocate AP to new safe buffer in Pei= MpLib Hi, > + if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { > + // > + // Check Page5Level Support or not. > + // > + Cr4.UintN =3D AsmReadCr4 (); > + Page5LevelSupport =3D (Cr4.Bits.LA57 ? TRUE : FALSE); > + > + // > + // Check Page1G Support or not. > + // > + Page1GSupport =3D FALSE; > + AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); > + if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) { > + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx.Uint32= ); > + if (RegEdx.Bits.Page1GB !=3D 0) { > + Page1GSupport =3D TRUE; > + } > + } > + > + // > + // Decide Paging Mode according Page5LevelSupport & Page1GSupport. > + // > + if (Page5LevelSupport) { > + PagingMode =3D Page1GSupport ? Paging5Level1GB : Paging5Level; > + } else { > + PagingMode =3D Page1GSupport ? Paging4Level1GB : Paging4Level; > + } > + } else { > + PagingMode =3D PagingPae; > + } I'm wondering whenever CpuPageTableLib should get a function for this? I suspect there a multiple places in edk2 which will need this functionality ... take care, Gerd -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#118880): https://edk2.groups.io/g/devel/message/118880 Mute This Topic: https://groups.io/mt/106018135/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_MN6PR11MB8244F24D892B0EA45D7BA5328CE32MN6PR11MB8244namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Gerd,
I agree that the logic might be duplicated in multi places.

But even CPU supports 1G paging, caller can decide whether to use 1G paging= or 2M paging, or 4K paging.
Using a single API to encapsulate the entire logic may not seem flexible.
Maybe, a lib API to detect 1G paging capability can be added to CpuLib.

Thanks,
Ray
From: Gerd Hoffmann <kra= xel@redhat.com>
Sent: Monday, May 13, 2024 19:07
To: Tan, Dun <dun.tan@intel.com>
Cc: devel@edk2.groups.io <devel@edk2.groups.io>; Ni, Ray <r= ay.ni@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kumar, Rahul R= <rahul.r.kumar@intel.com>; Wu, Jiaxin <jiaxin.wu@intel.com> Subject: Re: [PATCH 10/18] UefiCpuPkg:Relocate AP to new safe buffer= in PeiMpLib
 
  Hi,

> +  if (sizeof (UINTN) =3D=3D sizeof (UINT64)) {
> +    //
> +    // Check Page5Level Support or not.
> +    //
> +    Cr4.UintN       = ;  =3D AsmReadCr4 ();
> +    Page5LevelSupport =3D (Cr4.Bits.LA57 ? TRUE : FALS= E);
> +
> +    //
> +    // Check Page1G Support or not.
> +    //
> +    Page1GSupport =3D FALSE;
> +    AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NU= LL, NULL, NULL);
> +    if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) {
> +      AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL= , NULL, NULL, &RegEdx.Uint32);
> +      if (RegEdx.Bits.Page1GB !=3D 0) {
> +        Page1GSupport =3D TRUE; > +      }
> +    }
> +
> +    //
> +    // Decide Paging Mode according Page5LevelSupport = & Page1GSupport.
> +    //
> +    if (Page5LevelSupport) {
> +      PagingMode =3D Page1GSupport ? Paging5= Level1GB : Paging5Level;
> +    } else {
> +      PagingMode =3D Page1GSupport ? Paging4= Level1GB : Paging4Level;
> +    }
> +  } else {
> +    PagingMode =3D PagingPae;
> +  }

I'm wondering whenever CpuPageTableLib should get a function for this?
I suspect there a multiple places in edk2 which will need this
functionality ...

take care,
  Gerd

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