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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Sai Chaganty -----Original Message----- From: Hsu, WesleyX =20 Sent: Thursday, July 29, 2021 12:23 AM To: devel@edk2.groups.io Cc: Hsu, WesleyX ; Chan, Amy ; Y= eh, HerbX ; Peng, NickX ; Ni, Ra= y ; Chaganty, Rangasai V Subject: [PATCH v2] IntelSiliconPkg/VTd: Fix variables may be used uninitia= lized REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3491 Initialize several variables which may be used uninitialized after adding "= -ffat-lto-objects" option in GCC5 tool chain. Change-Id: Ib2684aa70637d449f8bbddb18cf0a458a2742909 Signed-off-by: WesleyX Hsu Cc: Amy Chan Cc: HerbX Yeh Cc: NickX Peng Cc: Ray Ni Cc: Rangasai V Chaganty --- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable= .c | 7 ++++++- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c = | 9 +++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Tran= slationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/= TranslationTable.c index 341e2beb..6676b2a9 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translation= Table.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translat +++ ionTable.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2020 - 2021, Intel Corporation. All rights=20 + reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -111,6 +111,11 @@ CreateSecondLevelPagingEntryTable ( return EFI_SUCCESS; } =20 + Lvl4PagesStart =3D 0; + Lvl4PagesEnd =3D 0; + Lvl4PtEntry =3D NULL; + Lvl5PtEntry =3D NULL; + BaseAddress =3D ALIGN_VALUE_LOW (MemoryBase, SIZE_2MB); EndAddress =3D ALIGN_VALUE_UP (MemoryLimit, SIZE_2MB); DEBUG ((DEBUG_INFO, "CreateSecondLevelPagingEntryTable: BaseAddress - 0x= %016lx, EndAddress - 0x%016lx\n", BaseAddress, EndAddress)); diff --git a/S= ilicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/S= ilicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c index d152039f..ca5f65a8 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= e.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationT +++ able.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights=20 + reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -133,7 +133,7 @@ CreateContextEntry ( mVtdUnitInformation[VtdIndex].Is5LevelPaging =3D TRUE; if ((mAcpiDmarTable->HostAddressWidth <=3D 48) && ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) !=3D 0= )) { - mVtdUnitInformation[VtdIndex].Is5LevelPaging =3D FALSE; + mVtdUnitInformation[VtdIndex].Is5LevelPaging =3D FALSE; } } else if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) = =3D=3D 0) { DEBUG((DEBUG_ERROR, "!!!! Page-table type is not supported on VTD %d= !!!!\n", VtdIndex)); @@ -199,6 +199,11 @@ CreateSecondLevelPagingEntryTabl= e ( return EFI_SUCCESS; } =20 + Lvl4PagesStart =3D 0; + Lvl4PagesEnd =3D 0; + Lvl4PtEntry =3D NULL; + Lvl5PtEntry =3D NULL; + BaseAddress =3D ALIGN_VALUE_LOW(MemoryBase, SIZE_2MB); EndAddress =3D ALIGN_VALUE_UP(MemoryLimit, SIZE_2MB); DEBUG ((DEBUG_INFO,"CreateSecondLevelPagingEntryTable: BaseAddress - 0x%= 016lx, EndAddress - 0x%016lx\n", BaseAddress, EndAddress)); -- 2.32.0.windows.2